AD7329_技术文档

1 MSPS, 8-Channel, Software-Selectable,

True Bipolar Input, 12-Bit Plus Sign ADC

AD7329

FUNCTIONAL BLOCK DIAGRAM

FEATURES

MUX

+

MUX

–

REF /REF

ADC

–

ADC

+

V

OUT

IN OUT

IN

DD

CC

12-bit plus sign SAR ADC

True bipolar input ranges

2.5V

VREF

Software-selectable input ranges

10 V, 5 V, 2.5 V, 0 V to +10 V

1 MSPS throughput rate

Eight analog input channels with channel sequencer

Single-ended true differential and pseudo differential

analog input capability

V

0

1

2

3

4

5

IN

13-BIT SUCCESSIVE

APPROXIMATION

ADC

I/P

MUX

T/H

V

6

7

IN

DOUT

SCLK

High analog input impedance

MUX_OUTand ADC_INpins allow separate access to mux and ADC

Low power: 21 mW

Temperature indicator

Full power signal bandwidth: 20 MHz

Internal 2.5 V reference

CONTROL

LOGIC AND

REGISTERS

CHANNEL

SEQUENCER

CS

DIN

AD7329

V

AGND

V

DRIVE

SS

Figure 1.

High speed serial interface

iCMOS™ process technology

24-lead TSSOP package

Power-down modes

GENERAL DESCRIPTION

The AD7329¹is an 8-channel, 12-bit plus sign successive

approximation ADC designed on the iCMOS (industrial

CMOS) process. iCMOS is a process combining high voltage

CMOS and low voltage CMOS. It enables the development of

a wide range of high performance analog ICs capable of 33 V

operation in a footprint that no previous generation of high

voltage parts could achieve. Unlike analog ICs using conventional

CMOS processes, iCMOS components can accept bipolar input

signals while providing increased performance, dramatically

reduced power consumption, and reduced package size.

PRODUCT HIGHLIGHTS

1. The AD7329 can accept true bipolar analog input signals,

±1ꢀ V, ±± V, ±2.± V, and ꢀ V to +1ꢀ V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential input pairs, four pseudo

differential inputs, or seven pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 21 mW, at 1 MSPS.

The AD7329 can accept true bipolar analog input signals. The

AD7329 has four software-selectable input ranges, ±1ꢀ V, ±± V,

±2.± V, and ꢀ V to +1ꢀ V. Each analog input channel can be

independently programmed to one of the four input ranges.

The analog input channels on the AD7329 can be programmed

to be single-ended, true differential, or pseudo differential.

±. MUX_OUTand ADC_INpins allow for signal conditioning of

the mux output prior to entering the ADC.

Table 1. Similar Devices

Device

Number

AD7328

AD7327

AD7324

AD7323

AD7322

AD7321

Throughput Rate

1000 kSPS

500 kSPS

1000 kSPS

500 kSPS

Number of Channels

8

4

2

The ADC contains a 2.± V internal reference. The AD7329 also

allows for external reference operation. If a 3 V reference is

applied to the REF_IN/REF_OUTpin, the AD7329 can accept a true

bipolar ±12 V analog input. The ADC has a high speed serial

interface that can operate at throughput rates up to 1 MSPS.

1000 kSPS

500 kSPS

¹Protected by U.S. Patent No. 6,731,232.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights ofthird parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7329

TABLE OF CONTENTS

Features .............................................................................................. 1

Registers........................................................................................... 2±

Addressing Registers.................................................................. 2±

Control Register ......................................................................... 26

Sequence Register....................................................................... 28

Range Registers........................................................................... 28

Sequencer Operation ..................................................................... 29

Reference ..................................................................................... 31

V_DRIVE............................................................................................ 31

Temperature Indicator............................................................... 31

Modes of Operation ....................................................................... 32

Normal Mode.............................................................................. 32

Full Shutdown Mode.................................................................. 32

Autoshutdown Mode ................................................................. 33

Autostandby Mode..................................................................... 33

Power vs. Throughput Rate....................................................... 34

Serial Interface ................................................................................ 3±

Microprocessor Interfacing........................................................... 36

AD7329 to ADSP-21xx.............................................................. 36

AD7329 to ADSP-BF±3x........................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 1±

Theory of Operation ...................................................................... 17

Circuit Information.................................................................... 17

Converter Operation.................................................................. 17

Output Coding............................................................................ 18

Transfer Functions...................................................................... 18

Analog Input Structure.............................................................. 18

Track-and-Hold Section............................................................ 19

Typical Connection Diagram ................................................... 2ꢀ

Analog Input ............................................................................... 2ꢀ

Driver Amplifier Choice............................................................ 23

REVISION HISTORY

4/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD7329

SPECIFICATIONS

V_DD= 12 V to 16.± V, V_SS= −12 V to −16.± V, V_CC= 4.7± V to ±.2± V, V_DRIVE= 2.7 V to ±.2± V, V_REF= 2.± V internal/external, f_SCLK= 2ꢀ

MHz, f_S= 1 MSPS, T_A= T_MAXto T_MIN, unless otherwise noted. MUX_OUT+ is connected directly to ADC_IN+ and MUX_OUT−is connected

directly to ADC_IN−, which is connected to GND for single-ended mode.

Table 2.

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

f_IN= 50 kHz sine wave

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)²

76

72.5

75

77

74

76.5

dB

Differential mode

Single-ended/pseudo differential mode

Differential mode; 2.5 V and 5 V ranges

Signal-to-Noise + Distortion

(SINAD)²

76.5

73.5

dB

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode; 2.5 V and

5 V ranges

72

73.5

dB

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

Total Harmonic Distortion (THD)²

−87

−85

−82

−80

−77

dB

Differential mode; 2.5 V and 5 V ranges

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode; 2.5 V and

5 V ranges

−80

−88

dB

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

Differential mode; 2.5 V and 5 V ranges

Peak Harmonic or Spurious

Noise (SFDR)²

−80

−78

−86

−84

dB

Differential mode; 0 V to +10 V and 10 V ranges

Single-ended/pseudo differential mode; 2.5 V and

5 V ranges

−82

dB

Single-ended/pseudo differential mode; 0 V to +10 V

and 10 V ranges

Intermodulation Distortion

(IMD) ²

fa = 50 kHz, fb = 30 kHz

Second-Order Terms

Third-Order Terms

Aperture Delay³

Aperture Jitter³

−88

−90

7

50

−79

dB

ns

ps

dB

Common-Mode Rejection

Up to 100 kHz ripple frequency; see Figure 17

(CMRR)²

Channel-to-Channel Isolation²

Full Power Bandwidth

−75

dB

f_INon unselected channels up to 100 kHz;

see Figure 14

At 3 dB

20

1.5

MHz

At 0.1 dB

Rev. 0 | Page 3 of 40

AD7329

B Version

Typ

Parameter¹

DC ACCURACY⁴

Min

Max

Unit

Test Conditions/Comments

All dc accuracy specifications are typical for

0 V to 10 V mode.

Resolution

No Missing Codes

13

12-bit

Bits

Differential mode

plus sign

11-bit

Bits

Single-ended/pseudo differential mode

plus sign

Integral Nonlinearity²

1.1

1

LSB

Differential mode

Single-ended/pseudo differential mode

(LSB = FSR/8192)

−0.7/+1.2

−0.7/+1

Differential Nonlinearity²

−0.9/+1.5 LSB

Differential mode; guaranteed no missing codes to

13 bits

Single-ended mode; guaranteed no missing codes to

12 bits

Single-ended/psuedo differential mode

(LSB = FSR/8192)

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

Single-ended/pseudo differential mode

Differential mode

0.9

LSB

Offset Error^{2, 5}

−4/+9

−7/+10

0.6

0.5

8.0

14

0.5

4

LSB

Offset Error Match^{2, 5}

Gain Error^{2, 5}

Gain Error Match^{2, 5}

Positive Full-Scale Error^{2, 6}

Positive Full-Scale Error Match^{2, 6}

Bipolar Zero Error^{2, 6}

7

0.5

8.5

7.5

0.5

4

6

0.5

Bipolar Zero Error Match^{2, 6}

Negative Full-Scale Error^{2, 6}

Negative Full-Scale Error Match^{2, 6}

Single-ended/pseudo differential mode

Differential mode

Rev. 0 | Page 4 of 40

AD7329

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

ANALOG INPUT

Input Voltage Ranges

Reference = 2.5 V; see Table 6

(Programmed via Range

Register)

10

V

V_DD= 10 V min, V_SS= −10 V min, V_CC= 2.7 V to 5.25 V

5

2.5

0 to 10

V

V_DD= 5 V min, V_SS= −5 V min, V_CC= 2.7 V to 5.25 V

V_DD= 5 V min, V_SS= − 5 V min, V_CC= 2.7 V to 5.25 V

V_DD= 10 V min, V_SS= AGND min, V_CC= 2.7 V to 5.25 V

Pseudo Differential V_IN−

Input Range

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5 V; see Figure 43 and

Figure 44

3.5

6

5

V

Reference = 2.5 V; range = 10 V

Reference = 2.5 V; range = 5 V

Reference = 2.5 V; range = 2.5 V

Reference = 2.5 V; range = 0 V to +10 V

V_IN= V_DDor V_SS

+3/−5

DC Leakage Current

100

nA

pF

3

Per channel, V_IN= V_DDor V_SS

Input Capacitance³

ADC_INCapacitance³

16

7

When in track, all ranges, single ended

When in track, 10 V range, single ended

When in track, 5 V range, single ended

When in track, 2.5 V range, single ended

When in track, 0 V to +10 V range, single ended

When in hold, all ranges, single ended

All ranges, single ended

10

14.5

10.5

4.0

7.5

13

MUX_OUT− Capacitance³

MUX_OUT+ Capacitance³

REFERENCE INPUT/OUTPUT

Input Voltage Range

Input DC Leakage Current

Input Capacitance

All ranges, single ended

2.5

3

1

V

μA

pF

V

10

2.5

Reference Output Voltage

Reference Output Voltage Error

@ 25°C

Reference Output Voltage

T_MINto T_MAX

Reference Temperature

Coefficient

5

10

25

mV

ppm/°C

3

7

ppm/°C

Ω

Reference Output Impedance

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

2.4

V

μA

pF

0.8

0.4

1

V_CC= 4.75 V to 5.25 V

V_CC= 2.7 to 3.6 V

V_IN= 0 V or V_DRIVE

Input Current, I_IN

3

Input Capacitance, C_IN

10

LOGIC OUTPUTS

Output High Voltage, V_OH

V_DRIVE

0.2 V

−

V

I_SOURCE= 200 μA

I_SINK= 200 μA

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output

Capacitance³

0.4

1

V

μA

pF

5

Output Coding

Straight natural binary

Twos complement

Coding bit set to 1 in control register

Coding bit set to 0 in control register

Rev. 0 | Page 5 of 40

AD7329

B Version

Typ

Parameter¹

Min

Max

Unit

Test Conditions/Comments

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition

Time^{2, 3}

800

300

ns

16 SCLK cycles with SCLK = 20 MHz

Full-scale step input; see the Terminology section

Throughput Rate

1

770

MSPS

kSPS

See the Serial Interface section; V_CC= 4.75 V to 5.25 V

V_CC< 4.75 V

POWER REQUIREMENTS

V_DD

V_SS

V_CC

Digital inputs = 0 V or V_DRIVE

See Table 6

12

16.5

−16.5

5.25

V

−12

2.7

See Table 6; typical specifications for V_CC< 4.75 V

V_DRIVE

Normal Mode (Static)

Normal Mode (Operational)

I_DD

I_SS

I_CCand I_DRIVE

Autostandby Mode (Dynamic)

I_DD

I_SS

0.9

mA

V_DD= 16.5, V_SS= −16.5 V, V_CC= V_DRIVE= 5.25 V

f_SAMPLE= 1 MSPS

V_DD= 16.5 V

360

410

3.2

μA

mA

V_SS= −16.5 V

V_CC= V_DRIVE= 5.25 V

f_SAMPLE= 250 kSPS

V_DD= 16.5 V

V_SS= −16.5 V

V_CC= V_DRIVE= 5.25 V

SCLK on or off

200

210

1.3

μA

mA

I_CCand I_DRIVE

Autoshutdown Mode (Static)

I_DD

I_SS

1

μA

V_DD= 16.5 V

V_SS= −16.5 V

V_CC= V_DRIVE= 5.25 V

SCLK on or off

V_DD= 16.5 V

I_CCand I_DRIVE

Full Shutdown Mode

I_DD

1

μA

I_SS

V_SS= −16.5 V

V_CC= V_DRIVE= 5.25 V

I_CCand I_DRIVE

POWER DISSIPATION

Normal Mode (Operational)

30

mW

μW

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5.25 V

V_DD= 12 V, V_SS= −12 V, V_CC= 5 V

V_DD= 16.5 V, V_SS= −16.5 V, V_CC= 5.25 V

21

Full Shutdown Mode

38.25

¹Temperature range is −40°C to +85°C.

²See the Terminology section.

³Sample tested during initial release to ensure compliance.

⁴For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

⁵Unipolar 0 V to 10 V range with straight binary output coding.

⁶Bipolar range with twos complement output coding.

Rev. 0 | Page 6 of 40

AD7329

TIMING SPECIFICATIONS

V_DD= 12 V to 16.± V, V_SS= −12 V to −16.± V, V_CC= 4.7± V to ±.2± V, V_DRIVE= 2.7 V to ±.2± V, V_REF= 2.± V internal/external, T_A= T_MAXto

T_MIN. Timing specifications apply with a 32 pF load, unless otherwise noted. MUX_OUT+ is connected directly to ADC_IN+ and MUX_OUT−is

connected directly to ADC_IN−, which is connected to GND for single-ended mode.

Table 3.

Limit at T_MIN, T_MAX

Description

V_DRIVE≤ V_CC

Parameter V_CC< 4.75 V V_CC= 4.75 V to 5.25 V Unit

f_SCLK

50

14

16 × t_SCLK

75

50

20

16 × t_SCLK

60

kHz min

MHz max

ns max

ns min

ns max

ns min

ns max

ns min

ns max

μs max

t_CONVERT

t_QUIET

t₁

t_SCLK= 1/f_SCLK

Minimum time between end of serial read and next falling edge of CS

Minimum CS pulse width

12

5

1

t₂

25

20

CS to SCLK set-up time; bipolar input ranges ( 10 V, 5 V, 2.5 V)

Unipolar input range (0 V to 10 V)

Delay from CS until DOUT three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

45

26

35

14

t₃

t₄

t₅

t₆

t₇

t₈

57

0.4 × t_SCLK

13

40

10

4

2

750

500

43

0.4 × t_SCLK

8

22

9

4

2

750

500

SCLK high pulse width

SCLK to data valid hold time

SCLK falling edge to DOUT high impedance

DIN set-up time prior to SCLK falling edge

DIN hold time after SCLK falling edge

Power-up from autostandby

t₉

t₁₀

t_POWER-UP

Power-up from full shutdown/autoshutdown mode, internal

reference

25

μs typ

Power-up from full shutdown/autoshutdown mode, external

reference

¹When using V_CC= 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t₂at 20 ns, the mark space ratio needs to be limited to 50:50.

t₁

CS

t_CONVERT

t₂

t₆

1

2

3

4

5

13

14

t₅

15

16

SCLK

DOUT

3 IDENTIFICATION BITS

t₃

t₇

t₈

t₄

t_QUIET

ADD1

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

THREE-

STATE

ADD2

THREE-STATE

t₁₀

t₉

REG

SEL1

REG

SEL2

WRITE

MSB

LSB

0

DIN

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 7 of 40

AD7329

ABSOLUTE MAXIMUM RATINGS

T_A= 2±°C, unless otherwise noted

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto AGND, DGND

V_SSto AGND, DGND

V_DDto V_CC

V_CCto AGND, DGND

V_DRIVEto AGND, DGND

AGND to DGND

Analog Input Voltage to AGND¹

Digital Input Voltage to DGND

Digital Output Voltage to GND

REF_INto AGND

Input Current to Any Pin

Except Supplies²

−0.3 V to +16.5 V

+0.3 V to −16.5 V

V_CC− 0.3 V to +16.5 V

−0.3 V to +7 V

−0.3 V to +0.3 V

V_SS− 0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to V_CC+ 0.3 V

10 mA

Operating Temperature Range

Storage Temperature Range

Junction Temperature

TSSOP Package

−40°C to +85°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Pb-Free Temperature, Soldering

Reflow

128°C/W

42°C/W

260(0)°C

2.5 kV

ESD

¹If the analog inputs are being driven from alternative V_DDand V_SSsupply

circuitry, Schottky diodes should be placed in series with the AD7329’s V_DD

and V_SSsupplies.

²Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 8 of 40

AD7329

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

24

23

22

21

20

19

18

17

16

15

14

13

CS

SCLK

DGND

DOUT

2

DIN

3

DGND

AGND

4

V

DRIVE

CC

AD7329

TOP VIEW

(Not to Scale)

5

REF /REF

IN OUT

6

V

SS

DD

7

ADC

+

ADC

–

IN

8

MUX

–

OUT

9

V

0

1

4

5

V

2

3

6

7

IN

10

11

12

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Descriptions

24

SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329.

This clock is also used as the clock source for the conversion process.

22

DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are

clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data

stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is

provided MSB first (see the Serial Interface section).

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7329 and frames the serial data transfer.

2

DIN

V_DRIVE

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register

on the falling edge of SCLK (see the Registers section).

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

This pin should be decoupled to DGND. The voltage at this pin can be different than that at V_CCbut should

not exceed V_CCby more than 0.3 V.

21

3, 23

4

DGND

AGND

Digital Ground. Ground reference point for all digital circuitry on the AD7329. The DGND and AGND voltages

ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and

any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally

should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

5

REF_IN/REF_OUTReference Input/Reference Output. The on-chip reference is available on this pin for use external to the

AD7329. Alternatively, the internal reference can be disabled and an external reference applied to this input.

On power up, this is the default condition. The nominal internal reference voltage is 2.5 V, which appears at

this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section).

20

V_CC

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. This supply

should be decoupled to AGND.

19

6

V_DD

V_SS

Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.

Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.

7

ADC_IN+

Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still

a high voltage signal ( 10 V, 5 V, 2.5 V, or 0 V to +10 V).

8

MUX_OUT

+

Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a

high voltage signal equivalent to the voltage applied to the V_IN+ input channel, as selected in the control

register or sequence register. If no external filtering or buffering is required, this pin should be tied to the

ADC_IN+ pin.

Rev. 0 | Page 9 of 40

AD7329

Pin No.

Mnemonic

Descriptions

17

MUX_OUT

−

Negative Multiplexer Output. This pin allows access to the on-chip track-and-hold. The voltage applied to this

pin is still a high voltage signal when the AD7329 is in differential mode. When the AD7329 is in single-ended

mode, this signal is AGND, and MUX_OUT− can be connected directly to the ADC_IN− pin. When the AD7329 is in

pseudo differential mode, a small dc voltage appears at this pin, and this pin should be tied to the ADC_IN− pin.

18

ADC_IN−

Negative ADC Input. This pin allows access to the track-and-hold. When the AD7329 is in single-ended mode,

this pin can be tied to MUX_OUT−, which is connected to AGND. When the AD7329 is in pseudo differential

mode, this pin should be connected to MUX_OUT−. When the AD7329 is in true differential mode, the voltage

applied to this pin is a high voltage signal ( 10 V, 5 V, 2.5 V, or 0 V to +10 V).

9 to 16

V_IN0 to V_IN7

Analog Input 0 Through Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.

The analog input channel for conversion is selected by programming the channel address bits, ADD2

through ADD0, in the control register. The inputs can be configured as eight single-ended inputs, four true

differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration

of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0, in the control register.

The input range on each input channel is controlled by programming the range registers. Input ranges of

10 V, 5 V, 2.5 V, or 0 V to +10 V can be selected on each analog input channel (see the Range Registers

section). On power up, V_IN0 is automatically selected and the voltage on this pin appears on MUX_OUT+.

Rev. 0 | Page 10 of 40

AD7329

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0

V

T

= V

DRIVE

= 5V

INT/EXT 2.5V REFERENCE

±10V RANGE

4096 POINT FFT

CC

= 25°C

V

= V = 5V

= 15V, V = –15V

SS

= 25°C

A

CC

DD

DRIVE

V

= 15V, V = –15V +INL = +0.55LSB

–20

–40

DD

SS

–INL = –0.68LSB

0.6

T

A

INT/EXT 2.5V REFERENCE

±10V RANGE

0.4

f_IN= 50kHz

SNR = 77.30dB

0.2

–60

SINAD = 76.85dB

THD = –86.96dB

SFDR = –88.22dB

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

512

1536

2560

4608

5632

6656

7680

Figure 4. FFT True Differential Mode

Figure 7. Typical INL True Differential Mode

1.0

0.8

0

–20

4096 POINT FFT

V

= V = 5V

= 15V, V = –15V

SS

CC

DD

DRIVE

0.6

T

= 25°C

A

INT/EXT 2.5V REFERENCE

±10V RANGE

–40

0.4

f_IN= 50kHz

SNR = 74.67dB

0.2

–60

SINAD = 74.03dB

THD = –82.68dB

SFDR = –85.40dB

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

V

= V

DRIVE

= 25°C

= 5V

±10V RANGE

+DNL = +0.79LSB

–DNL = –0.38LSB

CC

T

A

V

= 15V, V = –15V

DD

INT/EXT 2.5V REFERENCE

SS

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

512 1536

2560

4608

5632

6656

7680

Figure 5. FFT Single-Ended Mode

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

V

= V = 5V

DRIVE

CC

= 25°C

V

= V = 5V

DRIVE

CC

= 25°C

T

A

T

A

V

= 15V, V = –15V

DD

SS

V

= 15V, V = –15V

DD

SS

INT/EXT 2.5V REFERENCE

±10V RANGE

+DNL = +0.72LSB

–DNL = –0.22LSB

INT/EXT 2.5V REFERENCE

±10V RANGE

+INL = +0.87LSB

–INL = –0.49LSB

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

0

1024

2048

3072

3584

CODE

4096

5120

6144

7168

8192

512

1536 2560

4608

5632

6656

7680

512 1536

2560

4608

5632

6656

7680

Figure 6. Typical DNL True Differential Mode

Figure 9. Typical INL Single-Ended Mode

Rev. 0 | Page 11 of 40

AD7329

–50

V

80

75

70

65

60

55

50

= V

DRIVE

= 5V

CC

DD

V

= 12V, V = –12V

SS

–55

T

= 25°C

f_S^A= 1MSPS

±2.5V RANGE

–60

–65

–70

–75

–80

–85

–90

–95

INTERNAL REFERENCE

AD8021 BETWEEN MUX

OUT+

±10V RANGE

AND ADC

PINS

IN+

±5V RANGE

±10V RANGE

±5V RANGE

0V TO +10V RANGE

V

T

= V = 5V

DRIVE

CC

DD

= 12V, V = –12V

SS

= 25°C

f_S^A= 1MSPS

±2.5V RANGE

INTERNAL REFERENCE

AD8021 BETWEEN MUX

OUT

AND ADC PINS

IN

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

Figure 10. THD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V V_CC

Figure 13. SINAD vs. Analog Input Frequency for True Differential Mode (Diff)

at 5 V V_CC

–50

–55

V

T

= V = 5V

DRIVE

CC

DD

= 12V, V = –12V

SS

±10V RANGE

±5V RANGE

–55

–60

–65

–70

–75

–80

–85

–90

–95

= 25°C

f_S^A= 1MSPS

WIRE LINK

–60

INTERNAL REFERENCE

AD8021 BETWEEN MUX

AND ADC PINS

OUT

–65

–70

–75

–80

–85

–90

–95

–100

WITH AD8021

IN

0V TO +10V RANGE

±2.5V RANGE

V

= 12V, V = –12V

SS

DD

CC

= V

= 5V

DRIVE

SINGLE-ENDED MODE

50kHz ON SELECTED CHANNEL

f_S= 1MSPS

T

= 25°C

A

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

0

100

200

300

400

500

600

FREQUENCY OF INPUT NOISE (kHz)

Figure 11. THD vs. Analog Input Frequency for True Differential Mode (Diff) at

5 V V_CC

Figure 14. Channel-to-Channel Isolation with and Without AD8021 Between

the MUX_OUT+ and ADC_IN+ Pins

74

10k

9469

V

= 5V

CC

DD

9k

8k

7k

6k

5k

4k

3k

2k

1k

0

= 12V, V = –12V

SS

73

RANGE = ±10V

10k SAMPLES

±2.5V RANGE

±5V RANGE

72

71

70

69

68

67

66

T

= 25°C

A

0V TO +10V RANGE

±10V RANGE

V

T

= V = 5V

DRIVE

CC

DD

= 12V, V = –12V

SS

= 25°C

f_S^A= 1MSPS

INTERNAL REFERENCE

AD8021 BETWEEN MUX

OUT+

228

–1

303

1

0

2

AND ADC

PINS

IN+

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

–2

0

CODE

Figure 12. SINAD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V V_CC

Figure 15. Histogram of Codes, True Differential Mode

Rev. 0 | Page 12 of 40

AD7329

2.0

1.5

8k

7k

6k

5k

4k

3k

2k

1k

0

7600

V

= 5V

CC

DD

= 12V, V = –12V

SS

RANGE = ±10V

10k SAMPLES

INL = 1MSPS

1.0

T

= 25°C

A

0.5

INL = 500kSPS

0

–0.5

–1.0

–1.5

–2.0

INL = 1MSPS

±5V RANGE

= V

V

= 5V

DRIVE

CC

INTERNAL REFERENCE

SINGLE-ENDED MODE

AD8021 BETWEEN MUX

1201

–1

1165

1

+

OUT

AND ADC + PINS

0

23

–2

11

2

0

3

IN

±5

±7

±9

±11

±13

±15

±17

±19

–3

0

SUPPLY VOLTAGE (V) (V = +, V = –)

DD SS

CODE

Figure 19. INL Error vs. Supply Voltage at 500 kSPS and 1 MSPS

Figure 16. Histogram of Codes, Single-Ended Mode

–50

100mV p-p SINE WAVE ON EACH SUPPLY

–55 NO DECOUPLING

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

SINGLE-ENDED MODE

f

= 1MSPS

S

–60

–65

–70

–75

–80

–85

–90

–95

–100

V

= 5V

CC

V

= 3V

CC

V

= 5V

CC

= 12V

DD

V

= 3V

CC

DIFFERENTIAL MODE

f_IN= 50kHz

V

= –12V

SS

V

= 12V, V = –12V

SS

f_S^D=^D1MSPS

T

= 25°C

A

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

SUPPLY RIPPLE FREQUENCY (kHz)

RIPPLE FREQUENCY (kHz)

Figure 17. CMRR vs. Common-Mode Ripple Frequency

Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

2.0

1.5

–50

DIFFERENTIAL MODE

V

= 12V, V = –12V

DD

CC

SS

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

= V

DRIVE

= 5V

INTERNAL REFERENCE

AD8021 BETWEEN MUX

AND ADC PINS

IN

DNL = 500kSPS

±10V RANGE

1.0

OUT

R

= 2000Ω

= 1000Ω

= 600Ω

= 100Ω

= 50Ω

IN

0.5

DNL = 1MSPS

0

–0.5

–1.0

–1.5

–2.0

±2.5V RANGE

±5V RANGE

R

= 4000Ω

= 1000Ω

= 600Ω

= 100Ω

= 50Ω

IN

DNL = 500kSPS

V

= V = 5V

CC

DRIVE

INTERNAL REFERENCE

SINGLE-ENDED MODE

AD8021 BETWEEN MUX

+

OUT

AND ADC + PINS

IN

±5

±7

±9

±11

±13

±15

±17

±19

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

SUPPLY VOLTAGE (V) (V = +, V = –)

DD SS

Figure 18. DNL Error vs. Supply Voltage at 500 kSPS and 1 MSPS

Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,

True Differential Mode

Rev. 0 | Page 13 of 40

AD7329

–76

–78

–80

–82

–84

–86

–88

–50

±5V RANGE

= V = 5V

DRIVE

INTERNAL REFERENCE

SINGLE-ENDED MODE

AD8021 BETWEEN MUX

SINGLE-ENDED MODE

V

= 12V, V = –12V

CC

DD

CC

SS

–55

–60

–65

–70

–75

–80

–85

–90

= V

DRIVE

= 5V

INTERNAL REFERENCE

AD8021 BETWEEN MUX

AND ADC + PINS

IN

+

OUT

±10V RANGE

+

OUT

AND ADC + PINS

IN

R

= 2000Ω

IN

= 1000Ω

= 600Ω

= 100Ω

= 50Ω

30kHz/500kSPS

±2.5V RANGE

30kHz/1MSPS

10kHz/1MSPS

R

= 2000Ω

= 1000Ω

= 600Ω

= 100Ω

= 50Ω

IN

10kHz/500kSPS

±7

±5

±9

±11

±13

±15

±17

10

100

ANALOG INPUT FREQUENCY (kHz)

1000

SUPPLY VOLTAGE (V) (V = +, V = –)

DD SS

Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,

Single-Ended Mode

Figure 23. THD vs. Supply Voltage at 500 kSPS and 1 MSPS

with 10 kHz and 30 kHz Input Tone

Rev. 0 | Page 14 of 40

AD7329

TERMINOLOGY

Differential Nonlinearity

Negative Full-Scale Error

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

This applies when using twos complement output coding and

any of the bipolar analog input ranges. This is the deviation of

the first code transition (1ꢀ … ꢀꢀꢀ) to (1ꢀ … ꢀꢀ1) from the ideal

(that is, −4 × V_REF+ 1 LSB, −2 × V_REF+ 1 LSB, −V_REF+ 1 LSB)

after adjusting for the bipolar zero code error.

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale (a point 1 LSB

below the first code transition) and full scale (a point 1 LSB

above the last code transition).

Negative Full-Scale Error Match

This is the difference in negative full-scale error between any

two input channels.

Offset Code Error

Track-and-Hold Acquisition Time

This applies to straight binary output coding. It is the deviation

of the first code transition (ꢀꢀ ... ꢀꢀꢀ) to (ꢀꢀ ... ꢀꢀ1) from the

ideal, that is, AGND + 1 LSB.

The track-and-hold amplifier returns into track mode after the

14^thSCLK rising edge. Track-and-hold acquisition time is the

time required for the output of the track-and-hold amplifier to

reach its final value, within ±ꢁ LSB, after the end of a conversion.

Offset Error Match

This is the difference in offset error between any two input

channels.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at

the output of the A/D converter. The signal is the rms amplitude

of the fundamental. Noise is the sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

The ratio is dependent on the number of quantization levels in

the digitization process. The more levels, the smaller the quan-

tization noise. Theoretically, the signal to (noise + distortion) ratio

for an ideal N-bit converter with a sine wave input is given by

Gain Error

This applies to straight binary output coding. It is the deviation

of the last code transition (111 ... 11ꢀ) to (111 ... 111) from the

ideal (that is, 4 × V_REF− 1 LSB, 2 × V_REF− 1 LSB, V_REF− 1 LSB)

after adjusting for the offset error.

Gain Error Match

This is the difference in gain error between any two input

channels.

Signal to (Noise + Distortion) = (6.ꢀ2 N + 1.76) dB

For a 13-bit converter, this is 8ꢀ.ꢀ2 dB.

Bipolar Zero Code Error

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7329, it is defined as

This applies when using twos complement output coding and a

bipolar analog input. It is the deviation of the midscale transition

(all 1s to all ꢀs) from the ideal input voltage, that is, AGND − 1 LSB.

2

V₂+V₃+V₄+V_±+V₆

THD(dB) = 2ꢀ log

Bipolar Zero Code Error Match

This refers to the difference in bipolar zero code error between

any two input channels.

V₁

where V₁is the rms amplitude of the fundamental, and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Positive Full-Scale Error

This applies when using twos complement output coding and

any of the bipolar analog input ranges. It is the deviation of the

last code transition (ꢀ11 … 11ꢀ) to (ꢀ11 … 111) from the ideal

(4 × V_REF− 1 LSB, 2 × V_REF− 1 LSB, V_REF− 1 LSB) after

adjusting for the bipolar zero code error.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2, excluding dc) to the rms value of

the fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, the

largest harmonic could be a noise peak.

Positive Full-Scale Error Match

This is the difference in positive full-scale error between any

two input channels.

Rev. 0 | Page 15 of 40

AD7329

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

per the THD specification, where it is the ratio of the rms sum

of the individual distortion products to the rms amplitude of

the sum of the fundamentals expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk

between any two channels. It is measured by applying a full-scale,

1ꢀꢀ kHz sine wave signal to all unselected input channels and

determining the degree to which the signal attenuates in the

selected channel with a ±ꢀ kHz signal. Figure 14 shows the

worst-case across all eight channels for the AD7329. The analog

input range is programmed to be ±2.± V on the selected channel

and ±1ꢀ V on all other channels.

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition but

not the linearity of the converter. Power supply rejection is the

maximum change in the full-scale transition point due to a

change in power supply voltage from the nominal value (see the

Typical Performance Characteristics section).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa ± nfb, where

m, n = ꢀ, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n are equal to ꢀ. For example,

the second-order terms include (fa + fb) and (fa − fb), whereas

the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),

and (fa − 2fb).

CMRR (Common-Mode Rejection Ratio)

CMRR is defined as the ratio of the power in the ADC output at

full-scale frequency, f, to the power of a 1ꢀꢀ mV sine wave

applied to the common-mode voltage of the V_IN+ and V_IN−

frequency, f_S, as

CMRR (dB) = 1ꢀ log (Pf/Pf_S)

The AD7329 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, whereas the third-order

where Pf is the power at frequency f in the ADC output, and Pf_S

is the power at frequency f_Sin the ADC output (see Figure 17).

Rev. 0 | Page 16 of 40

AD7329

THEORY OF OPERATION

external reference operation is the default option. If the internal

reference is the preferred option, the user must write to the

reference bit in the control register to select the internal

reference operation.

CIRCUIT INFORMATION

The AD7329 is a fast, 8-channel, 12-bit plus sign, bipolar input,

serial A/D converter. The AD7329 can accept bipolar input ranges

that include ±1ꢀ V, ±± V, and ±2.± V; it can also accept a ꢀ V to

+1ꢀ V unipolar input range. A different analog input range can

be programmed on each analog input channel via the on-chip

registers. The AD7329 has a high speed serial interface that can

operate at throughput rates up to 1 MSPS.

The AD7329 also features power-down options to allow power

savings between conversions. The power-down modes are

selected by programming the on-chip control register as

described in the Modes of Operation section.

The AD7329 requires V_DDand V_SSdual supplies for the high

voltage analog input structures. These supplies must be equal to

or greater than the analog input range. See Table 6 for the

requirements of these supplies for each analog input range. The

AD7329 requires a low voltage 2.7 V to ±.2± V V_CCsupply to

power the ADC core.

CONVERTER OPERATION

The AD7329 is a successive approximation analog-to-digital

converter built around two capacitive DACs. Figure 24 and

Figure 2± show simplified schematics of the ADC in single-

ended mode during the acquisition and conversion phases,

respectively. Figure 26 and Figure 27 show simplified schematics

of the ADC in differential mode during acquisition and

conversion phases, respectively. In both examples, the

MUX_OUT+ pin is connected to the ADC_IN+ pin, and the

MUX_OUT− pin is connected to the ADC_IN− pin. The ADC is

composed of control logic, a SAR, and capacitive DACs. In

Figure 24 (the acquisition phase), SW2 is closed and SW1 is in

Position A, the comparator is held in a balanced condition, and

the sampling capacitor array acquires the signal on the input.

Table 6. Reference and Supply Requirements for Each

Analog Input Range

Selected

Analog

Input

Full-Scale

Input

Reference

Minimum

V_DD/V_SS(V)

Range (V) Voltage (V) Range (V) AV_CC(V)

10

5

2.5

3.0

2.5

3.0

2.5

3.0

2.5

3.0

10

12

3/5

10

12

5

6

5

6

CAPACITIVE

DAC

2.5

3

5

COMPARATOR

C

S

B

A

V

0

IN

0 to +10

0 to +12

+10/AGND

+12/AGND

CONTROL

LOGIC

SW1

SW2

AGND

Figure 24. ADC Acquisition Phase (Single Ended)

In order to meet the specified performance specifications when

the AD7329 is configured with the minimum V_DDand V_SS

supplies for a chosen analog input range, the throughput rate

should be decreased from the maximum throughput range (see

the Typical Performance Characteristics section).

When the ADC starts a conversion (Figure 2±), SW2 opens and

SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge redistribution

DAC are used to add and subtract fixed amounts of charge from

the capacitive DAC to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code

The analog inputs can be configured as either eight single-ended

inputs, four true differential input pairs, four pseudo differential

inputs, or seven pseudo differential inputs. Selection can be made

by programming the mode bits, Mode ꢀ and Mode 1, in the

control register.

CAPACITIVE

DAC

The serial clock input accesses data from the part and provides

the clock source for the successive approximation ADC. The

AD7329 has an on-chip 2.± V reference. However, the AD7329

can also work with an external reference. On power-up, the

COMPARATOR

C

S

B

A

V

0

IN

CONTROL

LOGIC

SW1

SW2

AGND

Figure 25. ADC Conversion Phase (Single Ended)

Rev. 0 | Page 17 of 40

AD7329

Figure 26 shows the differential configuration during the

acquisition phase. For the conversion phase, SW3 opens and

SW1 and SW2 move to Position B (see Figure 27). The output

impedances of the source driving the V_IN+ and V_IN− pins must

match; otherwise, the two inputs have different settling times,

resulting in errors.

The ideal transfer characteristic for the AD7329 when twos

complement coding is selected is shown in Figure 28. The ideal

transfer characteristic for the AD7329 when straight binary

coding is selected is shown in Figure 29.

011 ... 111

011 ... 110

CAPACITIVE

DAC

000 ... 001

000 ... 000

111 ... 111

COMPARATOR

C

S

B

V

+

IN

A

SW1

SW2

CONTROL

LOGIC

SW3

–

IN

B

C

100 ... 010

100 ... 001

100 ... 000

AGND – 1LSB

S

V

REF

CAPACITIVE

DAC

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB UNIPOLAR RANGE

Figure 26. ADC Differential Configuration During Acquisition Phase

ANALOG INPUT

Figure 28. Twos Complement Transfer Characteristic (Bipolar Ranges)

CAPACITIVE

DAC

111 ... 111

111 ... 110

COMPARATOR

C

S

B

V

+

IN

A

111 ... 000

011 ... 111

SW1

SW2

CONTROL

LOGIC

SW3

–

IN

B

C

S

V

REF

CAPACITIVE

DAC

000 ... 010

000 ... 001

000 ... 000

Figure 27. ADC Differential Configuration During Conversion Phase

–FSR/2 + 1LSB

AGND + 1LSB

+FSR/2 – 1LSB BIPOLAR RANGES

+FSR – 1LSB UNIPOLAR RANGE

OUTPUT CODING

ANALOG INPUT

Figure 29. Straight Binary Transfer Characteristic (Bipolar Ranges)

The AD7329 default output coding is set to twos complement.

The output coding is controlled by the coding bit in the control

register. To change the output coding to straight binary coding,

the coding bit in the control register must be set. When

operating in sequence mode, the output coding for each

channel in the sequence is the value written to the coding bit

during the last write to the control register.

ANALOG INPUT STRUCTURE

The analog inputs of the AD7329 can be configured as single-

ended, true differential, or pseudo differential via the control

register mode bits, as shown in Table 4 of the Registers section.

The AD7329 can accept true bipolar input signals. On power-

up, the analog inputs operate as eight single-ended analog input

channels. If true differential or pseudo differential is required, a

write to the control register is necessary after power-up to

change this configuration.

TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB

values (that is, 1 LSB, 2 LSB, and so on). The LSB size is

dependent on the analog input range selected.

Figure 3ꢀ shows the equivalent analog input circuit of the

AD7329 in single-ended mode. Figure 31 shows the equivalent

analog input structure in differential mode. The two diodes

provide ESD protection for the analog inputs.

Table 7. LSB Sizes for Each Analog Input Range

Input Range

Full-Scale Range/8192 Codes

LSB Size

2.441 mV

1.22 mV

0.61 mV

1.22 mV

10 V

5 V

2.5 V

0 V to +10 V

20 V

10 V

5 V

V

DD

MUX

+

ADC +

IN

OUT

D

10 V

C2

R1

V

0

IN

C1

C3

C4

D

V

SS

Figure 30. Equivalent Analog Input Circuit (Single Ended)

Rev. 0 | Page 18 of 40

AD7329

V

DD

For the AD7329, the value of R includes the on resistance of the

input multiplexer. The value of R is typically 3ꢀꢀ Ω. R_SOURCE

should include any extra source impedance on the analog input.

MUX

+

ADC

+

IN

OUT

D

C2

R1

V

+

IN

C1

C3

C4

D

The AD7329 enters track mode on the 14^thSCLK rising edge.

When the AD7329 is run at a throughput rate of 1 MSPS with a

2ꢀ MHz SCLK signal, the ADC has approximately 1.± SCLK

periods plus t₈plus the quiet time, t_QUIET, to acquire the analog

V

SS

DD

MUX

–

ADC

–

IN

OUT

D

C2

R1

CS

input signal. The ADC goes back into hold mode on the

falling edge.

V

–

IN

C1

C3

C4

D

V

SS

The current required to drive the ADC is extremely small when

using the external op amp between the MUX_OUTand ADC_IN

pins. This is due to the high input impedance of the op amp

placed between the MUX_OUTand ADC_INpins. This can be seen

in Figure 32, where the current required to drive the AD7329

input is <ꢀ.2 μA when AD8ꢀ21 is placed between the MUX_OUT

and ADC_INpins.

Figure 31. Equivalent Analog Input Circuit (Differential)

Care should be taken to ensure that the analog input does not

exceed the V_DDand V_SSsupply rails by more than 3ꢀꢀ mV.

Exceeding this value causes the diodes to become forward

biased and to start conducting into either the V_DDsupply rail or

the V_SSsupply rail. These diodes can conduct up to 1ꢀ mA

without causing irreversible damage to the part.

0.20

0.19

0.18

0.17

In Figure 3ꢀ and Figure 31, Capacitor C1 is typically 4 pF and

can primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance of the input

multiplexer and the track-and-hold switch. Capacitor C2 is the

sampling capacitor; its capacitance varies depending on the

analog input range selected (see the Specifications section).

V

= 12V, V = –12V

SS

DD

CC

0.16

0.15

0.14

= V

= 5V

DRIVE

SINGLE-ENDED MODE

50kHz ON SELECTED CHANNEL

f_IN= 50kHz

TRACK-AND-HOLD SECTION

The track-and-hold on the analog input of the AD7329 allows

the ADC to accurately convert an input sine wave of full-scale

amplitude to 13-bit accuracy. The input bandwidth of the track-

and-hold is greater than the Nyquist rate of the ADC. The

AD7329 can handle frequencies up to 2ꢀ MHz.

T

= 25°C

A

AD8021 BETWEEN MUX

AND ADC PINS

OUT

IN

0

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT RATE (kSPS)

Figure 32. Input Current vs. Throughput Rate

with AD8021 Between MUX_OUTand ADC_IN

The ADC_INpins connect directly to the input stage of the track-

and-hold circuit. This is a high impedance input. Connecting

the MUX_OUTpins directly to the ADC_INpins connects the

multiplexer output to the track-and-hold circuit. The input

voltage range on the ADC_INpins is determined by the range

register bits for the input channel selected. The user must

ensure that the input voltage to the ADC_INpins is within the

selected voltage range.

35

30

25

20

15

10

5

V

= 12V, V = –12V

SS

DD

CC

The track-and-hold enters its tracking mode on the 14^thSCLK

= V

= 5V

DRIVE

SINGLE-ENDED MODE

50kHz ON SELECTED CHANNEL

f_IN= 50kHz

CS

rising edge after the

falling edge. The time required to

acquire an input signal depends on how quickly the sampling

capacitor is charged. With zero source impedance, 3ꢀꢀ ns is

sufficient to acquire the signal to the 13-bit level.

T

= 25°C

A

WIRE LINK BETWEEN MUX

OUT

AND ADC PINS

IN

0

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT RATE (kSPS)

The acquisition time required is calculated using the following

formula:

Figure 33. Input Current vs. Throughput Rate

with a Wire Link Between MUX_OUTand ADC_IN

t_ACQ= 1ꢀ × ((R_SOURCE+ R)C)

where C is the sampling capacitance, and R is the resistance

seen by the track-and-hold amplifier looking at the input.

Rev. 0 | Page 19 of 40

AD7329

ANALOG INPUT

Single-Ended Inputs

TYPICAL CONNECTION DIAGRAM

Figure 34 shows a typical connection diagram for the AD7329.

In this configuration, the AGND pin is connected to the analog

ground plane of the system, and the DGND pin is connected to

the digital ground plane of the system. The analog inputs on the

AD7329 can be configured to operate in single-ended, true

differential, or pseudo differential mode. The AD7329 can operate

with either an internal or external reference. In Figure 34, the

AD7329 is configured to operate with the internal 2.± V reference.

A 68ꢀ nF decoupling capacitor is required when operating with

the internal reference.

The AD7329 has a total of eight analog inputs when operating

in single-ended mode. Each analog input can be independently

programmed to one of the four analog input ranges. In applications

where the signal source is high impedance, it is recommended

to buffer the signal before applying it to the ADC analog inputs.

Figure 36 shows the configuration of the AD7329 in single-

ended mode.

V+

5V

AGND

The V_CCpin can be connected to either a 3 V or a ± V supply

voltage. The V_DDand V_SSare the dual supplies for the high

voltage analog input structures. The voltage on these pins must

be equal to or greater than the highest analog input range

selected on the analog input channels (see Table 6 for more

information). The V_DRIVEpin is connected to the supply voltage

of the microprocessor. The voltage applied to the V_DRIVEinput

controls the voltage of the serial interface.

V

+

IN

V

CC

DD

AD7329¹

V

SS

V–

ADDITIONAL PINS OMITTED FOR CLARITY.

1

FILTERING/BUFFERING

Figure 36. Single-Ended Mode Typical Connection Diagram

+15V

V

+2.7V TO +5.25V

CC

True Differential Mode

+

10µF

+

0.1µF

10µF

0.1µF

The AD7329 can have four true differential analog input pairs.

Differential signals have some benefits over single-ended

signals, including better noise immunity based on the device’s

common-mode rejection and improvements in distortion

performance. Figure 37 defines the configuration of the true

differential analog inputs of the AD7329.

1

+

ADC

IN

V

MUX

V

CC

DD

OUT

+3V SUPPLY

V

DRIVE

+

10µF

0.1µF

V

0

1

2

3

4

5

6

7

IN

AD7329

CS

DOUT

SCLK

DIN

µC/µP

ANALOG INPUTS

±10V, ±5V, ±2.5V

0V TO +10V

V

+

IN

DGND

SERIAL

INTERFACE

REF /REF

IN

AD7329¹

OUT

680nF

0.1µF

–

ADC

IN AGND

1

MUX

V

OUT

SS

V

–

IN

–15V

10µF

1

+

MINIMUM V AND V SUPPLY VOLTAGES

DD SS

DEPEND ON THE HIGHEST ANALOG INPUT

1

ADDITIONAL PINS OMITTED FOR CLARITY.

RANGE SELECTED.

Figure 37. True Differential Inputs

Figure 34. Typical Connection Diagram (Single-Ended Mode)

The amplitude of the differential signal is the difference

between the signals applied to the V_IN+ and V_IN− pins in

each differential pair (V_IN+ − V_IN−). V_IN+ and V_IN− should

be simultaneously driven by two signals of equal amplitude,

dependent on the input range selected, that are 18ꢀ° out of

phase. Assuming the ±4 × V_REFmode, the amplitude of the

differential signal is −2ꢀ V to +2ꢀ V p-p (2 × 4 × V_REF),

regardless of the common mode.

FILTERING/BUFFERING

+15V

V

+2.7V TO +5.25V

CC

+

0.1µF

10µF

0.1µF

1

V

CC

DD

+3V SUPPLY

V

DRIVE

+

10µF

0.1µF

V

0

IN

CS

1

AD7329

2

3

4

5

6

7

DOUT

SCLK

DIN

µC/µP

ANALOG INPUTS

±10V, ±5V, ±2.5V

0V TO +10V

The common mode is the average of the two signals

(V_IN+ + V_IN−)/2

DGND

AGND

SERIAL

INTERFACE

REF /REF

IN

OUT

680nF

0.1µF

1

V

SS

and is therefore the voltage on which the two input signals are

centered.

–15V

10µF

1

+

MINIMUM V AND V SUPPLY VOLTAGES

DD SS

DEPEND ON THE HIGHEST ANALOG INPUT

RANGE SELECTED.

Figure 35. Typical Connection Diagram (Differential Mode)

Rev. 0 | Page 20 of 40

AD7329

6

4

This voltage is set up externally, and its range varies with

reference voltage. As the reference voltage increases, the

common-mode range decreases. When driving the differential

inputs with an amplifier, the actual common-mode range is

determined by the amplifier’s output swing. If the differential

inputs are not driven from an amplifier, the common-mode

range is determined by the supply voltage on the V_DDsupply pin

and the V_SSsupply pin.

±5V RANGE

2

0

–2

–4

–6

–8

±2.5V

±10V

RANGE RANGE

±10V

±2.5V

RANGE

When a conversion takes place, the common mode is rejected,

resulting in a noise-free signal of amplitude −2 × (4 × V_REF) to +2 ×

(4 × V_REF), corresponding to Digital Codes −4ꢀ96 to +4ꢀ9±.

V

= 3V

CC

= 2.5V

REF

±16.5V V /V

DD SS

±12V V /V

DD SS

5

±5V RANGE

4

Figure 40. Common-Mode Range for V_CC= 3 V and REF_IN/REF_OUT= 2.5 V

±5V RANGE

3

2

±2.5V

RANGE

8

±5V RANGE

±2.5V

RANGE

±10V

RANGE

6

4

1

0

±10V

–1

–2

–3

–4

–5

–6

RANGE

±2.5V

RANGE

2

±10V

RANGE

0

–2

–4

–6

–8

V

= 3V

CC

= 3V

REF

±5V RANGE

±16.5V V /V

DD SS

±12V V /V

DD SS

±2.5V

RANGE

V

= 5V

CC

Figure 38. Common-Mode Range for V_CC= 3 V and REF_IN/REF_OUT= 3 V

= 2.5V

REF

8

±16.5V V /V

±12V V /V

DD SS

Figure 41. Common-Mode Range for V_CC= 5 V and REF_IN/REF_OUT= 2.5 V

±5V RANGE

6

4

±2.5V

RANGE

±2.5V

RANGE

±10V

RANGE

2

±10V

RANGE

0

–2

–4

V

= 5V

CC

= 3V

REF

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 39. Common-Mode Range for V_CC= 5 V and REF_IN/REF_OUT= 3 V

Rev. 0 | Page 21 of 40

AD7329

8

6

Pseudo Differential Inputs

±5V RANGE

±2.5V

RANGE

±5V RANGE

The AD7329 can have four pseudo differential pairs or seven

pseudo differential inputs referenced to a common V_IN− pin.

The V_IN+ inputs are coupled to the signal source and must have

an amplitude within the selected range for that channel, as

programmed in the range register. A dc input is applied to the

V_IN− pin. The voltage applied to this input provides an offset for

the V_IN+ input from ground or pseudo ground. Pseudo differential

inputs separate the analog input signal ground from the ADC

ground, allowing cancellation of dc common-mode voltages.

Figure 42 shows the configuration of the AD7329 in pseudo

differential mode.

±2.5V

RANGE

±10V

RANGE

4

2

0

–2

–4

–6

–8

±10V

RANGE

0V TO +10V

RANGE

0V TO +10V

RANGE

V

= 5V

CC

= 2.5V

REF

±16.5V V /V

DD SS

±12V V /V

DD SS

When a conversion takes place, the pseudo ground corresponds

to Code −4ꢀ96 and the maximum amplitude corresponds to

Code +4ꢀ9±.

Figure 43. Pseudo Input Range with V_CC= 5 V

4

2

±5V RANGE

V+

5V

±5V RANGE

±2.5V

RANGE

0

V

+

IN

V

CC

DD

AD7329¹

–2

–4

–6

–8

±10V

V

–

SS

RANGE

IN

±2.5V

RANGE

±10V

RANGE

0V TO +10V

RANGE

0V TO +10V

RANGE

V–

V

= 3V

CC

1

= 2.5V

ADDITIONAL PINS OMITTED FOR CLARITY.

REF

Figure 42. Pseudo Differential Inputs

±16.5V V /V

DD SS

±12V V /V

DD SS

Figure 44. Pseudo Input Range with V_CC= 3 V

Figure 43 and Figure 44 show the typical voltage range on the

V_IN− pin for various analog input ranges when configured in

the pseudo differential mode.

For example, when the AD7329 is configured to operate in

pseudo differential mode and the ±± V range is selected with

16.± V V_DD, −16.± V V_SS, and ± V V_CC, the voltage on the V_IN−

pin can vary from −6.± V to +6.± V.

Rev. 0 | Page 22 of 40

AD7329

Table 8. Typical AC Performance

Using Different Op Amps in Single-Ended Mode

DRIVER AMPLIFIER CHOICE

In applications where the harmonic distortion and signal-to-

noise ratio are critical specifications, the analog input of the

AD7329 should be driven from a low impedance source. Large

source impedances significantly affect the ac performance of the

ADC and can necessitate the use of an input buffer amplifier.

No

Buffer AD845 AD8021 AD8610

74.24

72.42

74.03

74.88

73.78

72.11

−77.04

73.88

71.98

−76.47

10 V SNR (dB)

SNRD (dB)

−77.05 −75.95

THD (dB)

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of THD that can be

tolerated in the application. The THD increases as the source

impedance increases and performance degrades. Figure 21 and

Figure 22 show graphs of the THD vs. the analog input

frequency for various source impedances. Depending on the

input range and analog input configuration selected, the

AD7329 can handle source impedances of up to 4 kΩ before the

THD starts to degrade.

Table 9. Typical AC Performance

Using Different Op Amps in Differential Mode

No

Buffer AD845 AD8021 AD8610

77.16

76.50

76.81

76.02

76.95

76.78

76.76

75.89

−83.24

10 V SNR (dB)

SNRD (dB)

−84.91 −83.74 −90.55

THD (dB)

Differential operation requires that V_IN+ and V_IN− be

simultaneously driven with two signals of equal amplitude that

are 18ꢀ° out of phase. The common mode must be set up

externally to the AD7329. The common-mode range is

determined by the REF_IN/REF_OUTvoltage, the V_CCsupply voltage,

and the particular amplifier used to drive the analog inputs.

Differential mode with either an ac input or a dc input provides

the best THD performance over a wide frequency range. Because

not all applications have a signal preconditioned for differential

operation, there is often a need to perform a single-ended-to-

differential conversion.

Due to the programmable nature of the analog inputs on the

AD7329, the choice of op amp used to drive the inputs is a

function of the particular application and depends on the input

configuration and the analog input voltage ranges selected.

The driver amplifier must be able to settle for a full-scale step to

a 13-bit level, ꢀ.ꢀ122%, in less than the specified acquisition

time of the AD7329. An op amp such as the AD8ꢀ21 meets this

requirement when operating in single-ended mode. The AD8ꢀ21

needs an external compensating NPO type of capacitor. The

AD8ꢀ22 can also be used in high frequency applications where

a dual version is required. For lower frequency applications, op

amps such as the AD797, AD84±, and AD861ꢀ can be used with

the AD7329 in single-ended mode configuration.

This single-ended-to-differential conversion can be performed

using an op amp pair. Typical connection diagrams for an op

amp pair are shown in Figure 4± and Figure 46. In Figure 4±,

the common-mode signal is applied to the noninverting input

of the second amplifier.

Rev. 0 | Page 23 of 40

AD7329

1.5kΩ

V

DD

2kΩ

V

IN

100nF

V+

7

3

2

MUX

+

OUT

1.5kΩ

AD8021

6

ADC

+

IN

5

4

10pF

100nF

V–

V

SS

10kΩ

Figure 47. AD8021 Configuration Used Between MUX_OUTand ADC_INPins

Figure 45. Single-Ended-to-Differential Configuration with the AD845

for Bipolar Operation

442Ω

AD8021

V

IN

V+

442Ω

V–

AD8021

100Ω

Figure 46. Single-Ended-to-Differential Configuration with the AD8021

Rev. 0 | Page 24 of 40

AD7329

REGISTERS

The AD7329 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2.

These registers are write-only registers.

ADDRESSING REGISTERS

A serial transfer on the AD7329 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to

determine which register is addressed. The three MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register

select bits are used to determine which of the four on-board registers is selected. The write bit determines if the data on the DIN line

following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the

register select bits. If the write bit is ꢀ, the data on the DIN line does not load into any register.

Table 10. Decoding Register Select Bits and Write Bit

Write Register Select 1

Register Select 2

Description

0

1

0

Data on the DIN line during this serial transfer is ignored.

This combination selects the control register. The subsequent 12 bits are loaded into

the control register.

1

0

1

0

1

This combination selects Range Register 1. The subsequent 8 bits are loaded into

Range Register 1.

This combination selects Range Register 2. The subsequent 8 bits are loaded into

Range Register 2.

This combination selects the sequence register. The subsequent 8 bits are loaded into

the sequence register.

Rev. 0 | Page 25 of 40

AD7329

CONTROL REGISTER

The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The

control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7329 configuration for the next

conversion. If the sequence register is being used, data should be loaded into the control register after the range registers and the sequence

register have been initialized. The bit functions of the control register are shown in Table 11 (the power-up status of all bits is ꢀ).

MSB

15

LSB

0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Write Register Register ADD2 ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 Weak/

0

Select 1 Select 2

Three-State

Table 11. Control Register Details

Bit

Mnemonic

Description

12, 11, 10 ADD2, ADD1,

ADD0

These three channel address bits are used to select the analog input channel for the next conversion if the

sequencer is not being used. If the sequencer is being used, the three channel address bits are used to

select the final channel in a consecutive sequence.

9, 8

Mode 1, Mode 0

These two mode bits are used to select the configuration of the eight analog input pins, V_IN0 to V_IN7. These

pins are used in conjunction with the channel address bits. On the AD7329, the analog inputs can be

configured as eight single-ended inputs, four fully differential input pairs, four pseudo differential inputs,

or seven pseudo differential inputs (see Table 12).

7, 6

5

PM1, PM0

Coding

The power management bits are used to select different power mode options on the AD7329 (see Table 13).

This bit is used to select the type of output coding the AD7329 uses for the next conversion result. If the

coding = 0, the output coding is twos complement. If the coding = 1, the output coding is straight binary.

When operating in sequence mode, the output coding for each channel is the value written to the coding

bit during the last write to the control register.

4

Ref

The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is

enabled and used for the next conversion and the internal reference is disabled. If Ref = 1, the internal ref-

erence is used for the next conversion. When operating in sequence mode, the reference used for each

channel is the value written to the Ref bit during the last write to the control register.

3, 2

1

Seq1/Seq2

The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 14).

Weak/Three-State This bit selects the state of the DOUT line at the end of the current serial transfer. If the bit is set to 1, the

DOUT line is weakly driven to Channel Address Bit ADD2 of the following conversion. If this bit is set to 0,

DOUT returns to three-state at the end of the serial transfer (see the Serial Interface section).

The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true

differential input pairs, or eight single-ended analog inputs.

Table 12. Analog Input Configuration Selection

Mode 1 = 1, Mode 0 = 1

Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 =1

Mode 1 = 0, Mode 0 = 0

Channel Address Bits

ADD2 ADD1 ADD0 V_IN+

7 Pseudo Differential I/Ps 4 Fully Differential I/Ps 4 Pseudo Differential I/Ps 8 Single-Ended I/Ps

V_IN−

V_IN7

V_IN+

V_IN0

V_IN2

V_IN4

V_IN6

V_IN−

V_IN1

V_IN3

V_IN5

V_IN7

V_IN+

V_IN0

V_IN2

V_IN4

V_IN6

V_IN−

V_IN1

V_IN3

V_IN5

V_IN7

V_IN+

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

V_IN−

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

AGND

Temperature indicator

Rev. 0 | Page 26 of 40

AD7329

Table 13. Power Mode Selection

PM1 PM0 Description

1

0

1

0

1

0

Full Shutdown Mode. In this mode, all internal circuitry on the AD7329 is powered down. Information in the control register

is retained when the AD7329 is in full shutdown mode.

Autoshutdown Mode. The AD7329 enters autoshutdown on the 15^thSCLK rising edge when the control register is updated.

All internal circuitry is powered down in autoshutdown.

Autostandby Mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7329 enters

autostandby mode on the 15^thSCLK rising edge after the control register is updated.

Normal Mode. All internal circuitry is powered up at all times.

Table 14. Sequencer Selection

Seq1 Seq2 Description

0

The channel sequencer is not used. The analog channel, selected by programming the ADD2 to ADD0 bits in the control

register, selects the next channel for conversion.

0

1

Uses the sequence of channels that were previously programmed in the sequence register for conversion. The AD7329

starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted,

the AD7329 keeps converting the sequence. The range for each channel defaults to the range previously written into the

corresponding range register.

1

0

1

This configuration is used in conjunction with the channel address bits in the control register. This allows continuous

conversions on a consecutive sequence of channels, from Channel 0 through a final channel selected by the channel

address bits in the control register. The range for each channel defaults to the range previously written into the

corresponding range register.

The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control

register, selects the next channel for conversion.

Rev. 0 | Page 27 of 40

AD7329

SEQUENCE REGISTER

The sequence register on the AD7329 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in

the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.

MSB

16

LSB

1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Write

Register Select 1

Register Select 2

V_IN0

V_IN1

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

0

RANGE REGISTERS

The range registers are used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for

Channel ꢀ to Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from

Channel ꢀ to Channel 3. There are four analog input ranges, ±1ꢀ V, ±± V, ±2.± V, and ꢀ V to +1ꢀ V. A write to Range Register 1 is selected

by setting the write bit to 1 and the range select bits to ꢀ and 1. After the initial write to Range Register 1 occurs, each time an analog

input is selected, the AD7329 automatically configures the analog input to the appropriate range, as indicated by Range Register 1.

The ±1ꢀ V input range is selected by default on each analog input channel (see Table 1±).

MSB

16

LSB

1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Write Register Select 1

Register Select 2

V_IN0A V_IN0B V_IN1A V_IN1B V_IN2A V_IN2B V_IN3A V_IN3B

0

Range Register 2 is used to set the ranges for Channel 4 to Channel 7. It is an 8-bit, write-only register with two dedicated range bits for

each of the analog input channels from Channel 4 to Channel 7. There are four analog input ranges, ±1ꢀ V, ±± V, ±2.± V, and ꢀ V to +1ꢀ V.

After the initial write to Range Register 2 occurs, each time an analog input is selected, the AD7329 automatically configures the analog

input to the appropriate range, as indicated by Range Register 2. The ±1ꢀ V input range is selected by default on each analog input

channel (see Table 1±).

MSB

16

LSB

1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Write Register Select 1

Register Select 2

V_IN4A V_IN4B V_IN5A V_IN5B V_IN6A V_IN6B V_IN7A V_IN7B

0

Table 15. Range Selection

V_INxA

V_INxB

Description

0

1

0

1

0

1

This combination selects the 10 V input range on V_INx.

This combination selects the 5 V input range on V_INx.

This combination selects the 2.5 V input range on V_INx.

This combination selects the 0 V to +10 V input range on V_INx.

Rev. 0 | Page 28 of 40

AD7329

SEQUENCER OPERATION

POWER ON.

CS

DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE

FOR EACH ANALOG INPUT CHANNEL.

DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V

RANGE, SINGLE-ENDED MODE.

CS

DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE

FOR EACH ANALOG INPUT CHANNEL.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

RANGE REGISTER 1.

CS

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

ANALOG INPUT CHANNELS TO BE INCLUDED IN

THE SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

RANGE REGISTER 1.

CS

DIN: WRITE TO CONTROL REGISTER TO START THE

SEQUENCE, Seq1 = 0, Seq2 = 1.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

SINGLE-ENDED MODE, RANGE SELECTED IN

RANGE REGISTER 1.

CS

DIN: TIE DIN LOW/WRITE BIT = 0TO CONTINUE TO CONVERT

THROUGH THE SEQUENCE OF CHANNELS.

CS

DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN

THE SEQUENCE.

DIN TIED LOW/WRITE BIT = 0.

DIN: WRITE TO CONTROL

REGISTER TO STOP THE

SEQUENCE, Seq1 = 0, Seq2 = 0.

CONTINUOUSLY CONVERT

STOP

ON THE SELECTED SEQUENCE

A SEQUENCE.

OF CHANNELS.

DOUT: CONVERSION RESULT

FROM CHANNEL IN SEQUENCE.

SELECT A NEW SEQUENCE.

CS

DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE

NEW SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL X IN

THE FIRST SEQUENCE.

Figure 48. Programmable Sequence Flowchart

The AD7329 can be configured to automatically cycle through

a number of selected channels using the on-chip sequence

register with the Seq1 bit and the Seq2 bit in the control register.

Figure 48 shows how to program the AD7329 register to

operate in sequence mode.

These two initial serial transfers are only necessary if input

ranges other than the default ranges are required. After the

analog input ranges are configured, a write to the sequence

register is necessary to select the channels to be included in the

sequence. Once the channels for the sequence have been

selected, the sequence can be initiated by writing to the control

register and setting Seq1 to ꢀ and Seq2 to 1. The AD7329

continues to convert the selected sequence without interruption

provided that the sequence register remains unchanged and

Seq1 = ꢀ and Seq2 = 1 in the control register.

After power-up, the four on-chip registers contain default

values. Each analog input has a default input range of ±1ꢀ V. If

different analog input ranges are required, a write to the range

registers is necessary. This is shown in the first two serial

transfers of Figure 48.

Rev. 0 | Page 29 of 40

AD7329

If a change to one of the range registers is required during a

sequence, it is necessary to first stop the sequence by writing to

the control register and setting Seq1 to ꢀ and Seq2 to ꢀ. Next,

the write to the range register should be completed to change

the required range. The previously selected sequence should

then be initiated again by writing to the control register and

setting Seq1 to ꢀ and Seq2 to 1. The ADC converts the first

channel in the sequence.

Once the control register is configured to operate the AD7329

in this mode, the DIN line can be held low or the write bit can

be set to ꢀ. To return to traditional multichannel operation, a

write to the control register to set Seq1 to ꢀ and Seq2 to ꢀ is

necessary.

When Seq1 and Seq2 are both set to ꢀ or to 1, the AD7329 is

configured to operate in traditional multichannel mode, where

a write to Channel Address Bit ADD2 to Bit ADDꢀ in the control

register selects the next channel for conversion.

The AD7329 can be configured to convert a sequence of

consecutive channels (see Figure 49). This sequence begins by

converting on Channel ꢀ and ends with a final channel as

selected by Bit ADD2 to Bit ADDꢀ in the control register. In

this configuration, there is no need for a write to the sequence

register. To operate the AD7329 in this mode, set Seq1 to 1 and

Seq2 to ꢀ in the control register, and then select the final channel

in the sequence by programming Bit ADD2 to Bit ADDꢀ in the

control register.

POWER ON.

CS

DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE

FOR ANALOG INPUT CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V

RANGE, SINGLE-ENDED MODE.

CS

DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE

FOR ANALOG INPUT CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER 1,

SINGLE-ENDED MODE.

CS

DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL

CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1

AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER 1,

SINGLE-ENDED MODE.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE

TO CONVERT THROUGH THE SEQUENCE OF

CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 0,

RANGE SELECTED IN RANGE REGISTER 1.

CS

DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE

THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.

DOUT: CONVERSION RESULT FROM CHANNEL 1,

RANGE SELECTED IN RANGE REGISTER 1.

DIN TIED LOW/WRITE BIT = 0.

CONTINUOUSLY CONVERT

ON CONSECUTIVE SEQUENCE

OF CHANNELS.

STOP

A SEQUENCE.

CS

DIN: WRITE TO CONTROL

REGISTER TO STOP THE

SEQUENCE, Seq1 = 0, Seq2 = 0.

DOUT: CONVERSION RESULT

FROM CHANNEL IN SEQUENCE.

Figure 49. Flowchart for Consecutive Sequence of Channels

Rev. 0 | Page 30 of 40

AD7329

REFERENCE

TEMPERATURE INDICATOR

The AD7329 can operate with either the internal 2.± V on-chip

reference or an externally applied reference. The internal

reference is selected by setting the Ref bit in the control register

to 1. On power-up, the Ref bit is ꢀ, which selects the external

reference for the AD7329 conversion. Suitable reference sources

for the AD7329 include AD78ꢀ, AD1±82, ADR431, REF193,

and ADR391.

The AD7329 has an on-chip temperature indicator. The

temperature indicator can be used to provide local temperature

measurements on the AD7329. To access the temperature

indicator, the ADC should be configured in pseudo differential

mode, Mode 1 = Mode ꢀ = 1, which sets Channel Bits ADD2,

ADD1, and ADDꢀ to 1. V_IN7 must be tied to AGND or to a

small dc voltage within the specified pseudo input range for the

selected analog input range. When a conversion is initiated in

this configuration, the output code represents the temperature

(see Figure ±ꢀ). When using the temperature indicator on the

AD7329, the part should be operated at low throughput rates, such

as approximately 3ꢀ kSPS for the ±2.± V range. The throughput

rate is reduced for the temperature indicator mode because the

AD7329 requires more acquisition time for this mode.

The internal reference circuitry consists of a 2.± V band gap

reference and a reference buffer. When operating the AD7329

in internal reference mode, the 2.± V internal reference is

available at the REF_IN/REF_OUTpin, which should be decoupled

to AGND using a 68ꢀ nF capacitor. It is recommended that the

internal reference be buffered before applying it elsewhere in

the system. The internal reference is capable of sourcing up to

9ꢀ μA.

5450

V

= V = 5V

DRIVE

CC

DD

= 12V, V = –12V

SS

5400

5350

5300

5250

5200

5150

5100

5050

±2.5V RANGE

INTERNAL REFERENCE

30kSPS

On power-up, if the internal reference operation is required for

the ADC conversion, a write to the control register is necessary

to set the Ref bit to 1. During the control register write, the

conversion result from the first initial conversion is invalid. The

reference buffer requires ±ꢀꢀ ꢂs to power up and charge the

68ꢀ nF decoupling capacitor during the power-up time.

The AD7329 is specified for a 2.± V to 3 V reference range.

When a 3 V reference is selected, the ranges are ±12 V, ±6 V,

±3 V, and ꢀ V to +12 V. For these ranges, the V_DDand V_SSsupply

must be equal to or greater than the maximum analog input

range selected.

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 50. Temperature vs. ADC Output Code for 2.5 V Range

V_DRIVE

4420

The AD7329 has a V_DRIVEfeature to control the voltage at which

the serial interface operates. V_DRIVEallows the ADC to easily

interface to both 3 V and ± V processors. For example, if the

AD7329 is operated with a V_CCof ± V, the V_DRIVEpin can be

powered from a 3 V supply. This allows the AD7329 to accept

large bipolar input signals with low voltage digital processing.

V

= V

= 5V

CC

DRIVE

/V = ±12V

DD SS

4410

4400

4390

4380

4370

4360

4350

4340

50kSPS

±10V RANGE, INT REF

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 51. Temperature vs. ADC Output Code for 10 V Range

Rev. 0 | Page 31 of 40

AD7329

MODES OF OPERATION

The AD7329 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements. The mode of

operation of the AD7329 is controlled by the power management

bits, Bit PM1 and Bit PMꢀ, in the control register as shown in

Table 13. The default mode is normal mode, where all internal

circuitry is fully powered up.

The AD7329 remains fully powered up at the end of the

conversion if both PM1 and PMꢀ contain ꢀ in the control

register.

To complete the conversion and access the conversion result,

16 serial clock cycles are required. At the end of the conversion,

CS

can idle either high or low until the next conversion.

Once the data transfer is complete, another conversion can be

initiated after the quiet time, t_QUIET, has elapsed.

NORMAL MODE

(PM1 = PM0 = 0)

FULL SHUTDOWN MODE

(PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate

performance with the AD7329 being fully powered up at all

times. Figure ±2 shows the general operation of the AD7329

in normal mode.

In this mode, all internal circuitry on the AD7329 is powered

down. The part retains information in the registers during full

shutdown. The AD7329 remains in full shutdown mode until

the power management bits, Bit PM1 and Bit PMꢀ, in the

control register are changed.

CS

The conversion is initiated on the falling edge of , and the

track-and-hold section enters hold mode, as described in the

Serial Interface section. The data on the DIN line during the

16 SCLK transfer is loaded into one of the on-chip registers if

the write bit is set. The register is selected by programming the

register select bits (see Table 1ꢀ).

A write to the control register with PM1 = PMꢀ = 1 places the

part into full shutdown mode. The AD7329 enters full

shutdown mode on the 1±^thSCLK rising edge once the control

register is updated.

CS

If a write to the control register occurs while the part is in full

shutdown mode with the power management bits, Bit PM1 and

Bit PMꢀ, set to ꢀ (normal mode), the part begins to power up

on the 1±^thSCLK rising edge once the control register is

updated. Figure ±3 shows how the AD7329 is configured to exit

full shutdown mode. To ensure the AD7329 is fully powered up,

1

16

SCLK

DOUT

DIN

3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT

DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2

REGISTER

CS

t_POWER-UPshould elapse before the next

falling edge.

Figure 52. Normal Mode

THE PART IS FULLY POWERED UP

ONCE t_POWER-UPHAS ELAPSED

THE PART BEGINS TO POWER UP ON THE

15TH SCLK RISING EDGE AS PM1 = PM0 = 0

PART IS IN FULL

SHUTDOWN

t_POWER-UP

CS

1

16

1

16

SCLK

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA INTO CONTROL/SHADOW REGISTER

SDATA

DIN

DATA INTO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.

PM1 = PM0 = 0

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0

IN CONTROL REGISTER

Figure 53. Exiting Full Shutdown Mode

Rev. 0 | Page 32 of 40

AD7329

As is the case with autoshutdown mode, the AD7329 enters

AUTOSHUTDOWN MODE

standby on the 1±^thSCLK rising edge once the control register is

updated (see Figure ±4). The part retains information in the

registers during standby. The AD7329 remains in standby until

(PM1 = 1, PM0 = 0)

Once the autoshutdown mode is selected, the AD7329

automatically enters shutdown on the 1±^thSCLK rising edge. In

autoshutdown mode, all internal circuitry is powered down.

The AD7329 retains information in the registers during

autoshutdown. The track-and-hold section is in hold mode

CS

it receives a

rising edge. The ADC begins to power up on the

CS

rising edge, the track-and-hold,

rising edge. On the

which was in hold mode while the part was in standby, returns

to track.

CS

during autoshutdown. On the rising

edge, the track-and-

The power-up time from standby is 7±ꢀ ns. The user should

hold section, which was in hold during shutdown, returns to

track as the AD7329 begins to power up. The time to power up

from autoshutdown is ±ꢀꢀ ꢂs.

CS

ensure that 7±ꢀ ns have elapsed before bringing

low to

attempt a valid conversion. Once this valid conversion is

complete, the AD7329 again returns to standby on the 1±^th

When the control register is programmed to transition to

autoshutdown mode, it does so on the 1±^thSCLK rising edge.

Figure ±4 shows the part entering autoshutdown mode. The

CS

SCLK rising edge. The

part in standby mode.

signal must remain low to keep the

Figure ±4 shows the part entering autoshutdown mode. The

sequence of events is the same when entering autostandby

mode. In Figure ±4, the power management bits are configured

for autoshutdown. For autostandby mode, the power

management bits, PM1 and PMꢀ, should be set to ꢀ and 1,

respectively.

CS

AD7329 automatically begins to power up on the

edge. The t_POWER-UPis required before a valid conversion, initiated

CS

rising

by bringing the

signal low, can take place. Once this valid

conversion is complete, the AD7329 powers down again on the

th

CS

1± SCLK rising edge. The

signal must remain low again to

keep the part in autoshutdown mode.

AUTOSTANDBY MODE

(PM1 = 0, PM0 =1)

In autostandby mode, portions of the AD7329 are powered

down, but the on-chip reference remains powered up. The

reference bit in the control register should be 1 to ensure that

the on-chip reference is enabled. This mode is similar to

autoshutdown but allows the AD7329 to power up much faster,

which allows faster throughput rates.

PART BEGINS TO POWER

UP ON CS RISING EDGE

THE PART IS FULLY POWERED UP

ONCE t_POWER-UPHAS ELAPSED

PART ENTERS SHUTDOWN MODE

t_POWER-UP

TH

ON THE 15 RISING SCLK EDGE

IF PM1 = 1, PM0 = 0

CS

1

15 16

1

15 16

SCLK

SDATA

DIN

VALID DATA

DATA INTO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS

PM1 = 1, PM0 = 0

Figure 54. Entering Autoshutdown/Autostandby Mode

Rev. 0 | Page 33 of 40

AD7329

POWER VS. THROUGHPUT RATE

20

18

16

14

12

10

8

The power consumption of the AD7329 varies with throughput

rate. The static power consumed by the AD7329 is very low, and

significant power savings can be achieved as the throughput

rate is reduced. Figure ±± and Figure ±6 shows the power vs.

throughput rate for the AD7329 at a V_CCof 3 V and ± V,

respectively. Both plots clearly show that the average power

consumed by the AD7329 is greatly reduced as the sample

frequency is reduced. This is true whether a fixed SCLK value is

used or if it is scaled with the sampling frequency. Figure ±± and

Figure ±6 show the power consumption when operating in

normal mode for a fixed 2ꢀ MHz SCLK and a variable SCLK

that scales with the sampling frequency.

VARIABLE SCLK

20MHz SCLK

6

4

V

= 5V

CC

DD

= 12V, V = –12V

SS

2

T

= 25°C

A

INTERNAL REFERENCE

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT RATE (kHz)

0

12

Figure 56. Power vs. Throughput Rate with 5 V V_CC

10

20MHz SCLK

8

VARIABLE SCLK

6

4

V

= 3V

CC

DD

2

0

= 12V, V = –12V

= 25°C

SS

T

A

INTERNAL REFERENCE

100 200 300 400 500 600 700 800 900 1000 1100

THROUGHPUT RATE (kSPS)

0

Figure 55. Power vs. Throughput Rate with 3 V V_CC

Rev. 0 | Page 34 of 40

AD7329

SERIAL INTERFACE

Figure ±7 shows the timing diagram for the serial interface of

the AD7329. The serial clock applied to the SCLK pin provides

the conversion clock and controls the transfer of information to

and from the AD7329 during a conversion.

Conversion data is clocked out of the AD7329 on each SCLK

falling edge. Data on the DOUT line consists of three channel

identifier bits, a sign bit, and a 12-bit conversion result. The

channel identifier bits are used to indicate which channel

corresponds to the conversion result.

CS

The

signal initiates the data transfer and the conversion

CS

Three-State

If the Weak/

bit is set in the control register, rather

process. The falling edge of

puts the track-and-hold section

than returning to true three-state upon the 16^thSCLK falling

edge, the DOUT line is pulled weakly to the logic level

corresponding to ADD3 of the next serial transfer. This is done

to ensure that the MSB of the next serial transfer is set up in

into hold mode and takes the bus out of three-state. The analog

input signal is then sampled. Once the conversion is initiated,

it requires 16 SCLK cycles to complete.

The track-and-hold section goes back into track mode on the

14^thSCLK rising edge. On the 16^thSCLK falling edge, the

DOUT line returns to three-state. If the rising edge of

before 16 SCLK cycles have elapsed, the conversion is

CS

time for the first SCLK falling edge after the

falling edge. If

Three-State

the Weak/

bit is set to ꢀ and the DOUT line returns

CS

occurs

to true three-state between conversions, then depending on the

particular processor interfacing to the AD7329, the ADD3 bit

may be valid in time for the processor to clock it in successfully.

terminated and the DOUT line returns to three-state. Depending

CS

on where the

may be updated.

signal is brought high, the addressed register

Three-State

If the Weak/

bit is set to 1, then although the DOUT

line has been driven to ADD3 since the previous conversion, it

is nevertheless so weakly driven that another device could take

control of the bus. This will not lead to a bus contention issue

because, for example, a 1ꢀ kꢃ pull-up or pull-down resister is

sufficient to overdrive the logic level of ADD3. When the

Data is clocked into the AD7329 on the SCLK falling edge. The

three MSBs on the DIN line are decoded to select which register

is addressed. The control register is a 12-bit register. If the

control register is addressed by the three MSBs, the data on the

DIN line is loaded into the control on the 1±^thSCLK rising edge.

If the sequence register or either of the range registers is

addressed, the data on the DIN line is loaded into the addressed

register on the 11^thSCLK falling edge.

Three-State

Weak/

bit is set to 1, the ADD3 is typically valid 9 ns

CS

after the

falling edge, compared with 14 ns when the DOUT

line returns to three-state at the end of the conversion.

t₁

CS

t_CONVERT

t₂

t₆

1

2

3

4

5

13

14

t₅

15

16

SCLK

DOUT

3 IDENTIFICATION BITS

t₃

t₇

t₈

t₄

t_QUIET

ADD1

ADD0

SIGN

DB11

DB10

DB2

DB1

DB0

THREE-

STATE

ADD2

THREE-STATE

t₁₀

t₉

REG

SEL1

REG

SEL2

WRITE

MSB

LSB

0

DIN

Figure 57. Serial Interface Timing Diagram (Control Register Write)

Rev. 0 | Page 35 of 40

AD7329

MICROPROCESSOR INTERFACING

The serial interface on the AD7329 allows the part to be directly

connected to a range of different microprocessors. This section

explains how to interface the AD7329 with some of the most

common microcontroller and DSP serial interface protocols.

The frequency of the serial clock is set in the SCLKDIV register.

When the instruction to transmit with TFS is given (AXꢀ =

TXꢀ), the state of the serial clock is checked. The DSP waits

until the SCLK has gone high, low, and high again before

starting the transmission. If the timer and SCLK are chosen so

that the instruction to transmit occurs on or near the rising

edge of SCLK, data can be transmitted immediately or at the

next clock edge.

AD7329 TO ADSP-21xx

The ADSP-21xx family of DSPs interface directly to the AD7329

without requiring glue logic. The V_DRIVEpin of the AD7329 takes

the same supply voltage as that of the ADSP-21xx. This allows

the ADC to operate at a higher supply voltage than its serial

interface. The SPORTꢀ on the ADSP-21xx should be configured

as shown in Table 16.

For example, the ADSP2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained, and eight master clock periods

elapse for every one SCLK period. If the timer registers are

loaded with the value 8ꢀ3, 1ꢀꢀ.± SCLKs occur between

interrupts and, subsequently, between transmit instructions.

This situation leads to nonequidistant sampling because the

transmit instruction occurs on an SCLK edge. If the number of

SCLKs between interrupts is an integer of N, equidistant

sampling is implemented by the DSP.

Table 16. SPORT0 Control Register Setup

Setting

Description

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

SLEN = 1111

ISCLK = 1

Alternative framing

Active low frame signal

Right justify data

16-bit data-word

Internal serial clock

Frame every word

AD7329 TO ADSP-BF53x

TFSR = RFSR = 1

IRFS = 0

The ADSP-BF±3x family of DSPs interfaces directly to the

AD7329 without requiring glue logic, as shown in Figure ±9.

The SPORTꢀ Receive Configuration 1 register should be set up

as outlined in Table 17.

ITFS = 1

The connection diagram is shown in Figure ±8. The ADSP-21xx

has TFSꢀ and RFSꢀ tied together. TFSꢀ is set as an output, and

RFSꢀ is set as an input. The DSP operates in alternative framing

mode, and the SPORTꢀ control register is set up as described in

Table 16. The frame synchronization signal generated on TFS is

1

AD7329¹

ADSP-BF53x

SCLK

RSCLK0

RFS0

DT0

CS

tied to

and, as with all signal processing applications, requires

equidistant sampling. However, as in this example, the timer

interrupt is used to control the sampling rate of the ADC, and

under certain conditions equidistant sampling cannot be achieved.

DIN

DR0

DOUT

V

DRIVE

1

AD7329¹

ADSP-21xx

SCLK

SCLK0

V

DD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

TFS0

RFS0

CS

Figure 59. Interfacing the AD7329 to the ADSP-BF53x

DIN

DT0

DR0

Table 17. SPORT0 Receive Configuration 1 Register

Setting

Description

DOUT

V

DRIVE

RCKFE = 1

LRFS = 1

RFSR = 1

Sample data with falling edge of RSCLK

Active low frame signal

Frame every word

Internal RFS used

Receive MSB first

Zero fill

Internal receive clock

Receive enable

V

DD

IRFS = 1

1

ADDITIONAL PINS OMITTED FOR CLARITY.

RLSBIT = 0

RDTYPE = 00

IRCLK = 1

RSPEN = 1

SLEN = 1111

TFSR = RFSR = 1

Figure 58. Interfacing the AD7329 to the ADSP-21xx

The timer registers are loaded with a value that provides an

interrupt at the required sampling interval. When an interrupt

is received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and, hence, the

reading of data.

16-bit data-word

Rev. 0 | Page 36 of 40

AD7329

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 60. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

24-Lead TSSOP

Evaluation Board

Controller Board

Package Option

AD7329BRUZ¹

–40°C to +85°C

RU-24

AD7329BRUZ-REEL¹

AD7329BRUZ-REEL7¹

EVAL-AD7329CB²

EVAL-CONTROL BRD2³

¹Z = Pb-free part.

²This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

³This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7329CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the

relevant evaluation board technical note for more information.

Rev. 0 | Page 37 of 40

AD7329

NOTES

Rev. 0 | Page 38 of 40

AD7329

NOTES

Rev. 0 | Page 39 of 40

AD7329

NOTES

registered trademarks are the property of their respective owners.

D05402-0-4/06(0)

Rev. 0 | Page 40 of 40


型号：	AD7329
厂家：	ADI
描述：	1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC 1 MSPS ， 8通道，软件可选的真双极性输入， 12位加符号位ADC
文件：	总40页 (文件大小：529K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7329 [ADI]

相关型号：

AD7329BRUZ

AD7329BRUZ

AD7329BRUZ-REEL

AD7329BRUZ-REEL7

AD73311

AD73311AR

AD73311AR-REEL

AD73311ARS

AD73311ARSZ

AD73311ARSZ-REEL

AD73311ARZ

AD73311ARZ-REEL