AD628_06 [ADI]
High Common-Mode Voltage, Programmable Gain Difference Amplifier; 高共模电压，可编程增益差动放大器
| 型号： | AD628_06 |
| 厂家： | 
ADI |
| 描述： | High Common-Mode Voltage, Programmable Gain Difference Amplifier |
| 文件： | 总20页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage,
Programmable Gain Difference Amplifier
AD628
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High common-mode input voltage range
±±12 V at VS = ±±ꢀ V
Gain range 2.± to ±22
R
R
EXT1
EXT2
+V
S
R
G
Operating temperature range: −42°C to ±ꢁꢀ°C
Supply voltage range
Dual supply: ±1.1ꢀ V to ±±ꢁ V
100kΩ
10kΩ
–IN
+IN
G = +0.1
–IN
+IN
OUT
A2
Single supply: 4.ꢀ V to 36 V
–IN
10kΩ
A1
Excellent ac and dc performance
Offset temperature stability RTI: ±2 μV/°C maximum
Offset: ±±.ꢀ V mV maximum
+IN
100kΩ
10kΩ
AD628
CMRR RTI: 7ꢀ dB minimum, dc to ꢀ22 Hz, G = +±
–V
V
S
REF
APPLICATIONS
C
FILT
High voltage current shunt sensing
Programmable logic controllers
Analog input front end signal conditioning
+ꢀ V, +±2 V, ±ꢀ V, ±±2 V, and 4 to 12 mA
Isolation
Sensor signal conditioning
Power supply monitoring
Electrohydraulic control
Figure 1.
130
120
110
100
90
V
= ±15V
S
Motor control
80
GENERAL DESCRIPTION
70
V
= ±2.5V
The AD628 is a precision difference amplifier that combines
excellent dc performance with high common-mode rejection
over a wide range of frequencies. When used to scale high
voltages, it allows simple conversion of standard control
voltages or currents for use with single-supply ADCs. A
wideband feedback loop minimizes distortion effects due to
capacitor charging of Σ-Δ ADCs.
S
60
50
40
30
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 2. CMRR vs. Frequency of the AD628
A reference pin (VREF) provides a dc offset for converting bipolar
to single-sided signals. The AD628 converts +5 V, +10 V, 5 V,
10 V, and 4 to 20 mA input signals to a single-ended output
within the input range of single-supply ADCs.
A precision 10 kΩ resistor connected to an external pin is
provided for either a low-pass filter or to attenuate large
differential input signals. A single capacitor implements a low-
pass filter. The AD628 operates from single and dual supplies
and is available in an 8-lead SOIC_N or 8-lead MSOP package.
It operates over the standard industrial temperature range of
−40°C to +85°C.
The AD628 has an input common-mode and differential-mode
operating range of 120 V. The high common-mode input
impedance makes the device well suited for high voltage
measurements across a shunt resistor. The inverting input of the
buffer amplifier is available for making a remote Kelvin
connection.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9±26, Norwood, MA 21261-9±26, U.S.A.
Tel: 7ꢁ±.319.4722
Fax: 7ꢁ±.46±.3±±3
www.analog.com
©1226 Analog Devices, Inc. All rights reserved.
AD628
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Applications..................................................................................... 15
Gain Adjustment ........................................................................ 15
Input Voltage Range................................................................... 15
Voltage Level Conversion.......................................................... 16
Current Loop Receiver .............................................................. 17
Monitoring Battery Voltages..................................................... 17
Filter Capacitor Values............................................................... 18
Kelvin Connection ..................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 13
REVISION HISTORY
3/06—Rev. E to Rev. F
Changes to Figure 29..................................................................... 14
Changes to Table 5......................................................................... 15
Changes to Gain Adjustment Section......................................... 15
Added the Input Voltage Range Section..................................... 15
Added Figure 30 ............................................................................ 15
Added Figure 31 ............................................................................ 15
Changes to Voltage Level Conversion Section .......................... 16
Changes to Figure 32..................................................................... 16
Changes to Table 6......................................................................... 16
Changes to Figure 33 and Figure 34............................................ 17
Changes to Figure 35..................................................................... 18
Changes to Kelvin Connection Section...................................... 18
Changes to Table 1............................................................................ 3
Changes to Figure 3.......................................................................... 7
Replaced Voltage Level Conversion Section............................... 16
Changes to Figure 32 and Figure 33............................................. 17
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
5/05—Rev. D to Rev. E
Changes to Table 1........................................................................... 3
Changes to Table 2........................................................................... 5
Changes to Figure 33.....................................................................18
3/05—Rev. C to Rev. D
6/03—Rev. A to Rev. B
Updated Format................................................................ Universal
Changes to Table 1........................................................................... 3
Changes to Table 2........................................................................... 5
Changes to General Description ................................................... 1
Changes to Specifications............................................................... 2
Changes to Ordering Guide........................................................... 4
Changes to TPCs 4, 5, and 6 .......................................................... 5
Changes to TPC 9............................................................................ 6
Updated Outline Dimensions...................................................... 14
4/04—Rev. B to Rev. C
Updated Format................................................................ Universal
Changes to Specifications............................................................... 3
Changes to Absolute Maximum Ratings...................................... 7
Changes to Figure 3......................................................................... 7
Changes to Figure 26.....................................................................13
Changes to Figure 27.....................................................................13
Changes to Theory of Operation.................................................14
1/03—Rev. 0 to Rev. A
Change to Ordering Guide............................................................. 4
11/02—Rev. 0: Initial Version
Rev. F | Page 2 of 20
AD628
SPECIFICATIONS
TA = 25°C, VS = 15 V, RL = 2 kΩ, REXT1 = 10 kΩ, REXT2 = ∞, VREF = 0, unless otherwise noted.
Table 1.
AD61ꢁAR
Typ
AD61ꢁARM
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DIFFERENTIAL AND OUTPUT AMPLIFIER
Gain Equation
Gain Range
G = +0.1(1+ REXT1/REXT2
See Figure 29
VCM = 0 V; RTI of input pins2;
output amplifier G = +1
)
V/V
V/V
mV
0.11
−1.5
100
+1.5
0.11
−1.5
100
+1.5
Offset Voltage
vs. Temperature
CMRR3
4
8
4
8
μV/°C
dB
RTI of input pins;
G = +0.1 to +100
75
75
500 Hz
75
70
75
70
dB
dB
(μV/V)/°C
dB
Minimum CMRR Over Temperature −40°C to +85°C
vs. Temperature
1
94
4
1
94
4
PSRR (RTI)
VS = 10 V to 18 V
77
77
Input Voltage Range
Common Mode
Differential
−120
−120
+120
+120
−120
−120
+120
+120
V
V
Dynamic Response
Small Signal Bandwidth −3 dB
Full Power Bandwidth
Settling Time
G = +0.1
600
5
600
5
kHz
kHz
μs
G = +0.1, to 0.01%, 100 V step
40
40
Slew Rate
0.3
0.3
V/μs
Noise (RTI)
Spectral Density
1 kHz
0.1 Hz to 10 Hz
300
15
300
15
nV/√Hz
μV p-p
DIFFERENTIAL AMPLIFIER
Gain
0.1
0.1
V/V
Error
−0.1
−1.5
+0.01 +0.1
−0.1
−1.5
+0.01 +0.1
%
vs. Temperature
Nonlinearity
vs. Temperature
Offset Voltage
vs. Temperature
Input Impedance
Differential
5
5
5
5
ppm/°C
ppm
ppm
mV
3
10
+1.5
8
3
10
+1.5
8
RTI of input pins
μV/°C
220
55
220
55
kΩ
kΩ
dB
Common Mode
CMRR4
RTI of input pins;
G = +0.1 to +100
75
75
500 Hz
75
70
75
70
dB
dB
Minimum CMRR Over Temperature −40°C to +85°C
vs. Temperature
Output Resistance
Error
1
10
4
1
10
4
(μV/V)/°C
kΩ
%
−0.1
+0.1
−0.1
+0.1
OUTPUT AMPLIFIER
Gain Equation
G = (1 + REXT1/REXT2
)
V/V
Nonlinearity
Offset Voltage
vs. Temperature
Output Voltage Swing
G = +1, VOUT = 10 V
RTI of output amp
0.5
0.5
ppm
−0.15
+0.15 −0.15
0.6
+14.1 −14.2
+13.6 −13.8
+0.15 mV
0.6
+14.1
+13.6
μV/°C
V
V
RL = 10 kΩ
RL = 2 kΩ
−14.2
−13.8
Rev. F | Page 3 of 20
AD628
AD61ꢁAR
Typ
AD61ꢁARM
Parameter
Conditions
Min
Max
3
Min
Typ
1.5
Max
3
Unit
nA
Bias Current
1.5
Offset Current
CMRR
0.2
0.5
0.2
0.5
nA
dB
dB
VCM = 13 V
VOUT = 13 V
130
130
130
130
Open-Loop Gain
POWER SUPPLY
Operating Range
Quiescent Current
TEMPERATURE RANGE
2.25
−40
18
1.6
2.25
−40
18
1.6
V
mA
°C
+85
+85
1 To use a lower gain, see the Gain Adjustment section.
2 The addition of the difference amplifier and output amplifier offset voltage does not exceed this specification.
(0.1)(V
)
CM
3 Error due to common mode as seen at the output: V
=[
]×[Output AmplifierGain]
OUT
75
20
10
A1=[
(0.1)(V
)
CM
75
20
4 Error due to common mode as seen at the output of A1: V
]
OUT
10
Rev. F | Page 4 of 20
AD628
TA = 25°C, VS = 5 V, RL = 2 kΩ, REXT1 = 10 kΩ, REXT2 = ∞, VREF = 2.5, unless otherwise noted.
Table 2.
AD61ꢁAR
Typ
AD61ꢁARM
Typ Max Unit
Parameter
Conditions
Min
Max Min
DIFFERENTIAL AND OUTPUT AMPLIFIER
Gain Equation
Gain Range
G = +0.1(1+ REXT1/REXT2
See Figure 29
)
V/V
V/V
0.11
100
0.11
100
Offset Voltage
VCM = 2.25 V; RTI of input pins2;
output amplifier G = +1
−3.0
+3.0 −3.0
+3.0 mV
vs. Temperature
CMRR3
6
15
75
75
70
4
6
15
μV/°C
dB
dB
dB
(μV/V)/°C
dB
RTI of input pins; G = +0.1 to +100 75
500 Hz
75
70
Minimum CMRR Over Temperature −40°C to +85°C
vs. Temperature
PSRR (RTI)
1
94
1
94
4
VS = 4.5 V to 10 V
77
77
Input Voltage Range
Common Mode4
Differential
−12
−15
+17
+15
−12
−15
+17
+15
V
V
Dynamic Response
Small Signal Bandwidth – 3 dB
Full Power Bandwidth
Settling Time
G = +0.1
440
30
15
440
30
15
kHz
kHz
μs
G = +0.1; to 0.01%, 30 V step
Slew Rate
0.3
0.3
V/μs
Noise (RTI)
Spectral Density
1 kHz
0.1 Hz to 10 Hz
350
15
350
15
nV/√Hz
μV p-p
DIFFERENTIAL AMPLIFIER
Gain
0.1
0.1
V/V
%
ppm
ppm
Error
–0.1
−2.5
+0.01 +0.1 –0.1
3
3
+0.01 +0.1
3
3
Nonlinearity
vs. Temperature
Offset Voltage
vs. Temperature
Input Impedance
Differential
10
10
RTI of input pins
+2.5 −2.5
10
+2.5 mV
10
μV/°C
220
55
220
55
kΩ
kΩ
dB
Common Mode
CMRR5
RTI of input pins; G = +0.1 to +100 75
75
500 Hz
75
70
75
70
dB
dB
Minimum CMRR Over Temperature −40°C to +85°C
vs. Temperature
Output Resistance
Error
1
10
4
1
10
4
(μV/V)/°C
kΩ
%
−0.1
+0.1 −0.1
+0.1
OUTPUT AMPLIFIER
Gain Equation
G = (1 + REXT1/REXT2
)
V/V
Nonlinearity
G = +1, VOUT = 1 V to 4 V
RTI of output amplifier
0.5
0.5
0.15 mV
0.6
4.1
4
ppm
Output Offset Voltage
vs. Temperature
Output Voltage Swing
−0.15
0.15 −0.15
0.6
4.1
4
μV/°C
V
V
RL = 10 kΩ
RL = 2 kΩ
0.9
1
0.9
1
Bias Current
Offset Current
CMRR
1.5
0.2
3
0.5
1.5
0.2
3
0.5
nA
nA
dB
dB
VCM = 1 V to 4 V
VOUT = 1 V to 4 V
130
130
130
130
Open-Loop Gain
Rev. F | Page 5 of 20
AD628
AD61ꢁAR
Typ
AD61ꢁARM
Typ Max Unit
Parameter
Conditions
Min
2.25
−40
Max Min
POWER SUPPLY
Operating Range
Quiescent Current
TEMPERATURE RANGE
+36
1.6
2.25
−40
+36
1.6
V
mA
°C
+85
+85
1 To use a lower gain, see the Gain Adjustment section.
2 The addition of the difference amplifier and output amplifier offset voltage does not exceed this specification.
(0.1)(V
)
CM
3 Error due to common mode as seen at the output: V
=[
]×[Output AmplifierGain]
OUT
75
20
10
4 Greater values of voltage are possible with greater or lesser values of VREF
(0.1)(V
.
)
CM
75
20
5 Error due to common mode as seen at the output of A1: V
A1=[
]
OUT
10
Rev. F | Page 6 of 20
AD628
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses greater than those listed under Absolute Maximum
Parameter
Rating
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage
18 V
Internal Power Dissipation
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature
See Figure 3
120 V1
120 V1
Indefinite
−65°C to +125°C
–40°C to +85°C
300°C
THERMAL CHARACTERISTICS
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
1.6
T
= 150°C
J
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1 When using 12 V supplies or higher (see the Input Voltage Range section).
8-LEAD MSOP PACKAGE
8-LEAD SOIC PACKAGE
MSOP θ (JEDEC; 4-LAYER BOARD) = 132.54°C/W
JA
SOIC θ (JEDEC; 4-LAYER BOARD) = 154°C/W
JA
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 20
AD628
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5
–IN
+IN
AD628
TOP VIEW
(Not to Scale)
–V
S
+V
S
V
R
G
REF
C
OUT
FILT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
1
2
3
4
5
6
7
8
+IN
−VS
VREF
CFILT
OUT
RG
+VS
Noninverting Input
Negative Supply Voltage
Reference Voltage Input
Filter Capacitor Connection
Amplifier Output
Output Amplifier Inverting Input
Positive Supply Voltage
Inverting Input
−IN
Rev. F | Page 8 of 20
AD628
TYPICAL PERFORMANCE CHARACTERISTICS
140
120
100
80
40
8440 UNITS
G = +0.1
35
30
25
20
15
10
5
–15V
+15V
60
+2.5V
40
20
0
0
0.1
1
10
100
1k
10k
100k
1M
–1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
INPUT OFFSET VOLTAGE (mV)
FREQUENCY (Hz)
Figure 5. Typical Distribution of Input Offset Voltage,
VS = 15 V, SOIC_N Package
Figure 8. PSRR vs. Frequency, Single and Dual Supplies
1000
25
20
15
10
5
8440 UNITS
100
0
–74
1
10
100
1k
10k
100k
–78
–82
–86
–90
–94
–98 –102 –106 –110
FREQUENCY (Hz)
CMRR (dB)
Figure 9. Voltage Noise Spectral Density, RTI, VS = 15 V
Figure 6. Typical Distribution of Common-Mode Rejection, SOIC_N Package
1000
130
120
110
100
V
= ±15V
S
90
80
70
60
50
40
30
V
= ±2.5V
S
100
1
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 10. Voltage Noise Spectral Density, RTI, VS = 2.5 V
Figure 7. CMRR vs. Frequency
Rev. F | Page 9 of 20
AD628
40
35
30
25
20
15
10
5
9638 UNITS
1s
100
90
10
0
0
0
5
10
0
1
2
3
4
5
6
7
8
9
10
TIME (Sec)
GAIN ERROR (ppm)
Figure 11. 0.1 Hz to 10 Hz Voltage Noise, RTI
Figure 14. Typical Distribution of +1 Gain Error
150
100
50
60
50
UPPER CMV LIMIT
G = +100
G = +10
G = +1
40
–40°C
30
20
+85°C
V
= 0V
REF
0
10
+25°C
0
–40°C
–50
–100
–150
–10
–20
–30
–40
G = +0.1
+85°C
LOWER CMV LIMIT
15
0
5
10
(±V)
20
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
V
S
Figure 15. Common-Mode Operating Range vs.
Power Supply Voltage for Three Temperatures
Figure 12. Small Signal Frequency Response,
VOUT = 200 mV p-p, G = +0.1, +1, +10, and +100
60
50
VS = ±15V
500μV
G = +100
100
90
RL = 1k
Ω
40
30
G = +10
G = +1
20
RL = 2k
Ω
10
0
RL = 10k
Ω
10
0
–10
–20
–30
–40
G = +0.1
4.0V
10
100
1k
10k
100k
1M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 13. Large Signal Frequency Response,
VOUT = 20 V p-p, G = +0.1, +1, +10, and +100
Figure 16. Normalized Gain Error vs. VOUT, VS = 15 V
Rev. F | Page 10 of 20
AD628
VS = ±2.5V
100μV
500mV
RL = 1kΩ
100
90
100
90
RL = 2kΩ
RL = 10kΩ
10
0
10
0
4μs
50mV
500mV
OUTPUT VOLTAGE (V)
Figure 20. Small Signal Pulse Response,
RL = 2 kΩ, CL = 0 pF, Top: Input, Bottom: Output
Figure 17. Normalized Gain Error vs. VOUT, VS = 2.5 V
4
3
2
1
0
500mV
100
90
10
0
4μs
50mV
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 18. Bias Current vs. Temperature Buffer
Figure 21. Small Signal Pulse Response,
RL = 2 kΩ, CL = 1000 pF, Top: Input, Bottom: Output
15
10
5
–40°C
–25°C
+85°C
500mV
100
+25°C
90
0
–40°C
–5
–10
–15
–25°C
+85°C
+25°C
10
0
4μs
50mV
0
5
10
15
20
25
OUTPUT CURRENT (mA)
Figure 19. Output Voltage Operating Range vs. Output Current
Figure 22. Large Signal Pulse Response,
RL = 2 kΩ, CL = 1000 pF, Top: Input, Bottom: Output
Rev. F | Page 11 of 20
AD628
100
90
100
90
5V
5V
10mV
10mV
10
0
10
0
100μs
100μs
Figure 24. Settling Time to 0.01% 0 V to −10 V Step
Figure 23. Settling Time to 0.01%, 0 V to 10 V Step
Rev. F | Page 12 of 20
AD628
TEST CIRCUITS
HP3589A
SPECTRUM ANALYZER
HP3561A
+V
S
SPECTRUM ANALYZER
+V
S
C
FILT
4
–IN
10kΩ
10kΩ
7
–
+IN
–IN
100kΩ
FET
PROBE
AD829
+
OUT
–IN
–IN
+IN
G = +0.1
+IN
100kΩ
100kΩ
10kΩ
10kΩ
+IN
8
1
+IN
–IN
OUT
G = +100
5
100kΩ
–IN
G = +0.1
+IN
AD628
10kΩ
C
R
FILT
V
G
AD628
REF
10kΩ
–V
S
3
2
6
R
V
G
REF
10kΩ
–V
S
–
10kΩ
AD707
+
Figure 25. CMRR vs. Frequency
Figure 27. Noise Tests
SCOPE
+V
S
1 VAC
+15V
G = +100
G = +100
10kΩ
10kΩ
–IN
+
+IN
OUT
20Ω
100kΩ
AD829
–
–IN
–IN
G = +0.1
+IN
+IN
100kΩ
AD628
10kΩ
V
C
R
G
REF
FILT
–V
S
Figure 26. PSRR vs. Frequency
Rev. F | Page 13 of 20
AD628
THEORY OF OPERATION
The AD628 is a high common-mode voltage difference
amplifier, combined with a user-configurable output amplifier
(see Figure 28 and Figure 29). Differential mode voltages in
excess of 120 V are accurately scaled by a precision 11:1 voltage
divider at the input. A reference voltage input is available to the
user at Pin 3 (VREF). The output common-mode voltage of the
difference amplifier is the same as the voltage applied to the
reference pin. If the uncommitted amplifier is configured for
gain, connect Pin 3 to one end of the external gain resistor to
establish the output common-mode voltage at Pin 5 (OUT).
The uncommitted amplifier is a high open-loop gain, low offset,
low drift op amp, with its noninverting input connected to the
internal 10 kΩ resistor. Both inputs are accessible to the user.
Careful layout design has resulted in exceptional common-
mode rejection at higher frequencies. The inputs are connected
to Pin 1 (+IN) and Pin 8 (−IN), which are adjacent to the power
pins, Pin 2 (−VS) and Pin 7 (+VS). Because the power pins are at
ac ground, input impedance balance and, therefore, common-
mode rejection are preserved at higher frequencies.
R
G
The output of the difference amplifier is internally connected
to a 10 kΩ resistor trimmed to better than 0.1% absolute
accuracy. The resistor is connected to the noninverting input of
the output amplifier and is accessible at Pin 4 (CFILT). A
capacitor can be connected to implement a low-pass filter, a
resistor can be connected to further reduce the output voltage,
or a clamp circuit can be connected to limit the output swing.
100kΩ
100kΩ
10kΩ
G = +0.1
–IN
+IN
–IN
+IN
OUT
A2
–IN
10kΩ
A1
+IN
10kΩ
V
C
FILT
REF
Figure 28. Simplified Schematic
C
FILT
+V
S
AD628
100kΩ
10kΩ
–IN
+IN
G = +0.1
–IN
10kΩ
A1
+IN
OUT
A2
+IN
–IN
100kΩ
10kΩ
–V
V
REF
R
S
G
R
EXT3
R
R
EXT1
REFERENCE
VOLTAGE
EXT2
Figure 29. Circuit Connections
Rev. F | Page 14 of 20
AD628
APPLICATIONS
GAIN ADJUSTMENT
INPUT VOLTAGE RANGE
The AD628 system gain is provided by an architecture
consisting of two amplifiers. The gain of the input stage
is fixed at 0.1; the output buffer is user-adjustable as
VREF and the supply voltage determine the common-mode
input voltage range. The relation is expressed by
VCM
≤11(VS+ –1.2 V) −10 VREF
(2)
UPPER
G
A2 = 1 + REXT1/REXT2. The system gain is then
VCM
≥11(VS− +1.2 V) −10 VREF
LOWER
⎛
⎜
⎝
⎞
⎟
⎟
⎠
REXT1
REXT2
⎜
GTOTAL = 0.1× 1+
(1)
where VS+ is the positive supply, VS− is the negative supply,
and 1.2 V is the headroom needed for suitable performance.
Equation 2 provides a general formula for calculating the
common-mode input voltage range. However, keep the AD628
within the maximum limits listed in Table 1 to maintain
optimal performance. This is illustrated in Figure 30 where the
maximum common-mode input voltage is limited to 120 V.
Figure 31 shows the common-mode input voltage bounds for
single-supply voltages.
At a 2 nA maximum, the input bias current of the buffer amplifier
is very low and any offset voltage induced at the buffer amplifier
by its bias current may be neglected (2 nA × 10 kΩ = 20 μV).
However, to absolutely minimize bias current effects, select REXT1
and REXT2 so that their parallel combination is 10 kΩ. If practical
resistor values force the parallel combination of REXT1 and REXT2
below 10 kΩ, add a series resistor (REXT3) to make up for the
difference. Table 5 lists several values of gain and corresponding
resistor values.
200
150
100
50
Table 5. Nearest Standard 1% Resistor Values for
Various Gains1
Total Gain
(V/V)
A1 Gain
(V/V)
REXT±
(Ω)
REXT1
(Ω)
REXT3
(Ω)
MAXIMUM INPUT COMMON-MODE
0
0.1
0.2
0.25
0.5
1
2
5
10
1
2
10 k
20 k
∞
20 k
0
0
0
0
0
0
0
0
VOLTAGE WHEN V
= GND
REF
–50
–100
–150
–200
2.5
5
10
20
50
100
25.9 k
49.9 k
100 k
200 k
499 k
1 M
18.7 k
12.4 k
11 k
10.5 k
10.2 k
10.2 k
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±V)
1 See Figure 29.
Figure 30. Input Common-Mode Voltage vs. Supply Voltage
for Dual Supplies
To set the system gain to less than 0.1, create an attenuator by
placing Resistor REXT4 from Pin 4 (CFILT) to the reference voltage.
A divider is formed by the 10 kΩ resistor that is in series with
the positive input of A2 and Resistor REXT4. A2 is configured for
unity gain.
100
80
60
40
Using a divider and setting A2 to unity gain yields
20
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
REXT4
10 kꢀ + REXT4
MAXIMUM INPUT COMMON-MODE
GW / DIVIDER = 0.1 ×
×1
0
VOLTAGE WHEN V
= MIDSUPPLY
REF
–20
–40
–60
–80
0
2
4
6
8
10
12
14
16
SINGLE-SUPPLY VOLTAGE (V)
Figure 31. Input Common-Mode Voltage vs.
Supply Voltage for Single Supplies
Rev. F | Page 15 of 20
AD628
The differential input voltage range is constrained to the linear
operation of the internal amplifiers A1 and A2. The voltage
applied to the inputs of A1 and A2 should be between
VS− + 1.2 V and VS+ − 1.2 V. Similarly, the outputs of A1 and A2
should be kept between VS− + 0.9 V and VS+ − 0.9 V.
Designing such an application can be done in a few simple
steps, including the following:
•
Determine the required gain. For example, if the input
voltage must be transformed from 10 V to 0 V to +5 V,
the gain is +5/+20 or +0.25.
•
Determine if the circuit common-mode voltage should be
changed. An AD7940 ADC is illustrated for this example.
When operating from a 5 V supply, the common-mode
voltage of the AD7940 is half the supply, or 2.5 V. If the
AD628 reference pin and the lower terminal of the 10 kΩ
resistor are connected to a 2.5 V voltage source, the output
common-mode voltage is 2.5 V.
VOLTAGE LEVEL CONVERSION
Industrial signal conditioning and control applications typically
require connections between remote sensors or amplifiers and
centrally located control modules. Signal conditioners provide
output voltages of up to 10 V full scale. However, ADCs or
microprocessors operating on single 3.3 V to 5 V logic supplies
are now the norm. Thus, the controller voltages require further
reduction in amplitude and reference.
Table 6 shows resistor and reference values for commonly used
single-supply converter voltages. REXT3 is included as an option
to balance the source impedance into A2. This is described in
more detail in the Gain Adjustment section.
Furthermore, voltage potentials between locations are seldom
compatible, and power line peaks and surges can generate
destructive energy between utility grids. The AD628 offers an
ideal solution to both problems. It attenuates otherwise destruc-
tive signal voltage peaks and surges by a factor of 10 and shifts
the differential input signal to the desired output voltage.
Table 6. Nearest 1% Resistor Values for Voltage Level
Conversion Applications
ADC
Supply
Desired
Output
Input
VREF
REXT±
(kΩ)
REXT1
(kΩ)
Voltage (V) Voltage (V) Voltage (V) (V)
Conversion from voltage-driven or current-loop systems is
easily accomplished using the circuit shown in Figure 32. This
shows a circuit for converting inputs of various polarities and
amplitudes to the input of a single-supply ADC.
10
5
5
5
5
5
3
3
3
3
2.5
2.5
2.5
0
15
10
10
10
10
10
10
10
10
2.5
39.7
39.7
89.8
2.49
15
10
2.5
5
2.5
0
To adjust common-mode output voltage, connect Pin 3 (VREF
)
10
5
1.25
1.25
1.25
1.25
1.25
1.25
0
and the lower end of the 10 kΩ resistor to the desired voltage.
The output common-mode voltage is the same as the reference
voltage.
10
5
15
0
39.7
Rev. F | Page 16 of 20
AD628
+12V
–12V
0.1μF
10μF
0.1μF
10μF
2
7
+Vs
–Vs
–IN
8
AD628
10kΩ
A1
100kΩ
100kΩ
SERIAL DATA
+/–10V
SCLK
SDATA
CS
4
5
6
10kΩ
+IN
1
49.9Ω
AD7940
3
A2
V
5
IN
V
GND
2
DD
33nF
10kΩ
1
V
C
FILT
REF
R
G
6
3
4
10μF
0.1μF
R
EXT1
15kΩ
15nF
V
V
IN
OUT
+12V
2
3
REF195
4
0.1μF
10μF
R
10kΩ
EXT2
8
5
6
2
AD8606
2/2
7
AD8606
1/2
1
AD628 REFERENCE VOLTAGE
4
3
10kΩ
10kΩ
Figure 32. Level Shifter
MONITORING BATTERY VOLTAGES
CURRENT LOOP RECEIVER
Figure 34 illustrates how the AD628 is used to monitor a battery
charger. Voltages approximately eight times the power supply
voltage can be applied to the input with no damage. The resistor
divider action is well-suited for the measurement of many
power supply applications, such as those found in battery
chargers or similar equipment.
Analog data transmitted on a 4 to 20 mA current loop can be
detected with the receiver shown in Figure 33. The AD628 is an
ideal choice for such a function because the current loop is
driven with a compliance voltage sufficient to stabilize the loop,
and the resultant common-mode voltage often exceeds com-
monly used supply voltages. Note that with large shunt values, a
resistance of equal value must be inserted in series with the
inverting input to compensate for an error at the noninverting
input.
V
= 15V
+15V –15V
CM
3
7
2
4
AD628
10kΩ
249Ω
100kΩ
1
8
10kΩ
0V TO 5V
TO ADC
5
249Ω
100kΩ
10kΩ
6
I = 4 TO 20mA
210kΩ
100kΩ
9.53kΩ
+2.5V
Figure 33. Level Shifter for 4 to 20 mA Current Loop
Rev. F | Page 17 of 20
AD628
5V
+V
S
nV
(V)
–IN
100kΩ
100kΩ
10kΩ
10kΩ
BAT
0V TO 5V
TO ADC
+IN
–IN
OUT
A2
G = +0.1
A1
R
10kΩ
–IN
+IN
EXT1
CHARGING
CIRCUIT
+1.5V
BATTERY
R
G
+IN
OTHER
BATTERIES IN
CHARGING
CIRCUIT
10kΩ
AD628
–V
V
C
FILT
S
REF
Figure 34. Battery Voltage Monitor
FILTER CAPACITOR VALUES
KELVIN CONNECTION
Connect a capacitor to Pin 4 (CFILT) to implement a low-pass
filter. The capacitor value is
In certain applications, it may be desirable to connect the
inverting input of an amplifier to a remote reference point.
This eliminates errors resulting in circuit losses in interconnect-
ing wiring. The AD628 is particularly suited for this type of
connection. In Figure 35, a 10 kΩ resistor added in the feedback
matches the source impedance of A2. This is described in more
detail in the Gain Adjustment section.
C = 15.9/ft
(
ꢁF
)
where ft is the desired 3 dB filter frequency.
Table 7 shows several frequencies and their closest standard
capacitor values.
5V
Table 7. Capacitor Values for Various Filter Frequencies
+V
S
Frequency (Hz)
Capacitor Value (μF)
–IN
100kΩ
100kΩ
10kΩ
10kΩ
CIRCUIT
LOSS
10
50
60
100
400
1 k
5 k
10 k
1.5
0.33
0.27
0.15
0.039
0.015
0.0033
0.0015
+IN
A2
–IN
OUT
G = +0.1
A1
–IN
+IN
10kΩ
R
G
LOAD
+IN
10kΩ
AD628
V
–V
REF
C
FILT
S
V
/2
S
Figure 35. Kelvin Connection
Rev. F | Page 18 of 20
AD628
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
5.15
4.90
4.65
8
1
5
4
3.20
3.00
2.80
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
PIN 1
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
0.65 BSC
1.75 (0.0688)
1.35 (0.0532)
0.95
0.85
0.75
0.25 (0.0098)
1.10 MAX
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0.80
0.60
0.40
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
8°
0°
0.15
0.00
SEATING
PLANE
0.38
0.22
0.23
0.08
0.40 (0.0157)
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 36. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD628AR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Description
Package Option
Branding
8-Lead SOIC_N
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
AD628AR-REEL
AD628AR-REEL7
AD628ARZ1
AD628ARZ-RL1
AD628ARZ-R71
AD628ARM
AD628ARM-REEL
AD628ARM-REEL7
AD628ARMZ1
AD628ARMZ-RL1
AD628ARMZ-R71
AD628-EVAL
8-Lead SOIC_N 13" Reel
8-Lead SOIC_N 7" Reel
8-Lead SOIC_N
8-Lead SOIC_N 13" Reel
8-Lead SOIC_N 7" Reel
8-Lead MSOP
8-Lead MSOP 13" Reel
8-Lead MSOP 7" Reel
8-Lead MSOP
8-Lead MSOP 13" Reel
8-Lead MSOP 7" Reel
Evaluation Board
JGA
JGA
JGA
JGZ
JGZ
JGZ
1 Z = Pb-free part.
Rev. F | Page 19 of 20
AD628
NOTES
©1226 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C21991-2-3/26(F)
Rev. F | Page 20 of 20
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