AD629-EVAL [ADI]
High Common-Mode Voltage, Difference Amplifier; 高共模电压，差分放大器
| 型号： | AD629-EVAL |
| 厂家： | 
ADI |
| 描述： | High Common-Mode Voltage, Difference Amplifier |
| 文件： | 总16页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage,
Difference Amplifier
AD629
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Improved replacement for: INA117P and INA117KU
±270 V common-mode voltage range
Input protection to
±±00 V common mode
±±00 V differential mode
21.1kΩ
380kΩ
380kΩ
380kΩ
8
7
6
5
NC
+V
1
2
3
4
REF(–)
–IN
S
+IN
OUTPUT
REF(+)
20kΩ
–V
S
Wide power supply range (±2.± V to ±18 V)
±10 V output swing on ±12 V supply
1 mA maximum power supply current
AD629
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
HIGH ACCURACY DC PERFORMANCE
3 ppm maximum gain nonlinearity (AD629B)
20 μV/°C maximum offset drift (AD629A)
10 μV/°C maximum offset drift (AD629B)
10 ppm/°C maximum gain drift
The AD629 is a difference amplifier with a very high input,
common-mode voltage range. It is a precision device that allows
the user to accurately measure differential signals in the
presence of high common-mode voltages up to ±2ꢀ7 ꢁ.
The AD629 can replace costly isolation amplifiers in
applications that do not require galvanic isolation. The device
operates over a ±2ꢀ7 ꢁ common-mode voltage range and has
inputs that are protected from common-mode or differential
mode transients up to ±±77 ꢁ.
EXCELLENT AC SPECIFICATIONS
77 dB minimum CMRR @ ±00 Hz (AD629A)
86 dB minimum CMRR @ ±00 Hz (AD629B)
±00 kHz bandwidth
The AD629 has low offset, low offset drift, low gain error drift,
low common-mode rejection drift, and excellent CMRR over a
wide frequency range.
APPLICATIONS
High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
The AD629 is available in low cost, 8-lead PDIP and 8-lead
SOIC packages. For all packages and grades, performance is
guaranteed over the industrial temperature range of −47°C to
+8±°C.
Isolation
100
95
90
85
80
75
70
65
60
55
50
2mV/DIV
60V/DIV
–240
–120
0
120
240
20
100
1k
10k 20k
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 3. Error Voltage vs. Input Common-Mode Voltage
Figure 2. Common-Mode Rejection Ratio vs. Frequency
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999-2007 Analog Devices, Inc. All rights reserved.
AD629
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Connections...................................................................... 17
Single-Supply Operation ........................................................... 17
System-Level Decoupling and Grounding.............................. 17
Using a Large Sense Resistor..................................................... 11
Output Filtering.......................................................................... 11
Output Current and Buffering.................................................. 12
A Gain of 19 Differential Amplifier......................................... 12
Error Budget Analysis Example 1 ............................................ 12
Error Budget Analysis Example 2 ............................................ 13
Outline Dimensions....................................................................... 14
Ordering Guide............................................................................... 1±
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Typical Performance Characteristics ............................................. ±
Theory of Operation ........................................................................ 9
Applications..................................................................................... 17
REVISION HISTORY
3/07—Rev. A to Rev. B
Updated Format and Layout .............................................Universal
Changes to Ordering Guide .......................................................... 1±
3/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
Rev. B | Page 2 of 16
AD629
SPECIFICATIONS
TA = 2±°C, ꢁS = ±1± ꢁ, unless otherwise noted.
Table 1.
AD629A
Typ
AD629B
Typ
Parameter
GAIN
Condition
Min
Max
Min
Max
Unit
VOUT = 1ꢀ V, RL = 2 kΩ
Nominal Gain
Gain Error
Gain Nonlinearity
1
ꢀ.ꢀ1
4
1
3
1
ꢀ.ꢀ1
4
1
3
V/V
%
ppm
ppm
ppm/°C
ꢀ.ꢀ5
1ꢀ
ꢀ.ꢀ3
1ꢀ
3
RL = 1ꢀ kΩ
TA = TMIN to TMAX
Gain vs. Temperature
OFFSET VOLTAGE
Offset Voltage
1ꢀ
1
1ꢀ
ꢀ.2
ꢀ.1
ꢀ.5
1
mV
mV
VS = 5 V
vs. Temperature
vs. Supply (PSRR)
INPUT
TA = TMIN to TMAX
VS = 5 V to 15 V
6
1ꢀꢀ
2ꢀ
3
11ꢀ
1ꢀ
μV/°C
dB
84
9ꢀ
Common-Mode Rejection Ratio
VCM = 25ꢀ V dc
TA = TMIN to TMAX
VCM = 5ꢀꢀ V p-p, dc to 5ꢀꢀ Hz
VCM = 5ꢀꢀ V p-p, dc to 1 kHz
Common mode
77
73
77
88
88
86
82
86
96
9ꢀ
dB
dB
dB
dB
V
Operating Voltage Range
27ꢀ
13
27ꢀ
13
Differential
V
Input Operating Impedance
Common mode
Differential
2ꢀꢀ
8ꢀꢀ
2ꢀꢀ
8ꢀꢀ
kΩ
kΩ
OUTPUT
Operating Voltage Range
RL = 1ꢀ kΩ
13
13
V
RL = 2 kΩ
12.5
12.5
V
VS = 12 V, RL = 2 kΩ
1ꢀ
1ꢀ
V
Output Short-Circuit Current
Capacitive Load
25
25
mA
pF
Stable operation
1ꢀꢀꢀ
1ꢀꢀꢀ
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
Slew Rate
Full Power Bandwidth
Settling Time
5ꢀꢀ
2.1
28
15
12
5
5ꢀꢀ
2.1
28
15
12
5
kHz
V/μs
kHz
μs
μs
μs
1.7
1.7
VOUT = 2ꢀ V p-p
ꢀ.ꢀ1%, VOUT = 1ꢀ V step
ꢀ.1%, VOUT = 1ꢀ V step
ꢀ.ꢀ1%, VCM = 1ꢀ V step, VDIFF = ꢀ V
OUTPUT NOISE VOLTAGE
ꢀ.ꢀ1 Hz to 1ꢀ Hz
Spectral Density, ≥1ꢀꢀ Hz1
15
55ꢀ
15
55ꢀ
μV p-p
nV/√Hz
POWER SUPPLY
Operating Voltage Range
Quiescent Current
2.5
18
1
2.5
18
1
V
mA
mA
VOUT = ꢀ V
TMIN to TMAX
ꢀ.9
1.2
ꢀ.9
1.2
TEMPERATURE RANGE
For Specified Performance
TA = TMIN to TMAX
−4ꢀ
+85
−4ꢀ
+85
°C
1 See Figure 19.
Rev. B | Page 3 of 16
AD629
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Supply Voltage, VS
Internal Power Dissipation1
18 V
8-Lead PDIP (N)
8-Lead SOIC (R)
See Figure 4
See Figure 4
3ꢀꢀ V
5ꢀꢀ V
Indefinite
–VS − ꢀ.3 V to +VS + ꢀ.3 V
15ꢀ°C
−55°C to +125°C
−65°C to +15ꢀ°C
3ꢀꢀ°C
Input Voltage Range, Continuous
Common-Mode and Differential, 1ꢀ sec
Output Short-Circuit Duration
Pin 1 and Pin 5
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 6ꢀ sec)
2.0
T
= 150°C
J
8-LEAD PDIP
1.5
1.0
0.5
0
1 Specification is for device in free air:
8-Lead PDIP, θJA = 1ꢀꢀ°C/W;
8-Lead SOIC, θJA = 155°C/W.
8-LEAD SOIC
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP
ESD CAUTION
Rev. B | Page 4 of 16
AD629
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 2±°C, ꢁS = ±1± ꢁ, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
400
360
320
280
240
200
160
120
80
T
= +25°C
A
T
= +85°C
A
T
= –40°C
A
40
0
100
1k
10k
100k
1M
10M
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
POWER SUPPLY VOLTAGE (±V)
Figure 5. Common-Mode Rejection Ratio vs. Frequency
Figure 8. Common-Mode Operating Range vs. Power Supply Voltage
R
= 2kΩ
2mV/DIV
= ±18V
R
= 10kΩ
L
L
V
= ±18V
S
V
S
V
= ±15V
S
V
= ±15V
S
V
V
= ±12V
= ±10V
S
V
= ±12V
S
S
4V/DIV
16
4V/DIV
16
S
V
= ±10V
–8
–20 –16 –12
–8
–4
0
4
8
12
20
–20 –16 –12
–4
0
4
8
12
20
V
(V)
V
(V)
OUT
OUT
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 2 kΩ (Curves Offset for Clarity)
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 10 kΩ (Curves Offset for Clarity)
R
= 1kΩ
L
V
V
= ±5V, R = 10kΩ
L
S
V
= ±18V
S
V
= ±15V
S
= ±5V, R = 2kΩ
S
L
V
= ±5V, R = 1kΩ
V
V
= ±12V
S
L
S
S
1V/DIV
16
V
= ±2.5V, R = 1kΩ
= ±10V
–4
4V/DIV
16
S
L
–20 –16 –12
–8
–4
0
4
8
12
20
–20 –16 –12
–8
0
4
8
12
20
V
(V)
V
(V)
OUT
OUT
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage (Curves Offset for Clarity)
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 1 kΩ (Curves Offset for Clarity)
Rev. B | Page 5 of 16
AD629
20µV/DIV
40µV/DIV
V
= ±15V
V
= ±15V
S
S
R
= 10kΩ
R
= 2kΩ
L
L
2.5V/DIV
10
2V/DIV
8
–10
–5
0
5
–10
–8
–6
–4
–2
0
2
4
6
10
V
(V)
V
(V)
OUT
OUT
Figure 11. Gain Nonlinearity; VS = 15 V, RL = 10 kΩ
Figure 14. Gain Nonlinearity; VS = 15 V, RL = 2kΩ
14.0
13.0
–40°C
+25°C
20µV/DIV
V
R
= ±12V
= 10kΩ
S
–40°C
L
12.0
11.0
V = ±15V
+85°C
S
10.0
9.0
–11.5
–12.0
–12.5
–13.0
–13.5
–40°C
2V/DIV
8
+25°C
18
+85°C
14
–10
–8
–6
–4
–2
0
2
4
6
10
0
2
4
6
8
10
12
16
20
V
(V)
OUT
OUTPUT CURRENT (mA)
Figure 15. Output Voltage Operating Range vs. Output Current; VS = 15 V
Figure 12. Gain Nonlinearity; VS = 12 V, RL =10 kΩ
11.5
+85°C
40µV/DIV
V
R
= ±5V
= 1kΩ
10.5
9.5
–40°C
S
–40°C
L
8.5
V = ±12V
+25°C
S
7.5
+85°C
6.5
–9.0
–9.5
–10.0
–10.5
–11.0
–40°C
+25°C
18
0.6V/DIV
2.4
+85°C
10
–3.0 –2.4 –1.8 –1.2 –0.6
0
0.6
(V)
1.2
1.8
3.0
0
2
4
6
8
12
14
16
20
V
OUT
OUTPUT CURRENT (mA)
Figure 13. Gain Nonlinearity; VS = 5 V, RL = 1 kΩ
Figure 16. Output Voltage Operating Range vs. Output Current; VS = 12 V
Rev. B | Page 6 of 16
AD629
4.5
3.5
2.5
1.5
0.5
+85°C
–40°C
+25°C
G = +1
–40°C
R
C
= 2kΩ
= 1000pF
L
L
+85°C
V = ±5V
S
+85°C
–2.0
–2.5
–3.0
–3.5
–4.0
–40°C
+25°C
18
+85°C
6
+25°C
2
25mV/DIV
4µs/DIV
0
4
8
10
12
14
16
20
OUTPUT CURRENT (mA)
Figure 17. Output Voltage Operating Range vs. Output Current; VS = 5 V
Figure 20. Small Signal Pulse Response
120
+V
–V
S
110
100
90
G = +1
S
R
C
= 2kΩ
= 1000pF
L
L
80
70
60
50
40
30
25mV/DIV
4µs/DIV
0.1
1.0
10
100
1k
10k
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency
Figure 21. Small Signal Pulse Response
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
G = +1
R
C
= 2kΩ
= 1000pF
L
L
5V/DIV
5µs/DIV
0.01
0.1
1.0
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 19. Voltage Noise Spectral Density vs. Frequency
Figure 22. Large Signal Pulse Response
Rev. B | Page 7 of 16
AD629
5V/DIV
0V
5V/DIV
+10V
V
V
OUT
OUT
–10V
0V
OUTPUT
ERROR
OUTPUT
ERROR
1mV = 0.01%
10µs/DIV
1mV = 0.01%
10µs/DIV
1mV/DIV
1mV/DIV
Figure 26. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ
Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ
300
350
N = 2180
N = 2180
300
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
250
250
200
200
150
100
50
150
100
50
0
0
–150
–900
–600
–300
0
300
600
900
–100
–50
0
50
100
150
OFFSET VOLTAGE (µV)
COMMON-MODE REJECTION RATIO (ppm)
Figure 27. Typical Distribution of Offset Voltage; Package Option N-8
Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8
400
400
N = 2180
350
N = 2180
350
n ≈ 200 PCS. FROM
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
300
10 ASSEMBLY LOTS
300
250
200
150
100
50
250
200
150
100
50
0
–600
0
–600
–400
–200
0
200
400
600
–400
–200
0
200
400
600
+1 GAIN ERROR (ppm)
–1 GAIN ERROR (ppm)
Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8
Figure 25. Typical Distribution of −1 Gain Error; Package Option N-8
Rev. B | Page 8 of 16
AD629
THEORY OF OPERATION
The AD629 is a unity gain, differential-to-single-ended
amplifier (diff amp) that can reject extremely high common-
mode signals (in excess of 2ꢀ7 ꢁ with 1± ꢁ supplies). It consists
of an operational amplifier (op amp) and a resistor network.
To reduce output drift, the op amp uses super beta transistors
in its input stage. The input offset current and its associated
temperature coefficient contribute no appreciable output
voltage offset or drift, which has the added benefit of reducing
voltage noise because the corner where 1/f noise becomes
dominant is below ± Hz. To reduce the dependence of gain
accuracy on the op amp, the open-loop voltage gain of the op
amp exceeds 27 million, and the PSRR exceeds 147 dB.
To achieve high common-mode voltage range, an internal
resistor divider (Pin 3 or Pin ±) attenuates the noninverting
signal by a factor of 27. Other internal resistors (Pin 1, Pin 2,
and the feedback resistor) restore the gain to provide a differential
gain of unity. The complete transfer function equals
21.1kΩ
380kΩ
380kΩ
380kΩ
8
7
6
5
NC
+V
1
2
3
4
REF(–)
–IN
V
OUT = ꢁ (+IN) − ꢁ (−IN)
S
Laser wafer trimming provides resistor matching so that
common-mode signals are rejected while differential input
signals are amplified.
+IN
OUTPUT
REF(+)
20kΩ
–V
S
AD629
NC = NO CONNECT
Figure 29. Functional Block Diagram
Rev. B | Page 9 of 16
AD629
APPLICATIONS
+V
S
AD629
REF (–)
21.1kΩ
BASIC CONNECTIONS
NC
1
2
3
4
8
7
6
5
Figure 37 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between ±3 ꢁ and ±18 ꢁ
is applied between Pin ꢀ and Pin 4. Both supplies should be
decoupled close to the pins using 7.1 μF capacitors. Electrolytic
capacitors of 17 μF, also located close to the supply pins, may be
required if low frequency noise is present on the power supply.
While multiple amplifiers can be decoupled by a single set of
17 μF capacitors, each in amp should have its own set of 7.1 μF
capacitors so that the decoupling point can be located right at
the IC’s power pins.
380kΩ 380kΩ
–IN
+IN
V
+V
0.1µF
X
S
I
R
SHUNT
SHUNT
380kΩ
V
Y
20kΩ
–V
S
REF (+)
OUTPUT = V
OUT
– V
REF
NC = NO CONNECT
V
REF
Figure 31. Operation with a Single Supply
+V
S
Applying a reference voltage to REF(+) and REF(–) and
+3V TO +18V
NC
AD629
REF (–)
21.1kΩ
1
2
3
4
8
7
6
5
operating on a single supply reduces the input common-mode
range of the AD629. The new input common-mode range
depends upon the voltage at the inverting and noninverting
inputs of the internal operational amplifier, labeled ꢁX and ꢁY
in Figure 31. These nodes can swing to within 1 ꢁ of either rail.
Therefore, for a (single) supply voltage of 17 ꢁ, ꢁX and ꢁY can
range between 1 ꢁ and 9 ꢁ. If ꢁREF is set to ± ꢁ, the permissible
common-mode range is +8± ꢁ to –ꢀ± ꢁ. The common-mode
voltage ranges can be calculated by
380kΩ 380kΩ
–IN
+IN
(SEE
TEXT)
+V
0.1µF
S
I
R
SHUNT
SHUNT
380kΩ
V
= I
SHUNT
× R
SHUNT
OUT
20kΩ
–V
S
REF (+)
(SEE
TEXT)
0.1µF
NC = NO CONNECT
–V
S
–3V TO –18V
Figure 30. Basic Connections
V
CM (±) = 27 VX/VY(±) − 19 VREF
The differential input signal, which typically results from a load
current flowing through a small shunt resistor, is applied to
Pin 2 and Pin 3 with the polarity shown to obtain a positive
gain. The common-mode range on the differential input signal
can range from −2ꢀ7 ꢁ to +2ꢀ7 ꢁ, and the maximum differential
range is ±13 ꢁ. When configured as shown in Figure 37, the
device operates as a simple gain-of-1, differential-to-single-
ended amplifier; the output voltage being the shunt resistance
times the shunt current. The output is measured with respect to
Pin 1 and Pin ±.
SYSTEM-LEVEL DECOUPLING AND GROUNDING
The use of ground planes is recommended to minimize the
impedance of ground returns (and therefore the size of dc
errors). Figure 32 shows how to work with grounding in a
mixed-signal environment, that is, with digital and analog
signals present. To isolate low level analog signals from a noisy
digital environment, many data acquisition components have
separate analog and digital ground returns. All ground pins
from mixed-signal components, such as ADCs, should return
through a low impedance analog ground plane. Digital ground
lines of mixed-signal converters should also be connected to the
analog ground plane. Typically, analog and digital grounds
should be separated; however, it is also a requirement to
minimize the voltage difference between digital and analog
grounds on a converter, to keep them as small as possible
(typically <7.3 ꢁ). The increased noise, caused by the
converter’s digital return currents flowing through the analog
ground plane, is typically negligible. Maximum isolation
between analog and digital is achieved by connecting the ground
planes back at the supplies. Note that Figure 32 suggests a “star”
ground system for the analog circuitry, with all ground lines
being connected, in this case, to the ADC’s analog ground.
However, when ground planes are used, it is sufficient to
connect ground pins to the nearest point on the low impedance
ground plane.
Pin 1 and Pin ± (REF(–) and REF(+)) should be grounded for a
gain of unity and should be connected to the same low impedance
ground plane. Failure to do this results in degraded common-
mode rejection. Pin 8 is a no connect pin and should be left open.
SINGLE-SUPPLY OPERATION
Figure 31 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 ꢁ of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+)
and REF(–) to a low impedance reference voltage (some ADCs
provide this voltage as an output), which is capable of sinking
current. Therefore, for a single supply of 17 ꢁ, ꢁREF may be set
to ± ꢁ for a bipolar input signal. This allows the output to swing
±3 ꢁ around the central ± ꢁ reference voltage. Alternatively, for
unipolar input signals, ꢁREF can be set to about 2 ꢁ, allowing the
output to swing from 2 ꢁ (for a 7 ꢁ input) to within 2 ꢁ of the
positive rail.
Rev. B | Page 1ꢀ of 16
AD629
ANALOG POWER
SUPPLY
DIGITAL
POWER SUPPLY
GND +5V
Table 3 shows some sample error voltages generated by a
common-mode voltage of 277 ꢁ dc with shunt resistors from
27 Ω to 2777 Ω. Assuming that the shunt resistor is selected to
use the full ±17 ꢁ output swing of the AD629, the error voltage
becomes quite significant as RSHUNT increases.
–5V
+5V
GND
0.1µF
0.1µF
0.1µF 0.1µF
1
6
14
AGND DGND
Table 3. Error Resulting from Large Values of RSHUNT
(Uncompensated Circuit)
4
7
V
DD
V
DD
GND
12
–V
+V
S
S
3
2
+IN
–IN
MICROPROCESSOR
V
V
6
4
3
OUTPUT
AD629
IN1 AD7892-2
RS (Ω)
2ꢀ
Error VOUT (V)
Error Indicated (mA)
REF(–) REF(+)
IN2
ꢀ.ꢀ1
ꢀ.498
1
ꢀ.5
1
5
1ꢀꢀꢀ
2ꢀꢀꢀ
ꢀ.498
ꢀ.5
Figure 32. Optimal Grounding Practice for a Bipolar Supply Environment
with Separate Analog and Digital Supplies
POWER SUPPLY
To measure low current or current near zero in a high common-
mode environment, an external resistor equal to the shunt
resistor value can be added to the low impedance side of the
shunt resistor, as shown in Figure 34.
+5V
GND
0.1µF
0.1µF
0.1µF
+V
S
7
4
AD629
REF (–)
V
AGND DGND
21.1kΩ
DD
+V
–V
S
NC
1
2
3
4
8
7
6
5
S
V
GND
DD
3
2
+IN
–IN
V
V
6
OUTPUT
IN1
AD629
MICROPROCESSOR
R
R
380kΩ 380kΩ
COMP
–IN
+IN
ADC
IN2
REF(–) REF(+)
0.1µF
+V
S
I
1
5
SHUNT
SHUNT
380kΩ
V
OUT
Figure 33. Optimal Ground Practice in a Single-Supply Environment
20kΩ
–V
REF (+)
S
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 33 shows how to
minimize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive Pin REF(+)
and Pin REF(–). This means that the reference must be capable
of sourcing and sinking a current equal to ꢁCM/277 kΩ. As in
the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should connect at the power supply’s ground pin. Separate
traces (or power planes) should run from the power supply to
the supply pins of the digital and analog circuits. Ideally, each
device should have its own power supply trace, but these can be
shared by a number of devices, as long as a single trace is not
used to route current to both digital and analog circuitry.
0.1µF
–V
S
NC = NO CONNECT
Figure 34. Compensating for Large Sense Resistors
OUTPUT FILTERING
A simple 2-pole, low-pass Butterworth filter can be implemented
using the OP1ꢀꢀ after the AD629 to limit noise at the output, as
shown in Figure 3±. Table 4 gives recommended component
values for various corner frequencies, along with the peak-to-
peak output noise for each case.
+V
S
AD629
REF (–)
21.1kΩ
NC
1
2
3
4
8
7
6
5
+V
S
C1
0.1µF
R1
0.1µF
0.1µF
380kΩ 380kΩ
–IN
+IN
+V
S
V
OP177
OUT
R2
C2
380kΩ
USING A LARGE SENSE RESISTOR
20kΩ
REF (+)
–V
S
Insertion of a large value shunt resistance across the input pins,
Pin 2 and Pin 3, will imbalance the input resistor network,
introducing a common-mode error. The magnitude of the error
will depend on the common-mode voltage and the magnitude
–V
S
0.1µF
NC = NO CONNECT
Figure 35. Filtering of Output Noise Using a 2-Pole Butterworth Filter
of RSHUNT
.
Table 4. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency
R1
R2
C1
C2
Output Noise (p-p)
No Filter
5ꢀ kHz
5 kHz
5ꢀꢀ Hz
5ꢀ Hz
3.2 mV
1 mV
ꢀ.32 mV
1ꢀꢀ μV
32 μV
2.94 kΩ 1%
2.94 kΩ 1%
2.94 kΩ 1%
2.7 kΩ 1ꢀ%
1.58 kΩ 1%
1.58 kΩ 1%
1.58 kΩ 1%
1.5 kΩ 1ꢀ%
2.2 nF 1ꢀ%
22 nF 1ꢀ%
22ꢀ nF 1ꢀ%
2.2 μF 2ꢀ%
1 nF 1ꢀ%
1ꢀ nF 1ꢀ%
ꢀ.1 μF 1ꢀ%
1 μF 2ꢀ%
Rev. B | Page 11 of 16
AD629
OUTPUT CURRENT AND BUFFERING
ERROR BUDGET ANALYSIS EXAMPLE 1
The AD629 is designed to drive loads of 2 kꢂ to within 2 ꢁ of
the rails but can deliver higher output currents at lower output
voltages (see Figure 1±). If higher output current is required, the
output of the AD629 should be buffered with a precision op amp,
such as the OP113, as shown in Figure 36. This op amp can swing
to within 1 ꢁ of either rail while driving a load as small as 677 ꢂ.
In the dc application that follows, the 17 A output current from
a device with a high common-mode voltage (such as a power
supply or current-mode amplifier) is sensed across a 1 ꢂ shunt
resistor (see Figure 38). The common-mode voltage is 277 ꢁ,
and the resistor terminals are connected through a long pair of
lead wires located in a high noise environment, for example,
±7 Hz/67 Hz, 447 ꢁ ac power lines. The calculations in Table ±
assume an induced noise level of 1 ꢁ at 67 Hz on the leads, in
addition to a full-scale dc differential voltage of 17 ꢁ. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.
+V
S
AD629
REF (–)
21.1kΩ
NC
1
2
3
4
8
7
6
5
0.1µF
380kΩ 380kΩ
–IN
+IN
0.1µF
0.1µF
380kΩ
V
OP113
OUT
20kΩ
REF (+)
–V
S
OUTPUT
CURRENT
AD629
REF (–)
21.1kΩ
0.1µF
–V
S
10 AMPS
200V DC
TO GROUND
NC
NC = NO CONNECT
1
2
3
4
8
7
6
5
CM
380kΩ 380kΩ
–IN
+IN
+V
Figure 36. Output Buffering Application
S
0.1µF
1Ω
SHUNT
380kΩ
A GAIN OF 19 DIFFERENTIAL AMPLIFIER
V
OUT
While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected, as shown in Figure 3ꢀ, to give a precise gain of 19.
However, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a
temperature sensor, such as the AD±97.
20kΩ
REF (+)
–V
S
60Hz
0.1µF
POWER LINE
NC = NO CONNECT
Figure 38. Error Budget Analysis Example 1: VIN = 10 V Full-Scale,
VCM = 200 V DC, RSHUNT = 1 Ω, 1 V p-p, 60 Hz Power-Line Interference
+V
S
AD629
REF (–)
21.1kΩ
NC
1
2
3
4
8
7
6
5
THERMOCOUPLE
380kΩ 380kΩ
–IN
+IN
+V
0.1µF
S
380kΩ
V
OUT
V
REF
20kΩ
REF (+)
NC = NO CONNECT
Figure 37. A Gain of 19 Thermocouple Amplifier
Table 5. AD629 vs. INA117 Error Budget Analysis Example 1 (VCM = 200 V dc)
Error, ppm of FS
Error Source
AD629
INA117
AD629
INA117
ACCURACY, TA = 25°C
Initial Gain Error
(ꢀ.ꢀꢀꢀ5 × 1ꢀ)/1ꢀ V × 1ꢀ6
(ꢀ.ꢀꢀ1 V/1ꢀ V) × 1ꢀ6
(224 × 1ꢀ-6 × 2ꢀꢀ V)/1ꢀ V × 1ꢀ6
(ꢀ.ꢀꢀꢀ5 × 1ꢀ)/1ꢀ V × 1ꢀ6
(ꢀ.ꢀꢀ2 V/1ꢀ V) × 1ꢀ6
5ꢀꢀ
1ꢀꢀ
448ꢀ
5ꢀ8ꢀ
5ꢀꢀ
2ꢀꢀ
1ꢀ,ꢀꢀꢀ
1ꢀ,7ꢀꢀ
Offset Voltage
DC CMR (Over Temperature)
(5ꢀꢀ × 1ꢀ-6 × 2ꢀꢀ V)/1ꢀ V × 1ꢀ6
Total Accuracy Error
TEMPERATURE DRIFT (85°C)
Gain
1ꢀ ppm/°C × 6ꢀ°C
(2ꢀ μV/°C × 6ꢀ°C) × 1ꢀ6/1ꢀ V
1ꢀ ppm/°C × 6ꢀ°C
6ꢀꢀ
12ꢀ
72ꢀ
6ꢀꢀ
24ꢀ
84ꢀ
Offset Voltage
(4ꢀ μV/°C × 6ꢀ°C) × 1ꢀ6/1ꢀ V
Total Drift Error
RESOLUTION
Noise, Typical, ꢀ.ꢀ1 Hz to 1ꢀ Hz, μV p-p
CMR, 6ꢀ Hz
Nonlinearity
15 μV/1ꢀ V × 1ꢀ6
(141 × 1ꢀ-6 × 1 V)/1ꢀ V × 1ꢀ6
(1ꢀ-5 × 1ꢀ V)/1ꢀ V × 1ꢀ6
25 μV/1ꢀ V × 1ꢀ6
2
3
(5ꢀꢀ × 1ꢀ-6 × 1 V)/1ꢀ V × 1ꢀ6
(1ꢀ-5 × 1ꢀ V)/1ꢀ V × 1ꢀ6
Total Resolution Error
Total Error
14
5ꢀ
1ꢀ
1ꢀ
26
63
5826
11,6ꢀ3
Rev. B | Page 12 of 16
AD629
ERROR BUDGET ANALYSIS EXAMPLE 2
OUTPUT
This application is similar to the previous example except
that the sensed load current is from an amplifier with an ac
common-mode component of ±177 ꢁ (frequency = ±77 Hz)
present on the shunt (see Figure 39). All other conditions are
the same as before. Note that the same kind of power-line
interference can happen as detailed in Example 1. However,
the ac common-mode component of 277 ꢁ p-p coming from
the shunt is much larger than the interference of 1 ꢁ p-p;
therefore, this interference component can be neglected.
CURRENT
AD629
REF (–)
21.1kΩ
10 AMPS
±100V AC CM
TO GROUND
NC
1
2
3
4
8
7
6
5
380kΩ 380kΩ
–IN
+IN
+V
S
0.1µF
1Ω
SHUNT
380kΩ
V
OUT
20kΩ
REF (+)
–V
S
60Hz
0.1µF
POWER LINE
NC = NO CONNECT
Figure 39. Error Budget Analysis Example 2: VIN = 10 V Full-Scale,
VCM 100 V at 500 Hz, RSHUNT =1 Ω
=
Table 6. AD629 vs. INA117 AC Error Budget Example 2 (VCM
=
100 V @ 500 Hz)
INA117
Error, ppm of FS
Error Source
AD629
AD629
INA117
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
(ꢀ.ꢀꢀꢀ5 × 1ꢀ)/1ꢀ V × 1ꢀ6
(ꢀ.ꢀꢀ1 V/1ꢀ V) × 1ꢀ6
(ꢀ.ꢀꢀꢀ5 × 1ꢀ)/1ꢀ V × 1ꢀ6
(ꢀ.ꢀꢀ2 V/1ꢀ V) × 1ꢀ6
5ꢀꢀ
1ꢀꢀ
6ꢀꢀ
5ꢀꢀ
2ꢀꢀ
7ꢀꢀ
Total Accuracy Error
TEMPERATURE DRIFT (85°C)
Gain
1ꢀ ppm/°C × 6ꢀ°C
(2ꢀ μV/°C × 6ꢀ°C) × 1ꢀ6/1ꢀ V
1ꢀ ppm/°C × 6ꢀ°C
6ꢀꢀ
12ꢀ
72ꢀ
6ꢀꢀ
24ꢀ
84ꢀ
Offset Voltage
(4ꢀ μV/°C × 6ꢀ°C) × 1ꢀ6/1ꢀ V
Total Drift Error
RESOLUTION
Noise, Typical, ꢀ.ꢀ1 Hz to 1ꢀ Hz, μV p-p
CMR, 6ꢀ Hz
Nonlinearity
15 μV/1ꢀ V × 1ꢀ6
25 μV/1ꢀ V × 1ꢀ6
2
3
(141 × 1ꢀ-6 × 1 V)/1ꢀ V × 1ꢀ6
(1ꢀ-5 × 1ꢀ V)/1ꢀ V × 1ꢀ6
(141 × 1ꢀ-6 × 2ꢀꢀ V)/1ꢀ V × 1ꢀ6
(5ꢀꢀ × 1ꢀ-6 × 1 V)/1ꢀ V × 1ꢀ6
(1ꢀ-5 × 1ꢀ V)/1ꢀ V × 1ꢀ6
(5ꢀꢀ × 1ꢀ-6 × 2ꢀꢀ V)/1ꢀ V × 1ꢀ6
Total Resolution Error
Total Error
14
5ꢀ
1ꢀ
1ꢀ
AC CMR @ 5ꢀꢀ Hz
282ꢀ
2846
4166
1ꢀ,ꢀꢀꢀ
1ꢀ,ꢀ63
11,6ꢀ3
Rev. B | Page 13 of 16
AD629
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 40. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
⋅
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 41. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 14 of 16
AD629
ORDERING GUIDE
Model
Temperature Range
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
Package Description
Package Option
AD629AN
AD629ANZ1
AD629AR
AD629AR-REEL
AD629AR-REEL7
AD629ARZ1
AD629ARZ-RL1
AD629ARZ-R71
AD629BN
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,5ꢀꢀ pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,ꢀꢀꢀ pieces
8-Lead PDIP
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
AD629BNZ1
AD629BR
8-Lead PDIP
8-Lead SOIC_N
AD629BR-REEL
AD629BR-REEL7
AD629BRZ1
AD629BRZ-RL1
AD629BRZ-R71
AD629-EVAL
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,5ꢀꢀ pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,ꢀꢀꢀ pieces
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,5ꢀꢀ pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,ꢀꢀꢀ pieces
Evaluation Board
1 Z = RoHS compliant part.
Rev. B | Page 15 of 16
AD629
NOTES
©1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00783-0-2/07(B)
Rev. B | Page 16 of 16
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