AD5551BR [ADI]
5 V, Serial-Input Voltage-Output, 14-Bit DACs; 5 V ，串行输入电压输出， 14位DAC
| 型号： | AD5551BR |
| 厂家： | 
ADI |
| 描述： | 5 V, Serial-Input Voltage-Output, 14-Bit DACs |
| 文件： | 总12页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V, Serial-Input
Voltage-Output, 14-Bit DACs
a
AD5551/AD5552
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Full 14-Bit Performance
5 V Single Supply Operation
Low Power
V
DD
AD5551
Fast Settling Time
V
14-BIT DAC
Unbuffered Voltage Output Capable of Driving 60 k⍀
Loads Directly
V
REF
OUT
SPI™/QSPI™/MICROWIRE™-Compatible Interface
Standards
AGND
14-BIT DATA LATCH
CS
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
DIN
CONTROL
LOGIC
SCLK
SERIAL INPUT REGISTER
DGND
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
V
DD
R
FB
AD5552
RFB
INV
R
INV
V
REFF
14-BIT DAC
V
OUT
V
REFS
GENERAL DESCRIPTION
The AD5551 and AD5552 are single, 14-bit, serial input, voltage
output DACs that operate from a single 5 V 10% supply.
AGNDF
AGNDS
CS
14-BIT DATA LATCH
LDAC
CONTROL
LOGIC
SCLK
The AD5551 and AD5552 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
SERIAL INPUT REGISTER
DGND
DIN
These DACs provide 14-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
With an external op amp the AD5552 can be operated in bipo-
The AD5551 and AD5552 are fully specified and guaranteed
for a single 5 V 10% supply.
lar mode generating a
VREF output swing. The AD5552 also
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity. For higher precision
applications, please refer to 16-bit DACs AD5541, AD5542,
and AD5544.
2. Low Power Consumption.
Typically 1.5 mW with a 5 V supply.
3. 3-Wire Serial Interface.
The AD5551 and AD5552 are available in an SO package.
4. Unbuffered output capable of driving 60 kΩ loads, which
reduces power consumption as there is no internal buffer
to drive.
5. Power-On Reset Circuitry.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = 5 V ؎ 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications
TA = TMIN to TMAX, unless otherwise noted.)
AD5551/AD5552–SPECIFICATIONS
Parameter
Min Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
14
Bits
Relative Accuracy, INL
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Zero Code Error
0.15
0.15
–1.75 –0.3
0.1
0.1
1.0
0.8
0
LSB
LSB
LSB
ppm/°C
LSB
B Grade
Guaranteed Monotonic
0
0.5
Zero Code Temperature Coefficient
AD5552
Bipolar Resistor Matching
0.05
ppm/°C
1.000
0.0015
Ω/Ω
%
RFB/RINV, Typically RFB = RINV = 28 kΩ
Ratio Error
0.0152
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
0.25
0.2
2.5
LSB
ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range
0
VREF – 1 LSB
VREF – 1 LSB
V
V
µs
Unipolar Operation
–VREF
AD5552 Bipolar Operation
to 1/2 LSB of FS, CL = 10 pF
CL = 10 pF, Measured from 0% to 63%
1 LSB Change Around the Major Carry
All 1s Loaded to DAC, VREF = 2.5 V
Tolerance Typically 20%
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Power Supply Rejection Ratio
1
25
10
10
V/µs
nV-s
nV-s
kΩ
6.25
1.0
LSB
∆VDD 10%
DAC REFERENCE INPUT
Reference Input Range
2.0
9
7.5
VDD
V
kΩ
kΩ
Reference Input Resistance2
Unipolar Operation
AD5552, Bipolar Operation
LOGIC INPUTS
Input Current
1
0.8
µA
V
V
INL, Input Low Voltage
VINH, Input High Voltage
2.4
V
pF
V
Input Capacitance3
10
Hysteresis Voltage3
0.4
REFERENCE
Reference –3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
1.3
1
92
75
120
MHz
mV p-p
dB
pF
pF
All 1s Loaded
All 0s Loaded, VREF = 1 V p-p at 100 kHz
Code 0000H
Code 3FFFH
POWER REQUIREMENTS
VDD
IDD
4.50
5.50
1.1
6.05
V
mA
mW
0.3
1.5
Power Dissipation
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Reference input resistance is code-dependent, minimum at 2555H.
3Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–2–
AD5551/AD5552
(VDD = 5 V ؎ 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
TIMING CHARACTERISTICS1, 2 otherwise noted.)
Limit at TMIN, TMAX
All Versions
Parameter
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
25
40
20
20
15
15
35
20
15
0
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold Time
SCLK High to CS High Hold Time
Data Setup Time
Data Hold Time
LDAC Pulsewidth
t9
t10
t11
t12
30
30
30
CS High to LDAC Low Setup
CS High Time Between Active Periods
NOTES
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
Specifications subject to change without notice.
t1
SCLK
t2
t3
t6
t5
t7
t4
CS
t12
t8
t9
DB13
DB0
DIN
t11
t10
*
LDAC
*
AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 1. Timing Diagram
REV. 0
–3–
AD5551/AD5552
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Impedance θJA
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W
SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
V
OUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . 10 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C
ORDERING GUIDE
Model
INL
1 LSB
1 LSB
DNL
0.8 LSB
0.8 LSB
Temperature Range
Package Description
Package Option
AD5551BR
AD5552BR
–40°C to +85°C
–40°C to +85°C
8-Lead Small Outline IC
14-Lead Small Outline IC
SO-8
R-14
Die Size = 80 ϫ 139 = 11,120 sq mil; Number of Transistors = 1230.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5551/AD5552 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD5551 PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
VOUT
AGND
VREF
1
2
3
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry.
This is the voltage reference input for the DAC. Connect to external reference ranges from
2 V to VDD
.
CS
4
5
6
This is an active low-logic input signal. The chip select signal is used to frame the serial
data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on
the rising edge of SCLK.
SCLK
DIN
DGND
VDD
7
8
Digital Ground. Ground reference for digital circuitry.
Analog Supply Voltage, 5 V 10%.
AD5551 PIN CONFIGURATION
SOIC
AD5552 PIN CONFIGURATION
SOIC
1
2
3
4
8
7
6
5
V
1
2
3
4
5
6
7
14
13
V
V
DD
RFB
DD
OUT
DGND
DIN
AGND
AD5551
TOP VIEW
(Not to Scale)
INV
V
OUT
V
12 DGND
AGNDF
REF
AD5552
CS
SCLK
11 LDAC
AGNDS
TOP VIEW
(Not to Scale)
10
9
V
DIN
REFS
V
NC
REFF
8
CS
SCLK
NC = NO CONNECT
REV. 0
–4–
AD5551/AD5552
AD5552 PIN FUNCTION DESCRIPTIONS
Description
Mnemonic
Pin No.
RFB
VOUT
AGNDF
AGNDS
VREFS
1
2
3
4
5
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from
2 V to VDD
This is the voltage reference input (force) for the DAC. Connect to external reference ranges
from 2 V to VDD
.
VREFF
6
.
CS
7
8
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
SCLK
NC
9
No Connect.
DIN
10
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC
11
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
DGND
INV
12
13
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
VDD
14
Analog Supply Voltage, 5 V 10%.
TERMINOLOGY
Relative Accuracy
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in TPC 14.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. TPC 4 illustrates a typical DNL versus
code plot.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 13.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied by 10%.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Reference Feedthrough
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
REV. 0
–5–
AD5551/AD5552–Typical Performance Characteristics
0.5
0.25
0
0.5
0.25
0
T
V
V
= 25؇C
T
V
V
= 25؇C
A
A
= 5V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
–0.25
–0.5
–0.25
–0.5
16384
0
8192 10240 12288 14336
6144
CODE – Decimal
2048
4096
16384
0
8192 10240 12288 14336
6144
CODE – Decimal
2048
4096
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
0.5
0.5
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
0.25
0.25
0
–0.25
–0.5
0
–0.25
–0.5
–60
–20
100
140
20
60
–60
–20
100
140
20
60
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 2. Integral Nonlinearity vs. Temperature
TPC 5. Differential Nonlinearity vs. Temperature
1.0
0.5
V
T
= 5V
= 25؇C
DD
V
T
= 2.5V
= 25؇C
REF
0.75
0.5
A
A
DNL
0.25
0
DNL
0.25
0
–0.25
–0.5
INL
INL
–0.25
–0.5
–0.75
–1.0
2
3
6
7
4
5
0
2
3
5
6
1
4
SUPPLY VOLTAGE – V
REFERENCE VOLTAGE
TPC 3. Linearity Error vs. Supply Voltage
TPC 6. Linearity Error vs. Reference Voltage
REV. 0
–6–
AD5551/AD5552
1.00
0.75
0.50
0.75
0.50
0.25
0
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
0.25
0
–0.25
–0.50
–0.75
–1.00
25
75
–50
–25
0
50
100
125
150
25
75
100
125
–50
–25
0
50
150
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 7. Gain Error vs. Temperature
TPC 10. Zero-Code Error vs. Temperature
250
450
V
V
V
= 5V
DD
LOGIC
T
= 25؇C
A
= 5V
= 2.5V
400
350
REF
REFERENCE
VOLTAGE
DD
SUPPLY
200
300
250
200
150
VOLTAGE
V
= 5V
V
= 2.5V
REF
150
–40
0
1
2
3
4
5
6
–20
0
20
40
60
80
100
120
VOLTAGE – V
TEMPERATURE – ؇C
TPC 8. Supply Current vs. Temperature
TPC 11. Supply Current vs. Reference Voltage or Supply
Voltage
400
350
300
250
200
150
300
T
V
V
= 25؇C
1555H
A
V
V
= 5V
2155H
DD
= 5V
DD
= 2.5V
REF
250
200
150
100
50
= 2.5V
0155H
REF
T
= 25؇C
A
BIPOLAR MODE
UNIPOLAR MODE
0
0
1
2
3
4
5
8192 10240 12288 14336 16384
CODE – Decimal
0
2048
4096
6144
DIGITAL INPUT VOLTAGE – V
TPC 9. Supply Current vs. Digital Input Voltage
TPC 12. Reference Current vs. Code
REV. 0
–7–
AD5551/AD5552
2µs/DIV
V
V
T
= 2.5V
= 5V
= 25؇C
REF
100
90
100
DD
CLOCK (5V/DIV)
A
90
CS (5V/DIV)
10pF
50pF
100pF
200pF
= 2.5V
V
(50mV/DIV)
OUT
V
V
REF
= 5V
10
10
DD
T
= 25؇C
0%
A
0%
V
(0.5V/DIV)
OUT
2s/DIV
TPC 13. Digital Feedthrough
TPC 15. Large Signal Settling Time
V
V
= 2.5V
= 5V
= 25؇C
REF
V
V
T
= 2.5V
REF
= 5V
DD
100
100
90
DD
= 25؇C
A
T
A
V
(1V/DIV)
OUT
90
CS (5V/DIV)
V
(50mV/DIV)
OUT
GAIN = –216
V
(0.1V/DIV)
OUT
10
10
0%
0%
0.5s/DIV
2µs/DIV
TPC 14. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
TPC 16. Small Signal Settling Time
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by the ref-
erence is heavily code dependent. The output voltage is dependent
on the reference voltage as shown in the following equation.
The AD5551/AD5552 are single, 14-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5 V and consume typically 300 A with a supply of
5 V. Data is written to these devices in a 14-bit word format, via
a 3- or 4-wire serial interface. To ensure a known power-up state,
these parts were designed with a power-on reset function. In uni-
polar mode, the output is reset to 0 V, while in bipolar mode, the
AD5552 output is set to –VREF. Kelvin sense connections for
the reference and analog ground are included on the AD5552.
VREF × D
VOUT
=
2N
where D is the decimal data word loaded to the DAC register
and N is the resolution of the DAC. For a reference of 2.5 V,
the equation simplifies to the following.
Digital-to-Analog Section
2.5 × D
16,384
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 2. The DAC
architecture of the AD5551/AD5552 is segmented. The four
MSBs of the 14-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or VREF. The remaining 10 bits of the
data word drive switches S0 to S9 of a 10-bit voltage mode
R-2R ladder network.
VOUT
=
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with
full-scale loaded to the DAC.
The LSB size is VREF/16,384.
Serial Interface
The AD5551 and AD5552 are controlled by a versatile 3-wire
serial interface, which operates at clock rates up to 25 MHz and
is compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 1. Input
data is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 14-bit words. After 14 data bits
have been loaded into the serial input register, a low-to-high
transition on CS transfers the contents of the shift register to the
DAC. Data can only be loaded to the part while CS is low.
R
R
V
OUT
2R
2R
S0
2R
S1
2R
S9
2R
E1
2R
E2
2R
E15
V
REF
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
10-BIT R-2R LADDER
Figure 2. DAC Architecture
REV. 0
–8–
AD5551/AD5552
The AD5552 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC may be tied permanently
low to update the DAC synchronously. With LDAC tied perma-
nently low, the rising edge of CS will load the data to the DAC.
2.5V
10F
5V
0.1F
0.1F
RFB
+5V
SERIAL
V
V
V
DD
REFF
REFS
INTERFACE
R
FB
INV
OUT
CS
Unipolar Output Operation
R
DIN
INV
BIPOLAR
OUTPUT
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low-supply current, typically
300 µA, and a low-offset error. The AD5551 provides a unipolar
output swing ranging from 0 V to VREF. The AD5552 can be
configured to output both unipolar and bipolar voltages. Fig-
ure 3 shows a typical unipolar output voltage circuit. The code
table for this mode of operation is shown in Table I.
SCLK
LDAC
AD5551/AD5552
–5V
EXTERNAL
OP AMP
DGND AGNDF AGNDS
Figure 4. Bipolar Output (AD5552 Only)
Table II. Bipolar Code Table
5V
2.5V
DAC Latch Contents
MSB LSB
10F
Analog Output
0.1F
0.1F
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
+VREF × (8191/8192)
+VREF × (1/8192)
0 V
–VREF × (1/8192)
–VREF × (8191/8192) = –VREF
SERIAL
V
V
*
V
*
DD
REFS
REFF
INTERFACE
CS
AD820/
OP196
AD5551/AD5552
DIN
UNIPOLAR
OUTPUT
OUT
SCLK
LDAC
*
EXTERNAL
OP AMP
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
DGND
AGND
*
AD5552 ONLY
Bipolar Mode Worst-Case Output
Figure 3. Unipolar Output
Table I. Unipolar Code Table
DAC Latch Contents
VOUT–UNI +VOS 2 + RD – VREF 1 + RD
(
[
)(
)
(
)
]
VOUT–BIP
where
=
1 + 2 + RD /A
MSB LSB
Analog Output
VOS = External Op Amp Input Offset Voltage
RD = RFB and RIN Resistor Matching Error, Unitless
= Op Amp Open-Loop Gain
Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied
from a dual power supply. This will provide the REF output.
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
VREF × (16383/16384)
VREF × (8192/16384) = 1/2 VREF
A
VREF × (1/16384)
0 V
V
Assuming a perfect reference, the worst-case output voltage may
be calculated from the following equation.
In a single-supply application, selection of a suitable op amp
may be more difficult as the output swing of the amplifier does
not usually include the negative rail, in this case AGND. This
can result in some degradation of the specified performance
unless the application does not use codes near zero.
Unipolar Mode Worst-Case Output
D
214
VOUT–UNI
=
×(VREF +VGE )+VZSE + INL
where
The selected op amp needs to have very low-offset voltage, (the
DAC LSB is 152 µV with a 2.5 V reference), to eliminate the
need for output offset trims. Input bias current should also be
very low as the bias current multiplied by the DAC output
impedance (approximately 6K) will add to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain
errors, the input impedance of the output amplifier should be
as high as possible. The amplifier should also have a 3 dB band-
width of 1 MHz or greater. The amplifier adds another time
constant to the system, hence increasing the settling time of the
output. A higher 3 dB amplifier bandwidth results in a faster
effective settling time of the combined DAC and amplifier.
VOUT–UNI = Unipolar Mode Worst-Case Output
D
VREF
VGE
VZSE
INL
= Decimal Code Loaded to DAC
= Reference Voltage Applied to Part
= Gain Error in Volts
= Zero Scale Error in Volts
= Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5552 may be config-
ured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 4. The matched bipolar offset
resistors RFB and RINV are connected to an external op amp to
achieve this bipolar output swing where RFB = RINV = 28 kΩ.
Table II shows the transfer function for this output operating
mode. Also provided on the AD5552 are a set of Kelvin connec-
tions to the analog ground inputs.
REV. 0
–9–
AD5551/AD5552
Force Sense Buffer Amplifier Selection
**
LDAC
FO
These amplifiers can be single-supply or dual supplies, low-
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to 20 mA.
CS
ADSP-2101/
ADSP-2103*
AD5551/
AD5552*
TFS
DT
DIN
SCLK
SCLK
*
Reference and Ground
ADDITIONAL PINS OMITTED FOR CLARITY.
**
AD5552 ONLY
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5551/
AD5552 operates with a voltage reference ranging from 2 V to
VDD. Although DAC’s full-scale output voltage is determined
by the reference, references below 2 V will result in reduced
accuracy. Tables I and II outline the analog output voltage
for particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5552.
Figure 5. ADSP-2101/ADSP-2103 to AD5551/AD5552
Interface
68HC11 to AD5551/AD5552 Interface
Figure 6 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the SCLK of the DAC, while the MOSI output drives the
serial data lines SDIN. CS signal is driven from one of the
port lines. The 68HC11 is configured for master mode; MSTR
= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI
output is valid on the rising edge of SCK.
If the application does not require separate force and sense lines,
they should be tied together close to the package to minimize
voltage drops between the package leads and the internal die.
ADR291 and ADR293 are suitable references for this product.
Power-On Reset
**
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. On power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 14 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 14 bits are loaded,
only the last 14 are kept, and if fewer than 14 are loaded, bits
will remain from the previous word. If the AD5551/AD5552
needs to be interfaced with data shorter than 14 bits, the data
should be padded with zeros at the LSBs.
LDAC
PC6
68HC11/
68L11*
PC7
MOSI
SCK
CS
AD5551/
AD5552*
DIN
SCLK
*
**
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5552 ONLY
Figure 6. 68HC11/68L11 to AD5551/AD5552 Interface
MICROWIRE to AD5551/AD5552 Interface
Figure 7 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that
the reference and supply pins be bypassed with a 10 µF tantalum
capacitor in parallel with a 0.1 µF ceramic capacitor.
MICROPROCESSOR INTERFACING
CS
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
requires a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
CS
MICROWIRE*
SO
DIN
AD5551/
AD5552*
SCLK
SCLK
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 7. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 to AD5551/AD5552 Interface
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 8. TxD of the
microcontroller drives the SCLK of the AD5551/AD5552, while
RxD drives the serial data line of the DAC. P3.3 is a bit program-
mable pin on the serial port which is used to drive CS.
ADSP-2101/ADSP-2103 to AD5551/AD5552 Interface
Figure 5 shows a serial interface between the AD5551/AD5552
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set to operate in the SPORT (Serial Port) transmit
alternate framing mode. The ADSP-2101/ADSP-2103 is pro-
grammed through the SPORT control register and should be
configured as follows: Internal Clock Operation, Active Low
Framing, 16-Bit Word Length. The first 2 bits are DON’T CARE
as AD5551/AD5552 will keep the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT has
been enabled. Because of the edges-triggered difference, an inverter
is required at the SCLKs between the DSP and the DAC.
**
P3.4
P3.3
LDAC
CS
80C51/
80L51*
AD5551/
AD5552*
RxD
TxD
DIN
SCLK
*
**
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5552 ONLY
Figure 8. 80C51/80L51 to AD5551/AD5552 Interface
REV. 0
–10–
AD5551/AD5552
Decoding Multiple AD5551/AD5552s
The 80C51/80L51 provides the LSB first, while the AD5551/
AD5552 expects the MSB of the 14-bit word first. Care should be
taken to ensure the transmit routine takes this into account.
Usually it can be done through software by shifting out and accu-
mulating the bits in the correct order before inputting to the DAC.
Also, 80C51 outputs 2 byte words/16 bits data, thus the first two
bits, after rearrangement, should be DON’T CARE as they will
be dropped from the DAC’s 14-bit word.
The CS pin of the AD5551/AD5552 can be used to select one
of a number of DACs. All devices receive the same serial clock
and serial data, but only one device will receive the CS signal at
any one time. The DAC addressed will be determined by the
decoder. There will be some digital feedthrough from the digital
input lines. Using a burst clock will minimize the effects of digi-
tal feedthrough on the analog signal channels. Figure 10 shows a
typical circuit.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register on
the rising edge of the serial clock. The 80C51/80L51 transmits
its data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. As the DAC requires a 14-bit word,
P3.3 (or any one of the other programmable bits) is the CS input
signal to the DAC, so P3.3 should be brought low at the begin-
ning of the 16-bit write cycle 2 × 8 bit words and held low until
the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought
high again and the new data loads to the DAC. Again, the first
two bits, after rearranging, should be DON’T CARE. LDAC
on the AD5552 may also be controlled by the 80C51/80L51 serial
port output by using another bit programmable pin, P3.4.
AD5551/AD5552
SCLK
CS
V
OUT
DIN
DIN
V
DD
SCLK
AD5551/AD5552
ENABLE
EN
CS
CODED
ADDRESS
V
DECODER
DGND
OUT
DIN
SCLK
AD5551/AD5552
CS
V
OUT
APPLICATIONS
DIN
Optocoupler interface
SCLK
The digital inputs of the AD5551/AD5552 are Schmitt-
triggered, so they can accept slow transitions on the digital input
lines. This makes these parts ideal for industrial applications
where it may be necessary that the DAC is isolated from the
controller via optocouplers. Figure 9 illustrates such an interface.
AD5551/AD5552
CS
V
OUT
DIN
SCLK
Figure 10. Addressing Multiple AD5551/AD5552s
5V
REGULATOR
0.1F
10F
POWER
V
DD
10k⍀
V
DD
SCLK
SCLK
V
DD
AD5551/AD5552
V
10k⍀
CS
CS
OUT
V
DD
10k⍀
DIN
DIN
GND
Figure 9. AD5551/AD5552 in an Optocoupler Interface
REV. 0
–11–
AD5551/AD5552
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SO
(SO-8)
14-Lead SO
(R-14)
0.3444 (8.75)
0.3367 (8.55)
0.1968 (5.00)
0.1890 (4.80)
8
7
8
1
5
4
14
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
1
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ ؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
8؇
0؇
8؇
0؇
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
REV. 0
–12–
相关型号：
AD5552BR-REEL7
IC SERIAL INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDSO14, SOIC-14, Digital to Analog Converter
ADI
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