AD5553CRM [ADI]
Current Output/ Serial Input, 16-/14-Bit DAC; 电流输出/串行输入， 16位/ 14位DAC
| 型号： | AD5553CRM |
| 厂家： | 
ADI |
| 描述： | Current Output/ Serial Input, 16-/14-Bit DAC |
| 文件： | 总12页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Current Output/
a
Serial Input, 16-/14-Bit DAC
AD5543/AD5553
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16-Bit Resolution AD5543
14-Bit Resolution AD5553
ꢀ1 LSB DNL
AD5543/AD5553
R
FB
V
ꢀ2 LSB INL for AD5543
DD
ꢀ1 LSB INL for AD5553
Low Noise 12 nV/√Hz
Low Power, IDD = 10 ꢁA
D/A
CONVERTER
I
V
OUT
REF
16 OR 14
0.5 ꢁs Settling Time
4Q Multiplying Reference-Input
2 mA Full-Scale Current ꢀ 20%, with VREF = 10 V
Built-in RFB Facilitates Voltage Conversion
3-Wire Interface
CONTROL
LOGIC
DAC
REGISTER
CS
16 OR 14
CLK
SDI
GND
Ultracompact MSOP-8 and SOIC-8 Packages
16-/14-BIT SHIFT
REGISTER
APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
1.0
0.8
0.6
GENERAL DESCRIPTION
0.4
The AD5543/AD5553 are precision 16-/14-bit, low power,
current output, small form factor digital-to-analog converters.
They are designed to operate from a single 5 V supply with a
10 V multiplying reference.
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
The applied external reference VREF determines the full-scale
output current. An internal feedback resistor (RFB) facilitates the
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.
A serial-data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS).
CODE
Figure 1. Integral Nonlinearity Error
The AD5543/AD5553 are packaged in ultracompact
(3 mm ꢀ 4.7 mm) MSOP-8 and SOIC-8 packages.
REF LEVEL /DIV
0.000dB 12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
FFFFH
8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H
0000H
10
100
1k
10k
100k
1M
10M
REV. A
START 10.000Hz
STOP 50 000 000.000Hz
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Figure 2. Reference Multiplying Bandwidth
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5543/AD5553–SPECIFICATIONS
(@ VDD = 5 V ꢀ 10%, VSS = 0 V, IOUT = Virtual GND, GND = 0 V, VREF = 10 V,
TA = Full operating temperature range, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
5 V ꢀ 10% Unit
STATIC PERFORMANCE1
Resolution
N
1 LSB = VREF/216 = 153 µV when VREF = 10 V AD5543 16
1 LSB = VREF/214 = 610 µV when VREF = 10 V AD5553 14
Bits
Bits
Relative Accuracy
INL
Grade: AD5553C
Grade: AD5543B
Monotonic
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA max
Data = FFFFH
1
2
LSB max
LSB max
LSB max
nA max
nA max
mV typ/max
ppm/°C typ
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
1
10
20
Full-Scale Gain Error
Full-Scale Tempco2
GFSE
TCVFS
1/ 4
1
REFERENCE INPUT
VREF Range
VREF
RREF
CREF
–15/+15
5
5
V min/max
kΩ typ3
pF typ
Input Resistance
Input Capacitance2
ANALOG OUTPUT
Output Current
IOUT
Data = FFFFH for AD5543
Data = 3FFFH for AD5553
Code Dependent
2
mA typ
pF typ
Output Capacitance2
COUT
200
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
VIL
VIH
IIL
0.8
2.4
10
V max
V min
µA max
pF max
CIL
10
INTERFACE TIMING 2, 4
Clock Input Frequency
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Data Setup
fCLK
tCH
tCL
tCSS
tCSH
tDS
50
10
10
0
10
5
MHz
ns min
ns min
ns min
ns min
ns min
ns min
Data Hold
tDH
10
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
VDD RANGE
IDD
PDISS
PSS
4.5/5.5
10
0.055
0.006
V min/max
µA max
mW max
%/% max
Logic Inputs = 0 V
Logic Inputs = 0 V
∆VDD = 5%
Power Supply Sensitivity
AC CHARACTERISTICS4
Output Voltage Settling Time
tS
To 0.1% of Full Scale,
0.5
µs typ
Data = 0000H to FFFFH to 0000H for AD5543
Data = 0000H to 3FFFH to 0000H for AD5553
VREF = 5 V p-p, Data = FFFFH
VREF = 0 V, Data = 7FFFH to 8000H for AD5543
Data = 1FFFH to 2000H for AD5553
Reference Multiplying BW
DAC Glitch Impulse
BW
Q
4
7
MHz typ
nV-s typ
Feedthrough Error
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
VOUT/VREF Data = 0000H, VREF = 100 mV rms, same channel
–65
7
–85
12
dB
Q
CS = 1, and fCLK = 1 MHz
REF = 5 V p-p, Data = FFFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
nV-s typ
dB typ
nV/√Hz
THD
eN
V
NOTES
1All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal
is tied to the amplifier output. The op amp +IN is grounded and the DAC IOUT is tied to the op amp –IN. Typical values represent average readings measured at 25°C.
2These parameters are guaranteed by design and are not subject to production testing.
3All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier.
4All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
–2–
REV. A
AD5543/AD5553
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V(IOUT) to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Input Current to Any Pin except Supplies . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ Max – TA )/ꢁJA
Thermal Resistance ꢁJA
8-Lead Surface Mount (MSOP-8) . . . . . . . . . . . . . 150°C/W
8-Lead Surface Mount (SOIC-8) . . . . . . . . . . . . . . 100°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Operating Temperature Range
Models B, C . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
RN-8, RM-8 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . 215°C
RN-8, RM-8 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . 220°C
Pin
No. Mnemonic Function
1
CLK
Clock Input. Positive-edge triggered, clocks
data into shift register.
2
SDI
Serial Register Input. Data loads directly
into the shift register MSB first. Extra leading
bits are ignored.
3
4
RFB
Internal Matching Feedback Resistor. Con-
nects to external op amp for voltage output.
DAC Reference Input Pin. Establishes DAC
full-scale voltage. Constant input resistance
versus code.
VREF
5
IOUT
DAC Current Output. Connects to inverting
terminal of external precision I-to-V op amp
for voltage output.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
6
7
GND
VDD
Analog and Digital Ground
Positive Power Supply Input. Specified range
of operation 5 V 10%.
8
CS
Chip Select. Active low digital input. Transfers
shift-register data to DAC register on rising
edge. See Truth Table for operation.
PIN CONFIGURATION
MSOP and SOIC-8
AD5543/
AD5553
CLK
SDI
1
2
3
4
8
7
6
5
CS
V
DD
TOP VIEW
(Not to Scale)
R
GND
FB
I
V
OUT
REF
ORDERING GUIDE*
Temperature Package
INL
RES
Package
Model
(LSB) (LSB) Range
Description Option
Marking
AD5543BR
AD5543BRM
AD5553CRM
2
2
1
16
16
14
–40°C to +85°C SOIC-8
–40°C to +85°C MSOP-8
–40°C to +85°C MSOP-8
RN-8
RM-8
RM-8
AD5543
DXB
DUC
*The AD5543 contains 1040 transistors. The die size measures 55 mil ꢀ 73 mil, 4,015 sq. mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5543/AD5553 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
AD5543/AD5553–Typical Performance Characteristics
1.0
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2048
4096
6144
CODE – Decimal
8192 10240 12288 14336 16384
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
TPC 1. AD5543 Integral Nonlinearity Error
TPC 4. AD5553 Differential Nonlinearity Error
1.5
1.0
V
= 2.5V
= 25ꢂC
REF
0.8
0.6
T
A
1.0
0.5
0
0.4
0.2
INL
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
GE
2
4
6
8
10
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
SUPPLYVOLTAGEV –V
DD
TPC 2. AD5543 Differential Nonlinearity Error
TPC 5. Linearity Errors vs. VDD
1.0
0.8
5
4
3
2
1
0
V
= 5V
= 25ꢂC
DD
T
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2048
4096 6144
8192 10240 12288 14336 16384
0
0.5
1.0 1.5
2.0 2.5
3.0
3.5
4.0
4.5 5.0
CODE – Decimal
LOGIC INPUTVOLTAGEV –V
IH
TPC 3. AD5553 Integral Nonlinearity Error
TPC 6. Supply Current vs. Logic Input Voltage
–4–
REV. A
AD5543/AD5553
3.0
2.5
2.0
1.5
1.0
0.5
0
5555
H
8000
H
FFFF
0000
H
H
10k
100k
1M
CLOCK FREQUENCY – Hz
10M
100M
TPC 7. AD5543 Supply Current vs. Clock Frequency
TPC 10. Settling Time
90
V
= 5V ꢀ 10%
DD
80
70
60
50
40
30
20
10
0
V
= 10V
REF
CS (5V/DIV)
V
= 5V
= 10V
DD
V
REF
CODES 8000 ↔ 7FFF
H
H
V
(50mV/DIV)
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME – ꢁs
3.5
4.0
4.5 5.0
10
100
1k
10k
100k
1M
FREQUENCY – Hz
TPC 11. Midscale Transition and Digital Feedthrough
TPC 8. Power Supply Rejection vs. Frequency
REF LEVEL /DIV
0.000dB 12.000dB
MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB
FFFFH
8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H
0000H
10
100
1k
10k
100k
1M
10M
START 10.000Hz
STOP 50 000 000.000Hz
TPC 9. Reference Multiplying Bandwidth
REV. A
–5–
AD5543/AD5553
D1
D0
SDI
D15
D14
D13
D12
D11
D10
D9
D8
CLK
t
t
t
t
CL
DS
CH
DH
t
CSH
t
CSS
CS
Figure 3a. AD5543 Timing Diagram
D1
D0
SDI
D13
D12
D11
D10
D9
D8
D7
D6
CLK
t
t
t
t
CL
DS
CH
DH
t
CSH
t
CSS
CS
Figure 3b. AD5553 Timing Diagram
Table I. Control-Logic Truth Table
CLK
CS
Serial Shift Register Function
DAC Register
X
↑+
X
H
L
H
↑+
No Effect
Shift Register Data Advanced One Bit
No Effect
Latched
Latched
Latched
X
Shift Register Data Transferred to DAC Register
New Data Loaded from Serial Register
↑+ positive logic transition; X Don't Care
Table II. AD5543 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB
LSB
Bit Position
Data-Word
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
D1 D0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
Table III. AD5553 Serial Input Register Data Format; Data is Loaded in the MSB-First Format
MSB
B13
LSB
B1
Bit Position
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B0
Data-Word* D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
*A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered will be transferred to the DAC register when CS returns
to logic high.
–6–
REV. A
AD5543/AD5553
CIRCUIT OPERATION
various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the AD5543 on the amplifier’s inverting input node. The
feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. To maintain good analog perfor-
mance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or
chip capacitors in parallel with a 1 µF tantalum capacitor is recom-
mended. Due to degradation of power supply rejection ratio in
frequency, users must avoid using switching power supplies.
The AD5543/AD5553 contains a 16-/14-bit, current output,
digital-to-analog converter, a serial input register, and a DAC
register. Both converters use a 3-wire serial data interface.
D/A Converter Section
The DAC architecture uses a current steering R-2R ladder
design. Figure 4 shows the typical equivalent DAC structure.
The DAC contains a matching feedback resistor for use with an
external op amp, (see Figure 5). With RFB and IOUT terminals
connected to the op amp output and inverting node respec-
tively, a precision voltage output can be achieved as:
SERIAL DATA INTERFACE
The AD5543/AD5553 uses a 3-wire (CS, SDI, CLK) serial
data interface. New serial data is clocked into the serial input
register in a 16-bit data-word format for AD5543. The MSB is
loaded first. Table II defines the 16 data-word bits. Data is
placed on the SDI pin and clocked into the register on the positive
clock edge of CLK, subject to the data setup and hold time
VOUT = –VREF × D / 65,536 (AD5543)
VOUT = –VREF × D /16,384 (AD5553)
(1)
(2)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
requirements specified in the interface timing specifications
.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal logic to drive the DAC switches’ ON and OFF states.
Only the last 16 bits clocked into the serial register are inter-
rogated when the CS pin is strobed to transfer the serial register
data to the DAC register. Since most microcontrollers output
serial data in 8-bit bytes, two data bytes can be written to the
AD5543/AD5553. After loading the serial register, the rising edge
of CS transfers the serial register data to the DAC register;
during this strobe, the CLK should not be toggled. For the
AD5553, with 16-bit clock cycles, the two LSBs are ignored.
V
DD
R
R
R
R
V
FB
REF
2R
2R
2R
R
5kꢃ
S2
S1
I
OUT
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zener
diodes connected to ground (GND) and VDD as shown in Figure 6.
GND
V
DD
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED
DD
DIGITAL
INPUTS
Figure 4. Equivalent R-2R DAC Circuit
5kꢃ
Note that a matching switch is used in series with the internal 5 kΩ
feedback resistor. If users attempt to measure RFB, power must be
applied to VDD to achieve continuity.
DGND
V
DD
Figure 6. Equivalent ESD Protection Circuits
U1
PCB Layout and Power Supply Bypassing
V
R
FB
DD
U2
It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
I
V
V
REF
OUT
REF
V
V+
O
AD8628
V–
GND
It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device should
be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capaci-
tors. Low-ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize transient
disturbance and filter out low frequency ripple
AD5543/AD5553
–5V
Figure 5. Voltage Output Configuration
These DACs are also designed to accommodate ac reference
input signals. The AD5543 accommodates input reference
voltages in the range of –12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input resistance value of 5 kΩ,
30%. The DAC output (IOUT) is code-dependent, producing
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
REV. A
–7–
AD5543/AD5553
APPLICATIONS
Stability
Bipolar Output
The AD5543/AD5553 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
V
DD
U1
C1
R
V
FB
DD
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier
U4 configured as a summing amplifier (see Figure 9). In this
circuit, the second amplifier U4 provides a gain of 2 that increases
the output span magnitude to 5 V. Biasing the external amplifier
with a 2.5 V offset from the reference voltage results in a full
4-quadrant multiplying circuit. The transfer equation of this circuit
shows that both negative and positive output voltages are created
I
V
V
OUT
REF
REF
V
O
AD8628
GND
U2
AD5543/AD5553
Figure 7. Optional Compensation Capacitor for Gain
Peaking Prevention
as the input data (D) is incremented from code zero (VOUT
–2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V).
=
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout technique must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node.
VOUT = (D / 32,768 – 1) × VREF (AD5543)
VOUT = (D /16,384 – 1) × VREF (AD5553)
(3)
(4)
For AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.
An optional compensation capacitor C1 can be added for stability
as shown in Figure 7. C1 should be found empirically but 20 pF
is generally adequate for the compensation.
R1
R2
10kꢃꢀ0.01% 10kꢃꢀ0.01%
Positive Voltage Output
C2
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resistor’s
tolerance errors. To generate a negative reference, the reference
can be level-shifted by an op amp such that the VOUT and GND
pins of the reference become the virtual ground and –2.5 V
respectively, (see Figure 8).
U4
+5V
+5V
U1
5kꢃꢀ0.01%
V
O
V+
R3
ADR03
1/2AD8620
V–
C1
V
R
FB
DD
I
V
V
V
OUT
+5V
IN
REF
OUT
–5V
1/2AD8620
GND
U3
GND
–2.5 < V < +2.5
O
+5V
U2
AD5553 ONLY
ADR03
Figure 9. Four-Quadrant Multiplying Application Circuit
V
V
IN
OUT
U4
+5V
U1
V
GND
U3
–2.5V
C1
V
R
FB
DD
V+
I
1/2AD8620
OUT
REF
V
O
V–
1/2AD8628
GND
–5V
U2
0 < V < +2.5
AD5543/AD5553
O
Figure 8. Positive Voltage Output Configuration
–8–
REV. A
AD5543/AD5553
Programmable Current Source
If the resistors are perfectly matched, ZO is infinite, which is
desirable, and behaves as an ideal current source. On the other
hand, if they are not matched, ZO can be either positive or nega-
tive. Negative can cause oscillation. As a result, C1 is needed to
prevent the oscillation. For critical applications, C1 could be
found empirically, but typically falls in the range of few pF.
Figure 10 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. This circuit
can be used in 4 to 20 mA current transmitters with up to 500 Ω
of load. In Figure 10, it can be shown that if the resistor network is
matched, the load current is:
V
DD
U1
R2 + R3 / R1
(
)
V
R
FB
IL
=
×VREF × D
(5)
DD
R3
I
R1'
R2'
V
V
REF
OUT
REF
150kꢃ 15kꢃ
R3 in theory can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that AD8510 can deliver 20 mA in both direc-
tions and the voltage compliance approaches 15 V, which is
limited mainly by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes:
AD8628
GND
C1
10pF
AD5543/AD5553
U2
V
DD
R3'
50ꢃ
U3
V+
AD8510
V–
R3
50ꢃ
R1'R3 R1+ R2
(
)
ZO
=
(6)
V
SS
R1 R2'+R3' – R1' R2 + R3
(
)
(
)
V
L
R2
R1
15kꢃ
150kꢃ
I
LOAD
L
Figure 10. Programmable Current Source with Bidirec-
tional Current Control and High Voltage Compliance
Capabilities
REV. A
–9–
AD5543/AD5553
OUTLINE DIMENSIONS
8-Lead microSOIC Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.40
8ꢂ
0ꢂ
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢄ 45ꢂ
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8ꢂ
0.51 (0.0201)
0.33 (0.0130)
0ꢂ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–10–
REV. A
AD5543/AD5553
Revision History
Location
Page
2/03—Data Sheet changed from REV. 0 to REV. A.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. A
–11–
–12–
相关型号：
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