AD5554 [ADI]
Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs; 四，电流输出串行输入， 16位/ 14位DAC
| 型号： | AD5554 |
| 厂家： | 
ADI |
| 描述： | Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs |
| 文件： | 总16页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Current-Output
Serial-Input, 16-Bit/14-Bit DACs
a
AD5544/AD5554
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AD5544 16-Bit Resolution
AD5554 14-Bit Resolution
2 mA Full-Scale Current ꢀ20%, with VREF = ꢀ10 V
2 ꢁs Settling Time
VSS BIAS for Zero-Scale Error Reduction @ Temp
Midscale or Zero-Scale Reset
Four Separate 4Q Multiplying Reference Inputs
SPI-Compatible 3-Wire Interface
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power ON Reset
V
A B C D
DAC A
REF
V
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
R
FB
A
SDO
INPUT
REGISTER
DAC A
REGISTER
I A
OUT
R
R
R
R
R
R
R
R
A
R
A
GND
B
FB
INPUT
REGISTER
DAC B
REGISTER
16
D9
DAC B
DAC C
I B
OUT
D10
D11
D12
D13
D14
D15
A0
A B
GND
R
I
C
C
FB
INPUT
REGISTER
DAC C
REGISTER
Compact SSOP-28 Package
OUT
SDI
A1
A C
GND
APPLICATIONS
Automatic Test Equipment
Instrumentation
CS
R
I
D
FB
CLK
EN
INPUT
REGISTER
DAC D
REGISTER
D
OUT
DAC D
DAC
A
Digitally-Controlled Calibration
B
C
D
A D
GND
2:4
POWER-
ON
AD5544
DECODE
A
GND
F
RESET
DGND
RS
MSB
LDAC
V
SS
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital-
to-analog converters are designed to operate from a single 5 V
supply.
1.0
0.5
0.0
DAC A
DAC B
DAC C
DAC D
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
)
–0.5
–1.0
1.0
0.5
0.0
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI- and microcontroller-compatible inputs using
serial-data-in (SDI), clock (CLK), and a chip-select (CS). In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common level-sensitive
load-DAC strobe (LDAC) input allows simultaneous update of
all DAC outputs from previously loaded input registers. Addi-
tionally, an internal power ON reset forces the output voltage to
zero at system turn ON. An MSB pin allows system reset asser-
tion (RS) to force all registers to zero code when MSB = 0, or
to half-scale code when MSB = 1.
–0.5
–1.0
1.0
0.5
0.0
–0.5
–1.0
1.0
0.5
0.0
AD5544/AD5554 are packaged in the compact SSOP-28.
–0.5
–1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
Figure 1. AD5544 INL vs. Code Plot (TA = 25°C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ VDD = 5 V ꢀ 10%, VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = Full Operating Temperature Range,
unless otherwise noted.)
AD5544/AD5554–SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
N
INL
DNL
1 LSB = VREF/216 = 153 µV when VREF = 10 V
16
4
1.5
10
20
3
Bits
LSB
LSB
nA
nA
mV
IOUT
X
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = FFFFH
I
OUTX
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
GFSE
TCVFS
RFB
0.75
1
6
ppm/°C
kΩ
X
VDD = 5 V
4
8
REFERENCE INPUT
VREFX Range
Input Resistance
VREF
REFX
RREF
CREF
X
–15
4
+15
8
V
kΩ
%
R
6
1
5
Input Resistance Match
X
X
Channel-to-Channel
Input Capacitance2
pF
ANALOG OUTPUT
Output Current
I
OUTX
Data = FFFFH
Code-Dependent
1.25
2.5
0.8
mA
pF
Output Capacitance2
COUT
X
80
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
2.4
4
1
10
0.4
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
IOL = 1.6 mA
IOH = 100 µA
V
INTERFACE TIMING2, 3
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulsewidth
Data Setup
tCH
tCL
25
25
0
25
2
25
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
20
Data Hold
Load Setup
Load Hold
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
VDD RANGE
IDD
ISS
PDISS
PSS
4.5
5.5
250
1
1.25
0.006 %/%
V
Logic Inputs = 0 V
Logic Inputs = 0 V, VSS = –5 V
Logic Inputs = 0 V
50
0.001
µA
µA
mW
Power Supply Sensitivity
∆VDD
=
5%
NOTES
1All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2These parameters are guaranteed by design and not subject to production testing.
3All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
–2–
REV. 0
AD5544/AD5554
(@ VDD = 5 V ꢀ 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.)
AD5544 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min Typ Max Unit
AC CHARACTERISTICS1
Output Voltage Settling Time tS
To 0.1% of Full Scale, Data = 0000H
to FFFFH to 0000H
To 0.0015% of Full Scale, Data = 0000H
to FFFFH to 0000H
1
2
2
µs
Output Voltage Settling Time tS
µs
Reference Multiplying BW
BW –3 dB
VREFX = 100 mV rms, Data = FFFFH,
MHz
C
FB = 15 pF
REFX = 10 V, Data 0000H to 8000H to 0000H
VOUTX/VREFX Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
Q
V
1.2
–65
–90
nV-s
dB
dB
V
OUTA/VREF
B
Data = 0000H, VREFB = 100 mV rms,
Adjacent Channel, f = 100 kHz
CS = 1, and fCLK = 1 MHz
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
Q
5
–90
7
nV-s
dB
nV/√Hz
THD
eN
V
REF = 5 V p-p, Data = FFFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
NOTES
1All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
Specifications subject to change without notice.
–3–
REV. 0
(@ VDD = 5 V ꢀ 10%, VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range,
unless otherwise noted.)
AD5544/AD5554–SPECIFICATIONS
AD5554 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
N
INL
DNL
IOUT
IOUT
GFSE
TCVFS
RFB
1 LSB = VREF/214 = 610 µV when VREF = 10 V
14
1
1
10
20
10
Bits
LSB
LSB
nA
nA
mV
X
X
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = 3FFFH
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
2
1
6
ppm/°C
kΩ
X
VDD = 5 V
4
8
REFERENCE INPUT
VREFX Range
Input Resistance
VREF
RREF
RREF
X
X
X
–15
4
+15
8
V
kΩ
%
6
1
5
Input Resistance Match
Channel-to-Channel
Input Capacitance2
CREF
X
pF
ANALOG OUTPUT
Output Current
IOUT
COUT
X
X
Data = 3FFFH
Code-Dependent
1.25
2.5
0.8
mA
pF
Output Capacitance2
80
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
2.4
4
1
10
0.4
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
IOL = 1.6 mA
IOH = 100 µA
V
INTERFACE TIMING 2, 3
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulsewidth
Data Setup
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
25
25
0
25
2
25
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
Data Hold
Load Setup
Load Hold
tLDH
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
VDD RANGE
IDD
ISS
PDISS
PSS
4.5
5.5
250
1
1.25
0.006 %/%
V
Logic Inputs = 0 V
Logic Inputs = 0 V, VSS = –5 V
Logic Inputs = 0 V
50
0.001
µA
µA
mW
Power Supply Sensitivity
∆VDD
=
5%
NOTES:
1All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2These parameters are guaranteed by design and not subject to production testing.
3All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
–4–
REV. 0
AD5544/AD5554
(@ VDD = 5 V ꢀ 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V, VREFA,
B, C, D = 10 V, TA = full operating temperature range, unless otherwise
noted.)
AD5554 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min Typ Max Unit
AC CHARACTERISTICS1
Output Voltage Settling Time tS
To 0.1% of Full Scale, Data = 0000H
to 3FFFH to 0000H
To 0.0015% of Full Scale, Data = 0000H
1
2
µs
µs
Output Voltage Settling Time tS
to 3FFFH to 0000H
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
BW –3 dB
VREFX = 100 mV rms, Data = 3FFFH, CFB = 15 pF
2
1.2
–65
MHz
nV-s
dB
Q
V
REFX = 10 V, Data 0000H to 2000H to 0000H
VOUTX/VREFX Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
VOUTA/VREF
B
Data = 0000H, VREFB = 100 mV rms,
Adjacent Channel, f = 100 kHz
CS = 1, and fCLK = 1 MHz
VREF = 5 V p-p, Data = 3FFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
–90
5
–90
7
dB
nV-s
dB
Digital Feedthrough
Total Harmonic Distortion
Output Spot Noise Voltage
Q
THD
eN
nV/√Hz
NOTES:
1All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
Operating Temperature Range
Model A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature:
V
V
SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
REF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V
Logic Inputs and Output to GND . . . . . . . . . . . . –0.3 V, +8 V
V(IOUT) to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
RS-28 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RS-28 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . . . 220°C
A
GNDX to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 0.3 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Input Current to Any Pin Except Supplies . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA
28-Lead Shrink Surface-Mount (RS-28) . . . . . . . . 100°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C
ORDERING GUIDE
RES INL
Bit LSB LSB
DNL
Temperature
Range
Package
Description
Package
Option
Model
AD5544ARS 16
AD5554BRS 14
4
1
1.5
1
–40/+85°C
–40/+85°C
SSOP-28
SSOP-28
RS-28
RS-28
The AD5544/AD5554 contain 4196 transistors. The die size is 122 mil × 204 mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5544/AD5554 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–5–
REV. 0
AD5544/AD5554
SDI
A1
A0
D15 D14 D13 D12 D11 D10
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDH
LDAC
tLDAC
tPD
SDO
Figure 2. AD5544 Timing Diagram
SDI
A1
A0
D13 D12 D11 D10 D09 D08
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 3. AD5554 Timing Diagram
Table I. AD5544 Control-Logic Truth Table
CS CLK LDAC RS
MSB Serial Shift Register Function
Input Register Function DAC Register
H
L
L
L
↑+
X
L
↑+
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Shift-Register-Data Advanced One Bit Latched
No Effect
No Effect
Latched
Selected DAC Updated
with Current SR Contents
Latched
Latched
Latched
H
H
H
H
H
X
X
X
X
X
L
H
H
H
L
X
X
X
0
No Effect
No Effect
No Effect
No Effect
No Effect
Transparent
Latched
Latched
Latched Data = 0000H
H
↑+
H
H
Latched Data = 0000H
Latched Data = 8000H
L
H
Latched Data = 8000H
–6–
REV. 0
AD5544/AD5554
Table II. AD5554 Control-Logic Truth Table
CS CLK LDAC RS
MSB Serial Shift Register Function Input Register Function DAC Register
H
L
L
L
↑+
X
L
↑+
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Shift-Register-Data Advanced One Bit Latched
No Effect
No Effect
Latched
Selected DAC Updated
with Current SR Contents
Latched
Latched
Latched
Latched Data = 0000H
Latched Data = 2000H
H
H
H
H
H
X
X
X
X
X
L
H
H
H
L
X
X
X
0
No Effect
No Effect
No Effect
No Effect
No Effect
Transparent
Latched
Latched
Latched Data = 0000H
Latched Data = 2000H
H
↑+
H
H
L
H
NOTES
1. SR = Shift Register.
2. ↑+ positive logic transition; X = Don’t Care.
3. At power ON both the Input Register and the DAC Register are loaded with all zeros.
4. For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
5. For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
Table III. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9
LSB
B1 B0
D2 D1 D0
B8
B7
B6
B5
B4
B3
B2
D8
D7
D6
D5
D4
D3
NOTE
Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table IV. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B15
LSB
B14
A0
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word A1
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOTE
Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table V. Address Decode
A1
A0
DAC Decoded
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
–7–
REV. 0
AD5544/AD5554
AD5544/AD5554 PIN FUNCTION DESCRIPTIONS
Pin # Name
Function
DAC A Analog Ground.
DAC A Current Output.
1
2
3
4
5
6
AGND
A
I
OUTA
V
R
REFA
FBA
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
Establish Voltage Output for DAC A by Connecting to External Amplifier Output.
MSB Bit Set Pin During a Reset Pulse (RS) or at System Power ON if Tied to Ground or VDD.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for
AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB
= 0. Register Data = 8000H for AD5544 and 2000H for AD5554 when MSB = 1.
MSB
RS
7
8
VDD
CS
Positive Power Supply Input. Specified range of operation 5 V 10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input
Register when CS/LDAC returns High. Does not effect LDAC operation.
9
CLK
SDI
Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input, Input Data Loads Directly into the Shift Register.
Establish Voltage Output for DAC B by Connecting to External Amplifier Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for
AD5544 and 17 clock pulses for AD5554 after input at the SDI pin.
10
11
12
13
14
15
16
17
18
19
20
R
V
FBB
REFB
I
OUTB
A
A
GNDB
GNDC
I
OUTC
V
R
REFC
FBC
NC
SDO
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
22
23
24
25
26
27
28
A
VSS
GNDF
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation –0.3 V to –5.5 V.
DGND Digital Ground Pin.
R
V
FBD
REFD
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
DAC D Current Output.
I
OUTD
AGND
D
DAC D Analog Ground.
AD5544/AD5554 PIN CONFIGURATION
1
2
A
A
A
A
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
D
GND
GND
I
I
D
OUT
OUT
3
V
V
D
REF
REF
4
R
R
D
FB
FB
5
MSB
DGND
AD5544/
AD5554
6
V
RS
SS
7
V
A
F
DD
GND
TOP VIEW
(Not to Scale)
8
CS
CLK
SDI
LDAC
SDO
NC
9
10
11
12
13
14
R
B
B
B
B
R
C
FB
FB
V
V
C
REF
OUT
GND
REF
I
I
C
OUT
A
A
C
GND
NC = NO CONNECT
–8–
REV. 0
Typical Performance Characteristics–AD5544/AD5554
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
DAC A
DAC B
DAC C
0.00
–0.25
–0.50
DAC A
DAC B
DAC C
DAC D
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
0.00
–0.25
–0.50
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
0.00
–0.25
–0.50
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
DAC D
8192
0.00
–0.25
–0.50
0
8192 16384 24576 32768 40960 49152 57344 65536
0
2048 4096
6144
10240 12288 14336 16384
CODE – Decimal
CODE – Decimal
TPC 1. AD5544 DNL vs. Code (TA = 25°C)
TPC 3. AD5554 DNL vs. Code (TA = 25°C)
1.0
DAC A
DAC B
DAC C
0.5
0.0
2.0
1.5
V
V
T
= 5V
DD
–0.5
–1.0
= 10V
REF
= 25ꢂC
F000
8000
A
H
1.0
0.5
0
1.0
0.5
H
0.0
–0.5
–1.0
7FFF
H
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0FFF
H
0.0
–0.5
–1.0
0
–1500
–1000
–500
500
1000
1500
1.0
0.5
DAC D
OP AMP OFFSET VOLTAGE – ꢁV
0.0
–0.5
–1.0
TPC 4. AD5544 Integral Nonlinearity Error vs.
Op Amp Offset
0
2048 4096
6144
8192
10240 12288 14336 16384
CODE – Decimal
TPC 2. AD5554 INL vs. Code (TA = 25°C)
–9–
REV. 0
AD5544/AD5554
0.75
10.0
7.5
V
V
T
= 5V
V
V
T
= 5V
DD
DD
= 10V
= 10V
REF
REF
0.50
0.25
0.00
= 25ꢂC
= 25ꢂC
A
A
3000
H
5.0
2000
2.5
0.0
H
1FFF
H
H
–2.5
–5.0
–0.25
–0.50
–0.75
0FFF
–7.5
–10.0
–1500
0
–2000 –1500 –1000 –500
500
1000
1500 2000
0
–1000
–500
500
1000
1500
OP AMP OFFSET VOLTAGE – ꢁV
OP AMP OFFSET VOLTAGE – ꢁV
TPC 5. AD5554 Integral Nonlinearity Error vs.
Op Amp Offset
TPC 8. AD5544 Gain Error vs. Op Amp Offset
1.00
4
V
V
T
= 5V
V
V
T
= 5V
DD
DD
= 10V
= 10V
3
2
REF
0.75
REF
8000
F000
H
= 25ꢂC
= 25ꢂC
A
A
0.50
0.25
1
0
H
0.00
0FFF
H
–1
–2
–3
–4
–0.25
–0.50
–0.75
–1.00
–5
–1500
0
–1000 –750
–500 –250
250
500
750
1000
0
–1000
–500
500
1000
1500
OP AMP OFFSET VOLTAGE – ꢁV
OP AMP OFFSET VOLTAGE – ꢁV
TPC 6. AD5544 Differential Nonlinearity Error vs.
Op Amp Offset
TPC 9. AD5554 Gain Error vs. Op Amp Offset
0.3
30
V
V
T
= 5V
SS = 120 UNITS
2000
3000
DD
H
V
V
= 5V
= 10V
DD
REF
0.2
0.1
= 10V
= 25ꢂC
REF
A
T
= –40ꢂC TO +85ꢂC
A
H
20
10
0
0.0
0FFF
H
–0.1
–0.2
–0.3
ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.
0
–1500
–1000
–500
500
1000
1500
0
0.5
1.0
1.5
OP AMP OFFSET VOLTAGE – ꢁV
FULL-SCALE TEMPCO – ppm/ꢂC
TPC 7. AD5554 Differential Nonlinearity Error vs.
Op Amp Offset
TPC 10. AD5544 Full-Scale Tempco (ppm/ꢂC)
–10–
REV. 0
AD5544/AD5554
60
40
30
20
10
SS = 180 UNITS
V
V
T
= 5V
DD
= 10V
REF
V
OUT
(10V/DIV)
V
V
= 5V
= –40ꢂC TO +85ꢂC
DD
A
= 10V
REF
T
= 25ꢂC
= –343
A
A
V
1LSB = 52mV
V
OUT
(50mV/DIV)
1ꢁs/DIV
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
FULL-SCALE ERROR TEMPCO – ppm/ꢂC
TPC 11. AD5554 Full-Scale Tempco (ppm/ꢂC)
TPC 14. AD5544 Small Signal Settling Time
10000
1000
100
7FFF ➔ 8000
V
= 5V
DD
= 10V
= 25ꢂC
H
H
V
V
= 5V
DD
5555
FFFF
H
V
REF
= 10V
REF
T
A
T
= 25ꢂC
A
CS
(5V/DIV)
H
8000
H
H
0000
V
OUT
(50mV/DIV)
100ns/DIV
10
1k
10k
100k
1M
10M
100M
CLOCK FREQUENCY – Hz
TPC 12. AD5544 Midscale Transition
TPC 15. AD5544 Power Supply Current vs.
Clock Frequency
10000
1000
100
V
V
= 5V
DD
1555
0000 ➔ FFFF
V
= 5V
DD
= 10V
= 25ꢂC
H
H
H
= 10V
REF
V
REF
T
= 25ꢂC
A
CS
(5V/DIV)
T
A
3FFF
H
2000
H
H
0000
V
OUT
(5V/DIV)
2ꢁs/DIV
10
1k
10k
100k
1M
10M
100M
CLOCK FREQUENCY – Hz
TPC 16. AD5554 Power Supply Current vs.
Clock Frequency
TPC 13. AD5544 Large Signal Settling Time
–11–
REV. 0
AD5544/AD5554
100
600
500
400
300
200
100
0
V
= 5V ꢀ10%
V = 5V
DD
DD
= 25ꢂC
90
80
70
60
50
40
30
20
T
V
= 10V
A
REF
T
= 25ꢂC
A
100
1k
10k
100k
1M
0
1
2
3
4
5
CLOCK FREQUENCY – Hz
LOGIC INPUT VOLTAGE – Volts
TPC 17. AD5544/AD5554 Power Supply Rejection
vs. Frequency
TPC 19. AD5544/AD5554 Power Supply Current
vs. Logic Input Voltage
55
V
V
= 5V
DD
54
53
52
51
50
49
48
47
46
= 10V
REF
LOGIC = V
DD
–50
–25
0
25
50
75
100
125
150
TEMPERATURE – ꢂC
TPC 18. AD5544/AD5554 Power Supply Current
vs. Temperature
CIRCUIT OPERATION
with both negative or positive reference voltages. The VDD power
pin is only used by the logic to drive the DAC switches ON and
OFF. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to mea-
sure the value of RFB, power must be applied to VDD in order to
achieve continuity. An additional VSS bias pin is used to guard
the substrate during high temperature applications to minimize
zero-scale leakage currents that double every 10°C. The DAC
output voltage is determined by VREF and the digital data (D) as:
The AD5544 and AD5554 contain four, 16-bit and 14-bit,
current-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD5544/AD5554 use 3-wire SPI compatible serial data inter-
face, with a configurable asynchronous RS pin for half-scale
(MSB = 1) or zero-scale (MSB = 0) preset. In addition, an
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
D/A Converter Section
D
Each part contains four current-steering R-2R ladder DACs.
Figure 4 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The RFBX pin is connected to the output of
the external amplifier. The IOUTX terminal is connected to the
inverting input of the external amplifier. The AGNDX pin should
be Kelvin-connected to the load point in the circuit requiring
the full 16-bit accuracy. These DACs are designed to operate
V
= −V
×
×
(For AD5544)
(Equation 1)
OUT
REF
65536
D
V
OUT
= −V
(For AD5554)
(Equation 2)
REF
16384
Note that the output polarity is opposite to the VREF polarity for
dc reference voltages.
–12–
REV. 0
AD5544/AD5554
FFFF
V
H
DD
B15
B14
B13
B12
B11
B10
B9
R
R
R
R
X
V
X
FB
REF
2R
2R
2R
R
5kꢃ
S2
S1
I
X
OUT
B8
B7
B6
A
F
GND
B5
B4
A
X
GND
FROM OTHER DACS A
GND
B3
B2
V
DGND
B1
SS
V
V
= 5V
DD
B0
ZS
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED.
= 100mV rms
REF
DD
T
= 25ꢂC
A
Figure 4. Typical Equivalent DAC Channel
100
1k
10k
100k
1M 10M
These DACs are also designed to accommodate ac reference
input signals. Both AD5544/AD5554 will accommodate input
reference voltages in the range of –12 V to +12 V. The reference
voltage inputs exhibit a constant nominal input resistance of
5 kΩ, 30%. On the other hand, the DAC outputs IOUTA, B,
C, D are code-dependent and produce various output resis-
tances and capacitances. The choice of external amplifier
should take into account the variation in impedance generated
by the AD5544/AD5554 on the amplifiers’ inverting input
node. The feedback resistance, in parallel with the DAC ladder
resistance, dominates output voltage noise. For multiplying
mode applications, an external feedback compensation capacitor
(CFB) may be needed to provide a critically damped output
response for step changes in reference input voltages. Figures 5
and 6 show the gain vs. frequency performance at various
attenuation settings using a 23 pF external feedback capacitor
connected across the IOUTX and RFBX terminals for AD5544
and AD5554 respectively. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel
with 1 µF, is recommended. Under these conditions, clean
power supply with low ripple voltage capability should be used.
Switching power supplies is usually not suitable for this application
due to the higher ripple voltage and PSS frequency-dependent
characteristics. It is best to derive the AD5544/AD5554’s 5 V
supply from the systems’ analog supply voltages. (Do not use
the digital 5 V supply.) See Figure 7.
FREQUENCY – Hz
Figure 5. AD5554 Reference Multiplying Bandwidth
vs. Code
3FFF
H
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
V
V
= 5V
DD
= 100mV rms
ZS
REF
T
= 25ꢂC
= 23pF
A
C
F
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 6. AD5554 Reference Multiplying Bandwidth
vs. Code
15V
ANALOG
2R
POWER
SUPPLY
5V
+
R
V
DD
AD5544
R
FB
X
R
R
R
V
X
REF
2R
2R
2R
R
5kꢃ
15V
V
S2
S1
I
X
CC
OUT
V
A
F
OUT
GND
A1
A
X
GND
+
V
EE
LOAD
FROM OTHER DACS A
GND
DGND
V
SS
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
MUST BE POWERED.
V
DD
Figure 7. Recommended Kelvin-Sensed Hookup
–13–
REV. 0
AD5544/AD5554
V
A B C D
REF
CS
EN
AD5544
V
DD
CLK
R
I
A
FB
SDI
16
D0
DAC A
INPUT
D1
D2
A
DAC A
OUT
REGISTER
REGISTER
R
R
R
R
R
D3
A
A
GND
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
R B
FB
INPUT
REGISTER
DAC B
REGISTER
I
B
DAC B
OUT
R
R
R
A
B
DAC A
GND
SDO
B
C
D
A1
2:4
DECODE
R
I
C
FB
INPUT
REGISTER
DAC C
REGISTER
C
DAC C
OUT
A
C
GND
R
I
D
FB
INPUT
REGISTER
DAC D
REGISTER
D
DAC D
OUT
A
D
GND
SET
MSB
SET
MSB
A
F
POWER-
ON
RESET
GND
DGND
MSB
V
LDAC
RS
SS
Figure 8. System Level Digital Interfacing
SERIAL DATA INTERFACE
can be written to the AD5554. Keeping the CS line low between
the first and second byte transfer will result in a successful serial
register update.
The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI com-
patible serial data interface. Serial data of AD5544 and AD5554
is clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table
II defines the 18 data-word bits for AD5544. Table III defines
the 16 data-word bits for AD5554. Data is placed on the SDI
pin, and clocked into the register on the positive clock edge of
CLK subject to the data setup and data hold time requirements
specified in the Interface Timing Specifications. Data can only
be clocked in while the CS chip select pin is active low. For
AD5544, only the last 18 bits clocked into the serial register will
be interrogated when the CS pin returns to the logic high state,
extra data bits are ignored. For AD5554, only the last 16 bits
clocked into the serial register will be interrogated when the CS
pin returns to the logic high state. Since most microcontrollers
output serial data in 8-bit bytes, three right-justified data bytes
can be written to the AD5544. Keeping the CS line low between
the first, second, and third byte transfers will result in a success-
ful serial register update. Similarly, two right-justified data bytes
Once the data is properly aligned in the shift register, the posi-
tive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address bits A1
and A0. For AD5544, Tables I, III, V, and Figure 2 define the
characteristics of the software serial interface. For AD5554,
Tables II, IV, V, and Figure 3 define the characteristics of the
software serial interface. Figures 8 and 9 show the equivalent
logic interface for the key digital control pins for AD5544.
AD5554 has similar configuration, except with 14 data bits.
Two additional pins RS and MSB provide hardware control
over the preset function and DAC Register loading. If these
functions are not needed, the RS pin can be tied to logic high.
The asynchronous input RS pin forces all input and DAC regis-
ters to either the zero-code state (MSB = 0), or the half-scale
state (MSB = 1)
–14–
REV. 0
AD5544/AD5554
TO INPUT REGISTER
APPLICATIONS
The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.
A
B
C
D
ADDRESS
DECODER
CS
EN
SHIFT REGISTER
In some applications it may be necessary to generate the full 4-
quadrant multiplying capability or a bipolar output swing. This
is easily accomplished using an additional external amplifier
(A2) configured as a summing amplifier (see Figure 11). In this
circuit the first and second amplifiers (A1 and A2) provide a
total gain-of-2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the refer-
ence voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = –10 V) to midscale (VOUT
= 0 V) to full-scale (VOUT = 10 V).
CLK
SDI
TH
TH
19 /17
CLOCK
SDO
Figure 9. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the VDD power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state or half-scale, depending on the MSB pin voltage. The VDD
power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on
the power-ON reset performance. The DAC register data will
stay at zero or half-scale setting until a valid serial register data
load takes place.
D
VOUT
=
=
−1 ×V
REF
(For AD5544)
(Equation 3)
(Equation 4)
32768
D
VOUT
−1 ×VREF
(For AD5554)
ESD Protection Circuits
8192
All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and VDD as shown in Figure 9.
10kꢃ
10kꢃ
5kꢃ
V
DD
10V
V
REF
A2
V
OUT
5kꢃ
DIGITAL
INPUTS
AD588
–10V < V
< +10V
OUT
V
DD
V
X
R
X
REF
FB
DGND
I
X
OUT
ONE CHANNEL
AD5544
Figure 10. Equivalent ESD Protection Circuits
A1
V
A
F
A
X
SS
GND
GND
PCB LAYOUT
In PCB layout, all analog ground, AGNDX, should be tied together.
Amplifiers suitable for I-to-V conversion include:
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
Figure 11. Four-Quadrant Multiplying Application Circuit
• High Accuracy: OP97, OP297
• Speed and Accuracy: OP42
•
5 V Applications: OP162/OP262/OP462, OP184/OP284/
OP484
–15–
REV. 0
AD5544/AD5554
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
0.022 (0.558)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–16–
REV. 0
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