AD5551BR-REEL7 [ADI]
2.7 V to 5.5 V, Serial-Input, Voltage-Output, 14-Bit DACs; 2.7 V至5.5 V ，串行输入，电压输出， 14位DAC
| 型号： | AD5551BR-REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.7 V to 5.5 V, Serial-Input, Voltage-Output, 14-Bit DACs |
| 文件： | 总16页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 14-Bit DACs
AD5551/AD5552
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
DD
Full 14-bit performance
8
3 V and 5 V single supply operation
Low 0.625 mW power dissipation
1 μs settling time
Unbuffered voltage output capable of driving 60 kΩ
loads directly
SPI/QSPI/MICROWIRE-compatible interface standards
Power-on reset clears DAC output to 0 V (unipolar mode)
5 kV HBM ESD classification
AD5551
3
1
2
V
14-BIT DAC
V
OUT
REF
CS
AGND
4
6
14-BIT DATA LATCH
DIN
CONTROL
LOGIC
5
SERIAL INPUT REGISITER
SCLK
7
DGND
APPLICATIONS
Figure 1.
Digital gain and offset adjustment
Automatic test equipment
Data acquisition systems
V
DD
14
R
FB
AD5552
1
RFB
Industrial process control
R
INV
13 INV
6
V
REFF
GENERAL DESCRIPTION
2
3
V
OUT
14-BIT DAC
The AD5551/AD5552 are single, 14-bit, serial-input, voltage-
output DACs that operate from a single 2.7 V to 5.5 V supply.
The DAC output range extends from 0 V to VREF
5
7
V
AGNDF
REFS
14-BIT DATA LATCH
CS
.
LDAC 11
CONTROL
LOGIC
4
AGNDS
These DACs provide 14-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed by an output buffer.
SCLK
DIN
8
10
SERIAL INPUT REGISITER
12
DGND
With an external op amp, the AD5552 can be operated in
Figure 2.
bipolar mode generating a
VREF output swing. The AD5552
also includes Kelvin sense connections for the reference and
analog ground pins to reduce layout sensitivity. For higher
precision applications, refer to 16-bit DACs AD5541, AD5542,
and AD5544.
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
The AD5551 and AD5552 are fully specified and
guaranteed for a single 2.7 V to 5.5 V supply.
2. Low Power Consumption.
Typically 0.625 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered output capable of driving 60 kΩ loads, which
reduces power consumption as there is no internal buffer
to drive.
The AD5551/AD5552 utilize a versatile 3-wire interface that is
compatible with SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The AD5551 and AD5552 are available in 8-lead and
14-lead SOIC packages.
5. Power-On Reset Circuitry.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved.
AD5551/AD5552
TABLE OF CONTENTS
Features .............................................................................................. 1
Bipolar Output Operation......................................................... 12
Output Amplifier Selection....................................................... 12
Force Sense Buffer Amplifier Selection................................... 12
Reference and Ground............................................................... 13
Power-On Reset.......................................................................... 13
Power Supply and Reference Bypassing.................................. 13
Microprocessor Interfacing........................................................... 14
ADSP-21xx to AD5551/AD5552 Interface............................. 14
68HC11 to AD5551/AD5552 Interface................................... 14
MICROWIRE to AD5551/AD5552 Interface ........................ 14
80C51/80L51 to AD5551/AD5552 Interface.......................... 14
Applications Information.............................................................. 15
Optocoupler Interface................................................................ 15
Decoding Multiple AD5551/AD5552s.................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Digital-to-Analog Section......................................................... 11
Serial Interface ............................................................................ 11
Unipolar Output Operation...................................................... 11
REVISION HISTORY
5/10—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Data Sheet Title, Features Section, General
Description Section, and Product Highlights Section................. 1
Changes to Specifications Section.................................................. 3
Changes to Table 3............................................................................ 5
Changes to Pin VDD Description in Table 4 and Table 5 ............. 6
Changes to Typical Performance Characteristics Section........... 7
Changes to First Paragraph in Theory of Operation Section ... 11
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/00—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD5551/AD5552
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
14
Bits
Relative Accuracy, INL
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Zero-Code Error
±±.1ꢀ
±±.1ꢀ
−±.3
±±.1
±.1
±1.±
±±.ꢁ
+±.ꢀ
LSB
LSB
LSB
ppm/°C
LSB
B grade
Guaranteed monotonic
−1.ꢀ
±1
Zero-Code Temperature Coefficient
ADꢀꢀꢀ2
±±.±ꢀ
ppm/°C
Bipolar Resistor Matching
1.±±±
±±.±±1ꢀ
±±.2ꢀ
±±.2
−±.3
−±.3
Ω/Ω
%
LSB
ppm/°C
LSB
LSB
RFB/RINV, typically RFB = RINV = 2ꢁ kΩ
Ratio error
±±.±1ꢀ2
±1
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Error
Bipolar Gain Error
±1.2
±1.2
OUTPUT CHARACTERISTICS2
Output Voltage Range
±
VREF − 1 LSB
VREF − 1 LSB
V
V
μs
V/μs
nV-sec
nV-sec
kΩ
Unipolar operation
−VREF
ADꢀꢀꢀ2 bipolar operation
To ½ LSB of FS, CL = 1± pF
CL = 1± pF, measured from ±% to 63%
1 LSB change around the major carry
All 1s loaded to DAC, VREF = 2.ꢀ V
Tolerance typically 2±%
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Power Supply Rejection Ratio
DAC REFERENCE INPUT
Reference Input Range
Reference Input Resistance3
1
17
1.1
±.2
6.2ꢀ
±1.±
VDD
LSB
ΔVDD ± 1±%
2.±
9
7.ꢀ
V
kΩ
kΩ
Unipolar operation
ADꢀꢀꢀ2, bipolar operation
LOGIC INPUTS
Input Current
±1
±.ꢁ
μA
V
V
pF
V
VINL, Input Low Voltage
VINH, Input High Voltage
Input Capacitance2
Hysteresis Voltage2
REFERENCE2
2.4
1±
±.1ꢀ
Reference −3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
2.2
1
92
26
26
MHz
mV p-p
dB
pF
pF
All 1s loaded
All ±s loaded, VREF = 1 V p-p at 1±± kHz
Code ±±±±H
Code 3FFFH
POWER REQUIREMENTS
Digital inputs at rails
VDD
2.7
ꢀ.ꢀ
V
IDD
12ꢀ
1ꢀ±
±.ꢁ2ꢀ
μA
mW
Power Dissipation
±.62ꢀ
1 Temperature range is as follows: B version: −4±°C to +ꢁꢀ°C;
2 Guaranteed by design, not subject to production test.
3 Reference input resistance is code-dependent, minimum at 2ꢀꢀꢀH.
Rev. A | Page 3 of 16
AD5551/AD5552
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
All Versions
Parameter1, 2
Unit
Description
fSCLK
t1
t2
t3
t4
2ꢀ
4±
2±
2±
1ꢀ
1ꢀ
3ꢀ
2±
1ꢀ
±
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
tꢀ
t6
t7
tꢁ
t9
t1±
t11
t12
Data hold time
LDAC pulse width
3±
3±
3±
CS high to LDAC low setup
CS high time between active periods
1 Guaranteed by design, not production tested.
2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = ꢀ ns (1±% to
9±% of +3 V and timed from a voltage level of +1.6 V).
t1
SCLK
t2
t3
t6
t5
t7
t4
CS
t12
t8
t9
DIN
DB13
DB0
t11
t10
LDAC*
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 3. Timing Diagram
Rev. A | Page 4 of 16
AD5551/AD5552
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to AGND
Digital Input Voltage to DGND
VOUT to AGND
–±.3 V to +6 V
–±.3 V to VDD + ±.3 V
–±.3 V to VDD + ±.3 V
–±.3 V to +±.3 V
±1± mA
AGND, AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature, (TJ max)
Package Power Dissipation
Thermal Impedance
ESD CAUTION
−4±°C to +ꢁꢀ°C
−6ꢀ°C to +1ꢀ±°C
1ꢀ±°C
(TJ max – TA)/θJA
θJA
SOIC (R-ꢁ)
SOIC (R-14)
149.ꢀ°C/W
1±4.ꢀ°C/W
Lead Temperature, Soldering
Peak Temperature1
ESD2
26±°C
ꢀ kV
1 As per JEDEC Standard 2±.
2 HBM classification.
Rev. A | Page ꢀ of 16
AD5551/AD5552
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RFB
1
2
3
4
5
6
7
14 V
DD
V
13 INV
OUT
AGNDF
12 DGND
11 LDAC
10 DIN
AD5552
AGNDS
TOP VIEW
(Not to Scale)
V
V
1
2
3
4
8
7
6
5
V
DD
REFS
OUT
AD5551
V
9
8
NC
AGND
DGND
DIN
REFF
TOP VIEW
CS
SCLK
V
REF
(Not to Scale)
CS
SCLK
NC = NO CONNECNT
Figure 4. AD5551 Pin Configuration
Figure 5. AD5552 Pin Configuration
Table 4. AD5551 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
ꢀ
VOUT
AGND
VREF
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry.
This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
CS
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 4±%
and 6±%.
6
7
ꢁ
DIN
DGND
VDD
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
Digital Ground. Ground reference for digital circuitry.
Analog Supply Voltage, 2.7 V to ꢀ.ꢀ V ± 1±%.
Table 5. AD5552 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
ꢀ
6
7
ꢁ
RFB
VOUT
AGNDF
AGNDS
VREFS
Feedback Resistor. In bipolar mode, connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
VREFF
CS
SCLK
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 4±%
and 6±%.
9
NC
No Connect.
1±
11
DIN
LDAC
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
12
13
DGND
INV
Digital Ground. Ground reference for digital circuitry.
Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14
VDD
Analog Supply Voltage, 2.7 V to ꢀ.ꢀ V ± 1±%.
Rev. A | Page 6 of 16
AD5551/AD5552
TYPICAL PERFORMANCE CHARACTERISTICS
0.125
0.125
0.062
0
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
0.062
0
–0.062
–0.125
–0.062
–0.125
–0.187
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
CODE
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
0.062
0.187
V
= 5V
V
= 5V
DD
DD
V
= 2.5V
V
= 2.5V
REF
REF
0
–0.062
–0.125
–0.187
0.125
0.062
0
–0.062
–0.250
–0.125
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Integral Nonlinearity vs. Temperature
Figure 10. Differential Nonlinearity vs. Temperature
0.125
0.187
V
T
= 5V
V
= 2.5V
DD
= 25°C
REF
= 25°C
T
A
A
0.062
0
0.125
0.062
0
DNL
DNL
–0.062
–0.125
INL
–0.062
INL
–0.187
–0.125
2
3
4
5
6
7
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 8. Linearity Error vs. Supply Voltage
Figure 11. Linearity Error vs. Reference Voltage
Rev. A | Page 7 of 16
AD5551/AD5552
0
–0.025
–0.050
–0.075
–0.100
–0.125
–0.150
–0.175
–0.200
0.037
0.025
0.012
0
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REF
REF
T
= 25°C
T = 25°C
A
A
–0.012
–0.025
–0.037
–0.225
–40
25
85
–40
25
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Gain Error vs. Temperature
Figure 15. Zero-Code Offset Error vs. Temperature
132
130
128
126
124
122
120
118
116
2.0
1.5
1.0
0.5
V
V
= 5V
DD
T
= 25°C
A
= 2.5V
REF
T
= 25°C
A
REFERENCE VOLTAGE
= 5V
V
DD
SUPPLY VOLTAGE
= 2.5V
V
REF
0
0
–40
25
85
1
2
3
VOLTAGE (V)
4
5
6
TEMPERATURE (°C)
Figure 13. Supply Current vs. Temperature
Figure 16. Supply Current vs. Reference Voltage or Supply Voltage
200
200
V
V
= 5V
DD
180
160
140
120
100
80
= 2.5V
REF
T
= 25°C
A
150
100
50
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE (Decimal)
DIGITAL INPUT VOLTAGE (V)
Figure 17. Reference Current vs. Code
Figure 14. Supply Current vs. Digital Input Voltage
Rev. A | Page ꢁ of 16
AD5551/AD5552
V
V
= 2.5V
V
V
T
= 2.5V
REF
= 5V
REF
= 5V
2µs/DIV
DD
= 25°C
DD
= 25°C
A
T
A
CS (5V/DIV)
DIN (5V/DIV)
10pF
50pF
100pF
200pF
V
(50mV/DIV)
OUT
V
(0.5V/DIV)
OUT
2µs/DIV
Figure 18. Digital Feedthrough
Figure 20. Large Signal Settling Time
1.236
1.234
1.232
1.230
1.228
1.226
1.224
5
V
V
T
= 2.5V
REF
= 5V
DD
= 25°C
CS
0
A
V
(1V/DIV)
OUT
–5
–10
–15
–20
–25
–30
V
(50mV/DIV)
OUT
GAIN = –216
V
OUT
0.5µs/DIV
–0.5
0
0.5
1.0
1.5
2.0
TIME (ns)
Figure 19. Digital-to-Analog Glitch Impulse
Figure 21. Small Signal Settling Time
Rev. A | Page 9 of 16
AD5551/AD5552
TERMINOLOGY
Digital-to-Analog Glitch Impulse
Relative Accuracy
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A plot of the glitch impulse
is shown in Figure 19.
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. A typical DNL vs. code plot can be seen
in Figure 9.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
CS
but is measured when the DAC output is not updated.
is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-sec and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa. A
typical plot of digital feedthrough is shown in Figure 18.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It
is the deviation in slope of the DAC transfer characteristic
from ideal.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power-supply
rejection ratio is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by 10%.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero-Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Reference Feedthrough
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
Zero-Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Rev. A | Page 1± of 16
AD5551/AD5552
THEORY OF OPERATION
The AD5551/AD5552 are single, 14-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5.5 V and consume typically 125 μA with a supply of
5 V. Data is written to these devices in a 14-bit word format, via
a 3-or 4-wire serial interface. To ensure a known power-up
state, these parts were designed with a power-on reset function.
In unipolar mode, the output is reset to 0 V, while in bipolar
mode, the AD5552 output is set to −VREF. Kelvin sense
connections for the reference and analog ground are included
on the AD5552.
SERIAL INTERFACE
The AD5551/AD5552 are controlled by a versatile 3-wire serial
interface, which operates at clock rates up to 25 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 3. Input
CS
data is framed by the chip select input, . After a high-to-low
CS
transition on , data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 14-bit words. After 14 data bits
have been loaded into the serial input register, a low-to-high
DIGITAL-TO-ANALOG SECTION
CS
transition on
the DAC. Data can only be loaded to the part while
LDAC
transfers the contents of the shift register to
CS
is low.
function that allows the DAC latch
LDAC CS
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 22. The DAC
architecture of the AD5551/AD5552 is segmented. The four
MSBs of the 14-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or VREF. The remaining 10 bits of the
data word drive switches S0 to S9 of a 10-bit voltage mode R-2R
ladder network.
The AD5552 has an
to be updated asynchronously by bringing
LDAC
low after
should be maintained high while data is
LDAC
goes high.
written to the shift register. Alternatively,
permanently low to update the DAC synchronously. With
LDAC CS
may be tied
tied permanently low, the rising edge of
loads
the data to the DAC.
R
R
V
OUT
UNIPOLAR OUTPUT OPERATION
2R
2R
S0
2R . . . . .
S1 . . . . .
2R
S9
2R
E1
2R . . . . .
E2 . . . . .
2R
E15
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low-supply current, typically
300 ꢀA, and a low-offset error. The AD5551 provides a unipolar
output swing ranging from 0 V to VREF. The AD5552 can be con-
figured to output both unipolar and bipolar voltages. Figure 23
shows a typical unipolar output voltage circuit. The code table
for this mode of operation is shown in Table 6.
V
REF
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
10-BIT R-2R LADDER
Figure 22. DAC Architecture
5V 2.5V
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage as shown in the following
equation:
10µF
0.1µF
0.1µF
SERIAL
INTERFACE
V
V
*
V
*
DD
REFF
REFS
AD820/
OP196
CS
VREF × D
UNIPOLAR
OUTPUT
DIN
AD5551/
AD5552
V
OUT
VOUT
where:
=
2N
SCLK
EXTERNAL
OP AMP
LDAC*
DGND
AGND
D is the decimal data word loaded to the DAC register.
N is the resolution of the DAC.
*AD5552 ONLY.
Figure 23. Unipolar Output
For a reference of 2.5 V, the equation simplifies to the following,
Table 6. Unipolar Code Table
2.5 × D
VOUT
=
DAC Latch Contents
16,384
MSB
LSB
Analog Output
This gives a VOUT of 1.25 V with midscale loaded, and a VOUT
of 2.5 V with full-scale loaded to the DAC. The LSB size is
VREF/16,384.
11 1111 1111 1111
1± ±±±± ±±±± ±±±±
±± ±±±± ±±±± ±±±1
±± ±±±± ±±±± ±±±±
VREF × (16,3ꢁ3/16,3ꢁ4)
VREF × (ꢁ192/16,3ꢁ4) = ½ VREF
VREF × (1/16,3ꢁ4)
± V
Rev. A | Page 11 of 16
AD5551/AD5552
Assuming a perfect reference, the worst-case output voltage
may be calculated from the following equation:
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
D
[(VOUT−UNI +VOS )(2 + RD) −VREF (1 + RD)
VOUT −UNI
=
×
(
VREF + VGE + VZSE + INL
)
VOUT−BIP
=
214
1 + (2 + RD)/ A
where:
OUT–UNI is the unipolar mode worst-case output.
D is the decimal code loaded to the DAC.
where:
OS is the external op amp input offset voltage.
RD is the RFB and RIN resistor matching error, unitless.
A is the op amp open-loop gain.
V
V
V
V
V
REF is the reference voltage applied to part.
GE is the gain error in volts.
ZSE is the zero-scale error in volts.
OUTPUT AMPLIFIER SELECTION
INL is the integral nonlinearity in volts.
For bipolar mode, use a precision amplifier, supplied from a
dual power supply. This provides the VREF output. In a single-
supply application, selection of a suitable op amp may be more
difficult as the output swing of the amplifier does not usually
include the negative rail, in this case AGND. This can result in
some degradation of the specified performance unless the
application does not use codes near zero.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5552 may be confi-
gured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors RFB and RINV are connected to an external op amp
to achieve this bipolar output swing where RFB = RINV = 28 kΩ.
Table 7 shows the transfer function for this output operating
mode. Also provided on the AD5552 are a set of Kelvin
connections to the analog ground inputs.
The selected op amp needs to have a very low-offset voltage,
(the DAC LSB is 152 μV with a 2.5 V reference), to eliminate
the need for output offset trims. Input bias current should also
be very low as the bias current multiplied by the DAC output
impedance (approximately 6K) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, therefore increasing the settling time of the output.
A higher 3 dB amplifier bandwidth results in a faster effective
settling time of the combined DAC and amplifier.
5V 2.5V
10µF
0.1µF
0.1µF
+5V
RFB
SERIAL
INTERFACE
V
V
V
REFS
DD
REFF
R
FB
INV
EXTERNAL
OP AMP
CS
R
INV
UNIPOLAR
OUTPUT
DIN
V
OUT
AD5552
SCLK
–5V
LDAC
DGND AGNDF AGNDS
Figure 24. Bipolar Output (AD5552 Only)
FORCE SENSE BUFFER AMPLIFIER SELECTION
Table 7. Bipolar Code Table
DAC Latch Contents
These amplifiers can be single-supply or dual supplies, low
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to 20 mA.
MSB
LSB
Analog Output
+VREF × (ꢁ191/ꢁ192)
+VREF × (1/ꢁ192)
± V
−VREF × (1/ꢁ192)
−VREF × (ꢁ191/ꢁ192) = –VREF
11 1111 1111 1111
1± ±±±± ±±±± ±±±±
±± ±±±± ±±±± ±±±1
±± ±±±± ±±±± ±±±±
±± ±±±± ±±±± ±±±±
Rev. A | Page 12 of 16
AD5551/AD5552
REFERENCE AND GROUND
POWER-ON RESET
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5551/
AD5552 operate with a voltage reference ranging from 2 V to
VDD. Although DAC’s full-scale output voltage is determined by
the reference, references below 2 V results in reduced accuracy.
Table 6 and Table 7 outline the analog output voltage for
particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5552.
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. After power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 14 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 14 bits are loaded,
only the last 14 are kept, and if fewer than 14 are loaded, bits
remain from the previous word. If the AD5551/AD5552 needs
to be interfaced with data shorter than 14 bits, the data should
be padded with zeros at the LSBs.
If the application does not require separate force and sense
lines, they should be tied together close to the package to
minimize voltage drops between the package leads and the
internal die. ADR291 and ADR293 are suitable references
for this product.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 ꢀF
tantalum capacitor in parallel with a 0.1 ꢀF ceramic capacitor.
Rev. A | Page 13 of 16
AD5551/AD5552
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
require a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
MICROWIRE TO AD5551/AD5552 INTERFACE
Figure 27 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
MICROWIRE*
AD5551/
AD5552*
CS
SO
CS
ADSP-21xx TO AD5551/AD5552 INTERFACE
DIN
SCLK
SCLK
Figure 25 shows a serial interface between the AD5551/AD5552
and the ADSP-21xx. The ADSP-21xx should be set to operate in
the SPORT (serial port) transmit alternate framing mode. The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows: internal clock operation,
active low framing, 16-bit word length. The first 2 bits are don’t
care as AD5551/AD5552 keeps the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. Because of the edges-triggered difference, an
inverter is required at the SCLKs between the DSP and the DAC.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 27. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 TO AD5551/AD5552 INTERFACE
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 28. TxD of the micro-
controller drives the SCLK of the AD5551/AD5552, while RxD
drives the serial data line of the DAC. P3.3 is a bit programmable
CS
pin on the serial port which is used to drive
.
ADSP-21xx*
AD5551/
80C51/
80L51*
AD5551/
AD5552*
*
AD5552
P3.4
P3.3
RxD
TxD
LDAC**
FO
LDAC**
CS
TFS
DT
CS
DIN
DIN
SCLK
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
Figure 25. ADSP-21xx to AD5551/AD5552 Interface
Figure 28. 80C51/80L51 to AD5551/AD5552 Interface
The 80C51/80L51 provides the LSB first, while the AD5551/
AD5552 expect the MSB of the 14-bit word first. Take care to
ensure that the transmit routine takes this into account. Usually
it can be done through software by shifting out and accumu-
lating the bits in the correct order before inputting to the DAC.
Also, 80C51 outputs 2 byte words/16 bits data, thus the first
two bits, after rearrangement, should be don’t care as they are
dropped from the 14-bit word of the DAC.
68HC11 TO AD5551/AD5552 INTERFACE
Figure 26 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC, while the MOSI output drives the serial data
CS
line DIN.
signal is driven from one of the port lines. The
68HC11 is configured for master mode; MSTR = 1, CPOL = 0,
and CPHA = 0. Data appearing on the MOSI output is valid on
the rising edge of SCK.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register
on the rising edge of the serial clock. The 80C51/80L51 transmits
its data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. As the DAC requires a 14-bit word,
68HC11/
68L11*
AD5551/
*
AD5552
PC6
PC7
LDAC**
CS
MOSI
SCK
DIN
SCLK
CS
P3.3 (or any one of the other programmable bits) is the
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY.
input signal to the DAC, so P3.3 should be brought low at the
beginning of the 16-bit write cycle 2 × 8 bit words and held low
until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is
brought high again and the new data loads to the DAC. Again,
Figure 26. 68HC11/68L11 to AD5551/AD5552 Interface
LDAC
the first two bits, after rearranging, should be don’t care.
on the AD5552 may also be controlled by the 80C51/80L51
serial port output by using another bit programmable pin, P3.4.
Rev. A | Page 14 of 16
AD5551/AD5552
APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
DECODING MULTIPLE AD5551/AD5552S
CS
The
a number of DACs. All devices receive the same serial clock and
CS
pin of the AD5551/AD5552 can be used to select one of
The digital inputs of the AD5551/AD5552 are Schmitt-
triggered, so they can accept slow transitions on the digital
input lines. This makes these parts ideal for industrial applica-
tions where it may be necessary that the DAC is isolated from
the controller via optocouplers. Figure 29 illustrates such an
interface.
serial data, but only one device receives the
signal at any one
time. The DAC addressed is determined by the decoder. There
is some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels. Figure 30 shows a typical circuit.
5V
REGULATOR
0.1µF
POWER
AD5551/
10µF
SCLK
AD5552
CS
V
OUT
OUT
OUT
OUT
V
DD
DD
DD
DIN
DIN
V
DD
SCLK
10kΩ
V
DD
SCLK
SCLK
ENABLE
AD5551/
AD5552
EN
V
AD5551/
AD5552
CS
CODED
ADDRESS
V
DECODER
DGND
DIN
10kΩ
V
SCLK
CS
CS
OUT
AD5551/
AD5552
V
CS
10kΩ
V
DIN
DIN
DIN
GND
SCLK
AD5551/
AD5552
Figure 29. AD5551/AD5552 in an Optocoupler Interface
CS
V
DIN
SCLK
Figure 30. Addressing Multiple AD5551/AD5552s
Rev. A | Page 1ꢀ of 16
AD5551/AD5552
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
INL
DNL
Temperature Range
−4±°C to +ꢁꢀ°C
−4±°C to +ꢁꢀ°C
−4±°C to +ꢁꢀ°C
−4±°C to +ꢁꢀ°C
−4±°C to +ꢁꢀ°C
Package Description
Package Option
ADꢀꢀꢀ1BRZ
±1 LSB
±±.ꢁ LSB
±±.ꢁ LSB
±±.ꢁ LSB
±±.ꢁ LSB
±±.ꢁ LSB
ꢁ-Lead SOIC_N
ꢁ-Lead SOIC_N
ꢁ-Lead SOIC_N
ꢁ-Lead SOIC_N
14-Lead SOIC_N
R-ꢁ
R-ꢁ
R-ꢁ
R-ꢁ
R-14
ADꢀꢀꢀ1BRZ-REEL7 ±1 LSB
ADꢀꢀꢀ1BR
ADꢀꢀꢀ1BR-REEL7
ADꢀꢀꢀ2BRZ
±1 LSB
±1 LSB
±1 LSB
1 Z = RoHS Compliant Part.
©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01943-0-5/10(A)
Rev. A | Page 16 of 16
相关型号：
AD5552BR-REEL7
IC SERIAL INPUT LOADING, 1 us SETTLING TIME, 14-BIT DAC, PDSO14, SOIC-14, Digital to Analog Converter
ADI
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