AD5544ARSZ-REEL7 [ADI]
Quad, Current-Output, Serial-Input 16-/14-Bit DACs; 四，电流输出，串行输入16位/ 14位DAC
| 型号： | AD5544ARSZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Quad, Current-Output, Serial-Input 16-/14-Bit DACs |
| 文件： | 总24页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
Data Sheet
AD5544/AD5554
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREFA B C D
AD5544: 16-bit resolution
INL of 1 LSB (B Grade)
AD5554: 14-bit resolution
INL of 0.5 LSB (B Grade)
2 mA full-scale current 20%, with VREF
0.9 µs settling time to 0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
VDD
RFB
D0
D1
D2
D3
D4
D5
D6
D7
D8
A
SDI
INPUT
REGISTER
DAC A
REGISTER
IOUT
AGND
FBB
A
DAC A
R
R
R
R
R
R
R
R
A
= 10 V
R
INPUT
REGISTER
DAC B
REGISTER
16
D9
IOUT
B
DAC B
DAC C
DAC D
D10
D11
D12
D13
D14
D15
A0
AGND
B
RFBC
INPUT
REGISTER
DAC C
REGISTER
IOUT
C
SDO
A1
AGND
C
CS
RFBD
CLK
EN
INPUT
REGISTER
DAC D
REGISTER
IOUT
D
DAC
A
B
C
D
AGND
D
2:4
Temperature range: −40°C to +125°C
Compact 28-lead SSOP and 32-lead LFCSP
AD5544
POWER-ON
RESET
DECODE
AGND
F
DGND
RS
MSB
LDAC
VSS
APPLICATIONS
Figure 1.
Automatic test equipment
Instrumentation
Digitally controlled calibration
The AD5544 is packaged in the compact 28-lead SSOP and 32-
lead LFCSP. The AD5554 is packed in the compact 28-lead SSOP.
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current output, digital-
to-analog converters (DACs) are designed to operate from a
2.7 V to 5.5 V supply range.
The EV-AD5544/45SDZ is available for evaluating DAC perfor-
mance. For more information, see the UG-285 evaluation board
user guide.
The applied external reference input voltage (VREFx) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
CS
(SDI), a chip select ( ), and clock (CLK) signals. In addition,
a serial data out pin (SDO) allows for daisy-chaining when multiple
packages are used. A common, level-sensitive, load DAC strobe
LDAC
(
) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
–0.1
–0.2
RS
The MSB pin allows system reset assertion ( ) to force all registers
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
to zero code when MSB = 0 or to half-scale code when MSB = 1.
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
Rev. G
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2000–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5544/AD5554
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converter (DAC) ....................................... 13
Serial Data Interface....................................................................... 15
Truth Tables................................................................................. 16
Power-On Reset.......................................................................... 17
ESD Protection Circuits ............................................................ 17
Power Supply Sequence ............................................................. 17
Layout and Power Supply Bypassing ....................................... 18
Grounding................................................................................... 18
Applications Information .............................................................. 19
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5544 Electrical Characteristics ............................................. 3
AD5554 Electrical Characteristics ............................................. 4
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
REVISION HISTORY
8/09—Rev. B to Rev. C
5/13—Rev. F to Rev. G
Change to Table 1 ..............................................................................3
Change to Table 2 ..............................................................................4
Changes to General Description Section ...................................... 1
Deleted Evaluation Board for the AD5544 Section and
Figure 30 to Figure 35; Renumbered Sequentially ..................... 22
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
8/09—Rev. A to Rev. B
Changes to Features Section ............................................................1
Changes to Figure 2...........................................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Moved Timing Diagram...................................................................5
Added Figure 4; Renumbered Sequentially ...................................5
Change to Table 3 ..............................................................................6
Changes to Table 4.............................................................................7
Changes to Typical Performance Characteristics Section ...........8
Changes to Figure 19...................................................................... 10
Moved Table 5, Table 6, and Table 7 ............................................ 12
Moved Truth Tables Section ......................................................... 13
Deleted Figure 27; Renumbered Sequentially ............................ 14
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide.......................................................... 16
1/12—Rev. E to Rev. F
Changes to Figure 1.......................................................................... 1
Added Figure 18; Renumbered Sequentially .............................. 11
Changes to Evaluation Board Schematics Section..................... 22
6/11—Rev. D to Rev. E
Added 32-Lead LFCSP.................................................. Throughout
Changes to Table 1, Supply Characteristics Parameters.............. 3
Changes to Table 2, Supply Characteristics Parameters.............. 5
Added Figure 6, Renumbered Subsequent Figures, Changes
to Table 4 ............................................................................................ 7
Changed Applications Section to Applications Information
Section, Added Reference Selection and Amplifier Selection
Sections ............................................................................................ 19
Added Evaluation Board for the AD5544 Section ..................... 21
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 18
12/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Electrical Characteristics Tables...................................4
Change to Pin Description Table ................................................. 10
Addition of Power Supply Sequence Section.............................. 19
Addition of Layout and Power Supply Bypassing Section ........ 19
Addition of Grounding Section.................................................... 19
Addition of Figure 32..................................................................... 19
9/09—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 12........................................................................ 9
Changes to Figure 19...................................................................... 10
Changes to Table 8 and Table 9..................................................... 13
Changes to Ordering Guide .......................................................... 16
4/00—Revision 0: Initial Version
Rev. G | Page 2 of 24
Data Sheet
AD5544/AD5554
SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, V REFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Condition/Comments
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
Relative Accuracy
N
INL
1 LSB = VREFx/216 = 153 µV when VREF = 10 V
AD5544BRSZ
16
1
2
1
4
1
1.5
1
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
nA
AD5544ARSZ
AD5544BCPZ
AD5544ACPZ-1
Differential Nonlinearity
DNL
AD5544BRSZ
AD5544ARSZ
AD5544BCPZ
AD5544ACPZ-1
1
Output Leakage Current
IOUT
x
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = 85°C
Data = 0xFFFF
10
20
3
nA
mV
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
GFSE
TCVFS
RFBx
0.75
1
6
ppm/°C
kΩ
VDD = 5 V
4
8
REFERENCE INPUT
VREFx Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
VREF
x
−15
4
+15
8
V
kΩ
%
RREF
RREF
x
x
6
0.35
5
Channel-to-channel
CREF
x
pF
Output Current
IOUT
COUT
x
x
Data = 0xFFFF
Code dependent
1.25
2.4
4
2.5
0.8
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
35
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
V
tCH
tCL
tCSS
tCSH
tPD
25
25
0
ns
ns
ns
ns
ns
Clock Width Low
CS to Clock Setup
Clock to CS Hold
25
2
Clock to SDO Propagation
Delay
20
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
tLDAC
tDS
tDH
tLDS
tLDH
25
20
20
5
ns
ns
ns
ns
ns
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
VDD RANGE
IDD
ISS
2.7
5.5
5
9
V
µA
µA
Logic inputs = 0 V
Logic inputs = 0 V, VSS = −5 V
0.001
Rev. G | Page 3 of 24
AD5544/AD5554
Data Sheet
Parameter
Symbol
PDISS
PSS
Test Condition/Comments
Min Typ
Max
1.25
0.006
Unit
mW
%/%
Power Dissipation
Logic inputs = 0 V
Power Supply Sensitivity
AC CHARACTERISTICS4
Output Voltage Settling Time
Reference Multiplying
Bandwidth (BW)
∆VDD
=
5%
tS
To 0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000
VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF,
0.9
12
µs
MHz
BW − 3 dB
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
Q
VREFx = 8 V, data = 0x0000 to 0x8000 to 0x0000
Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz
Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
−1
−65
−90
nV-sec
dB
dB
VOUTx/VREF
VOUTA/VREF
x
B
Digital Feedthrough
Q
CS = 1, fCLK = 1 MHz
0.6
−98
7
nV-sec
dB
nV/√Hz
Total Harmonic Distortion
Output Spot Noise Voltage
THD
eN
VREFx = 5 V p-p, data = 0xFFFF, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1 All static performance tests (except IOUTx) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier.
AD5554 ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, V SS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, V REFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Condition/Comments
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
N
1 LSB = VREFx/214 = 610 µV when VREFx = 10 V
14
0.5
1
10
20
10
Bits
LSB
LSB
nA
nA
mV
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
INL
DNL
IOUT
x
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = 85°C
Data = 0x3FFF
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
GFSE
TCVFS
RFBx
2
1
6
ppm/°C
kΩ
VDD = 5 V
4
8
REFERENCE INPUT
VREFx Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
VREF
x
−15
4
+15
8
V
kΩ
%
RREF
RREF
x
x
6
1
5
Channel-to-channel
CREF
x
pF
Output Current
IOUT
COUT
x
x
Data = 0x3FFF
Code dependent
1.25
2.4
4
2.5
0.8
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
80
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
V
tCH
tCL
tCSS
tCSH
25
25
0
ns
ns
ns
ns
Clock Width Low
CS to Clock Setup
Clock to CS Hold
25
Rev. G | Page 4 of 24
Data Sheet
AD5544/AD5554
Parameter
Symbol
Test Condition/Comments
Min Typ
Max
Unit
Clock to SDO Propagation
Delay
tPD
2
20
ns
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
tLDAC
tDS
tDH
tLDS
tLDH
25
20
20
5
ns
ns
ns
ns
ns
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
AC CHARACTERISTICS4
Output Voltage Settling Time
VDD RANGE
IDD
ISS
PDISS
PSS
2.7
5.5
5
9
1.25
0.006
V
µA
µA
mW
%/%
Logic inputs = 0 V
Logic inputs = 0 V, VSS = −5 V
Logic inputs = 0 V
0.001
∆VDD
= 5%
tS
To 0.1% of full scale, data = 0x0000 to 0x3FFF to 0x0000
VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF
0.9
12
µs
MHz
Reference Multiplying
Bandwidth (BW)
BW − 3 dB
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
Q
VREFx = 8 V, data = 0x0000 to 0x2000 to 0x0000
Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz
Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
−1
−65
−90
nV-sec
dB
dB
VOUTx/VREF
VOUTA/VREF
x
B
Digital Feedthrough
Q
CS = 1, fCLK = 1 MHz
0.6
−98
7
nV-sec
dB
nV/√Hz
Total Harmonic Distortion
Output Spot Noise Voltage
THD
eN
VREFx = 5 V p-p, data = 0x3FFF, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier,.
Rev. G | Page 5 of 24
AD5544/AD5554
Data Sheet
TIMING DIAGRAMS
SDI
A1
A0
D15 D14 D13 D12
D11 D10
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 3. AD5544 Timing Diagram
SDI
A1
A0
D13 D12 D11 D10 D09 D08
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 4. AD5554 Timing Diagram
Rev. G | Page 6 of 24
Data Sheet
AD5544/AD5554
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Parameter
Rating
VDD to GND
VSS to GND
VREFx to GND
Logic Input and Output to GND
V(IOUTx) to GND
−0.3 V, +8 V
+0.3 V, −7 V
−18 V, +18 V
−0.3 V, +8 V
−0.3 V, VDD + 0.3 V
−0.3 V, +0.3 V
50 mA
(TJ max − TA)/θJA
θJA
100°C/W
AGNDx to DGND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance
28-Lead SSOP
ESD CAUTION
32-Lead LFCSP
32.5°C/W
Maximum Junction Temperature (TJ Max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
150°C
−40°C to +125°C
−65°C to +150°C
Vapor Phase, 60 Sec
Infrared, 15 Sec
215°C
220°C
Rev. G | Page 7 of 24
AD5544/AD5554
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
A
A
A
GND
A
D
GND
2
I
OUT
I
D
OUT
3
V
REF
V
D
REF
A
I
V
A
A
A
A
MSB
RS
1
2
3
4
5
6
7
8
24 DGND
4
R
R
D
GND
FB
FB
23
22
21
20
19
18
17
V
SS
GND
LDAC
SDO
NC
OUT
5
MSB
RS
DGND
A
F
REF
AD5544
TOP VIEW
(Not to Scale)
R
6
V
FB
SS
AD5544/
AD5554
TOP VIEW
(Not to Scale)
7
V
A
F
DD
GND
V
8
CS
CLK
SDI
DD
R
C
LDAC
SDO
FB
CS
V
C
REF
9
10
11
12
13
14
NC
R
B
B
B
B
FB
R
C
FB
V
REF
OUT
GND
V
C
REF
I
I
C
OUT
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO AGND.
A
A
C
GND
NC = NO CONNECT
Figure 6. LFCSP Pin Configuration
Figure 5. TSSOP Pin Configuration
Table 4. Pin Function Descriptions
LFCSP
Pin No.
TSSOP
Pin No.
Mnemonic
Description
1
2
3
1
2
3
AGND
A
DAC A Analog Ground.
DAC A Current Output.
IOUT
A
VREF
A
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be
tied to the VDD pin.
4
5
6
4
5
6
RFBA
MSB
RS
Establish the voltage output for DAC A by connecting to an external amplifier output.
MSB Bit. Set pin during a reset pulse (RS) or at system power-on if tied to ground or VDD
.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code
(0x8000 for the AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin.
Register data = 0x0000 when MSB = 0.
7
8
7
8
VDD
CS
Positive Power Supply Input. Specified range of operation: 5 V 10ꢀ.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data
to the input register when CS/LDAC returns high. Does not affect LDAC operation.
9
9
CLK
SDI
RFBB
Clock Input. Positive edge clocks data into the shift register.
Serial Data Input. Input data loads directly into the shift register.
Establish the voltage output for DAC B by connecting to an external amplifier output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be
tied to the VDD pin.
10
11
12
10
11
12
VREF
B
13
14
15
16
17
13
14
15
16
17
IOUT
AGND
AGND
IOUT
B
B
C
C
C
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
VREF
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be
tied to the VDD pin.
18
19
20
18
19
20
RFBC
NC
SDO
Establish the voltage output for DAC C by connecting to an external amplifier output.
No Connect. Leave the pin unconnected.
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock
pulses for the AD5544 and 17 clock pulses for the AD5554 after input at the SDI pin.
21
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 8 and Table 9 for operation.
22
23
24
25
22
23
24
25
AGND
VSS
DGND
RFBD
F
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
Digital Ground Pin.
Establish the voltage output for DAC D by connecting to an external amplifier output.
Rev. G | Page 8 of 24
Data Sheet
AD5544/AD5554
LFCSP
Pin No.
26
TSSOP
Pin No.
Mnemonic
VREF
Description
26
D
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be
tied to the VDD pin.
27
28
27
28
29
30
31
32
33
IOUT
D
D
DAC D Current Output.
DAC D Analog Ground.
Do not connect.
Do not connect.
Do not connect.
AGND
NC
NC
NC
NC
N/A
N/A
N/A
N/A
N/A
Do not connect.
Connect the exposed pad to AGNDx.
EPAD
Rev. G | Page 9 of 24
AD5544/AD5554
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
1.5
1.0
V
V
= 5V
REF
DD
0x0FFF
0x7FFF
= 10V
0.05
0
0xF000
0x8000
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
0.5
0
–0.5
–1.0
–1.5
–2000 –1500 –1000 –500
0
500
1000
1500
2000
0
0
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
OFFSET VOLTAGE (µV)
Figure 7. AD5544 DNL vs. Code, TA = 25°C
Figure 10. AD5544 Integral Nonlinearity Error vs. Op Amp Offset
0.20
0.15
0.10
0.05
0
1.00
V
V
= 5V
REF
DD
= 10V
0.75
0.50
0.25
0
0x0FFF
0xF000
0x8000
–0.05
–0.10
–0.15
–0.20
–0.25
–0.50
–0.75
–1.00
–1000 –750
–500
–250
0
250
500
750
1000
2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000
CODE
OP AMP OFFSET (µV)
Figure 8. AD5554 INL vs. Code, TA = 25°C
Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset
0.10
0.05
0
10
V
V
= 5V
REF
DD
= 10V
5
0
–5
–0.05
–0.10
–0.15
–10
–15
–20
–1500
–1000
–500
0
500
1000
1500
2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000
CODE
OP AMP OFFSET (µV)
Figure 9. AD5554 DNL vs. Code, TA = 25°C
Figure 12. AD5544 Gain Error vs. Op Amp Offset
Rev. G | Page 10 of 24
Data Sheet
AD5544/AD5554
10,000
1000
100
10
–3.88
–3.90
–3.92
–3.94
–3.96
–3.98
–4.00
–4.02
–4.04
–4.06
–4.08
ZERO SCALE
MIDSCALE
FULL SCALE
0x5555
1
1k
10k
100k
1M
10M
100M
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
CLOCK FREQUENCY (Hz)
TIME (µs)
Figure 13. AD5544 Midscale Transition
Figure 16. AD5544 Power Supply Current vs. Clock Frequency
100
V
V
= 5V
REF
DD
V
V
= 5V
REF
DD
= 10V
= 10V
90
80
70
60
50
40
30
20
10
0
V
OUT
LDAC
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. AD5544 Large Signal Settling Time
Figure 17. AD5544/AD5554 Power Supply Rejection vs. Frequency
0.1
4
0
20
0
–20
0
–4
–40
–60
–8
–80
–0.1
–0.2
–12
–16
–20
–100
–120
–140
–160
–2
0
2
4
6
8
10
0
5k
10k
15k
20k
25k
FREQUENCY (Hz)
TIME (µs)
Figure 18. AD5544/AD5554 Analog THD
Figure 15. AD5544 Small Signal Settling Time
Rev. G | Page 11 of 24
AD5544/AD5554
Data Sheet
300
250
200
150
100
50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOGIC INPUT (V)
Figure 19. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage
Rev. G | Page 12 of 24
Data Sheet
AD5544/AD5554
THEORY OF OPERATION
The AD5544 and the AD5554 contain four 16-bit and 14-bit,
current output DACs, respectively. Each DAC has its own inde-
pendent multiplying reference input. Both the AD5544 and the
AD5554 use a 3-wire, SPI-compatible serial data interface, with
These DACs are also designed to accommodate ac reference input
signals. Both the AD5544 and the AD5554 accommodate input
reference voltages in the range of −15 V to +15 V. The reference
voltage inputs exhibit a constant nominal input resistance of 5 kΩ
RS
30%. On the other hand, the IOUTA, IOUTB, IOUTC, and IOUTD
a configurable asynchronous
pin for half-scale (MSB = 1) or
LDAC
DAC outputs are code dependent and produce various output
resistances and capacitances. The choice of external amplifier
should take into account the variation in impedance generated by
the AD5544/AD5554 on the inverting input node of the amplifier.
The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications,
an external feedback compensation capacitor, CFB, may be needed
to provide a critically damped output response for step changes in
reference input voltages. Figure 21 shows the gain vs. frequency
performance at various attenuation settings using a 23 pF external
feedback capacitor connected across the IOUTx and RFBx terminals
for the AD5544 and the AD5554, respectively. To maintain good
analog performance, power supply bypassing of 0.01 μF, in parallel
with 1 μF, is recommended. Under these conditions, a clean power
supply with low ripple voltage capability should be used. Switching
power supplies is usually not suitable for this application due to
the higher ripple voltage and PSS frequency-dependent charac-
teristics. It is best to derive the supply of the AD5544/AD5554
from system analog supply voltages. Do not use the digital
supply (see Figure 22).
zero-scale (MSB = 0) preset. In addition, an
4-channel, simultaneous updates for hardware synchronized
output voltage changes.
strobe enables
DIGITAL-TO-ANALOG CONVERTER (DAC)
Each part contains four current-steering R-R ladder DACs.
Figure 20 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The RFBx pin connects to the output of the
external amplifier. The IOUTx terminal connects to the inverting
input of the external amplifier. The AGNDx pin should be Kelvin-
connected to the load point, requiring full 16-bit accuracy. These
DACs are designed to operate with both negative and positive
reference voltage.
The VDD power pin is used only by the logic to drive the DAC
switches on and off. Note that a matching switch is used in series
with the internal 5 kΩ feedback resistor. If users attempt to
measure the value of RFB, power must be applied to VDD to achieve
continuity. An additional VSS bias pin is used to guard the substrate
during high temperature applications, minimizing zero-scale
leakage currents that double every 10°C. The DAC output
voltage is determined by VREF and the digital data (D) in the
following equations:
2
0
–2
–4
–6
–8
D
(1)
VOUT VREF
VOUT VREF
for the AD5544
65,536
D
(2)
for the AD5554
16,384
Note that the output polarity is opposite the VREF polarity for dc
reference voltages.
V
DD
R
R
R
R
X
V
X
FB
REF
100k
1M
10M
FREQUENCY (Hz)
100M
2R
2R
2R
R
5kΩ
Figure 21. AD5554 Reference Multiplying Bandwidth vs. Code
S2
S1
I
X
OUT
A
F
GND
A
X
GND
FROM OTHER DACS A
GND
V
DGND
SS
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, AND V MUST BE POWERED.
DD
Figure 20. Typical Equivalent DAC Channel
Rev. G | Page 13 of 24
AD5544/AD5554
Data Sheet
15V
ANALOG
POWER
SUPPLY
2R
R
5V
+
V
DD
AD5544
R
FB
X
RR
R
V
X
REF
2R
2R
2R
R
5kΩ
15V
S2
S1
V
I
X
CC
OUT
V
A
F
OUT
GND
A1
A
X
GND
+
V
EE
LOAD
FROM OTHER DACS A
GND
DGND
V
SS
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
AND V MUST BE POWERED.
DD
Figure 22. Recommended Kelvin-Sensed Hookup
Rev. G | Page 14 of 24
Data Sheet
AD5544/AD5554
SERIAL DATA INTERFACE
Similarly, two right-justified data bytes can be written to the
CS
The AD5544/AD5554 use a 3-wire ( , SDI, CLK), SPI-compatible
CS
AD5554. Keeping the
line low between the first and second
serial data interface. Serial data of the AD5544/AD5554 is clocked
into the serial input register in an 18-bit and 16-bit data-word
format, respectively. The MSB bits are loaded first. Table 5 defines
the 18 data-word bits for the AD5544, and Table 6 defines the
16 data-word bits for the AD5554. Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK,
subject to the data setup and data hold time requirements specified
in the interface timing specifications (see Table 1 and Table 2).
byte transfer results in a successful serial register update.
When the data is properly aligned in the shift register, the posi-
CS
tive edge of the
initiates the transfer of new data to the target
DAC register, determined by the decoding of Address Bit A1
and Address Bit A0. For the AD5544, Table 5, Table 7, Table 8,
and Figure 3 define the characteristics of the software serial
interface.
CS
Data can be clocked in only while the
low. For the AD5544, only the last 18 bits clocked into the serial
CS
chip select pin is active
For the AD5554, Table 6, Table 7, Table 9, and Figure 4 define
the characteristics of the software serial interface. Figure 23 and
Figure 24 show the equivalent logic interface for the key digital
control pins for the AD5544. The AD5554 has a similar configu-
register are interrogated when the
pin returns to the logic high
state; extra data bits are ignored. For the AD5554, only the last
16 bits clocked into the serial register are interrogated when the
RS
ration, except that it has 14 data bits. Two additional pins, and
CS
MSB, provide hardware control over the preset function and
pin returns to the logic high state. Because most microcon-
trollers output serial data in 8-bit bytes, three right-justified data
CS
RS
DAC register loading. If these functions are not needed, the
RS
pin
bytes can be written to the AD5544. Keeping the
line low
pin can be tied to logic high. The asynchronous input
between the first, second, and third byte transfers results in a
successful serial register update.
forces all input and the DAC registers to either the zero-code
state (MSB = 0) or the half-scale state (MSB = 1).
Table 5. AD5544 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format)1
MSB
LSB
B0
B17
A1
B16
A0
B15
D15
B14
D14
B13
D13
B12
D12
B11
D11
B10
D10
B9
B8
B7
B6
B5
B4
B3
B2
B1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
CS
Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the line returns to logic high. At this point, an
internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.
LDAC
Any extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the
tied logic low to disable the DAC registers.
pin can be
Table 6. AD5554 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format)1
MSB
LSB
B0
B15
A1
B14
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
B8
B7
B6
B5
B4
B3
B2
B1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
CS
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the line returns to logic high. At this point, an
internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0.
LDAC
Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the
tied logic low to disable the DAC registers.
pin can be
Table 7. Address Decode
A1
A0
0
DAC Decoded
DAC A
0
0
1
DAC B
1
0
DAC C
1
1
DAC D
Rev. G | Page 15 of 24
AD5544/AD5554
Data Sheet
TRUTH TABLES
Table 8. AD55441 Control Logic Truth Table
CS
LDAC
High
High
High
RS
CLK
X
Low
MSB2 Serial Shift Register Function3
Input Register Function
Latched
Latched
DAC Register
High
Low
Low
High
High
High
X
X
X
No effect
No effect
Latched
Latched
Latched
￪+3
Shift register data advanced one bit Latched
Low
￪+3
High
Low
High
High
High
High
X
X
No effect
No effect
Latched
Latched
Latched
Selected DAC updated with
current shift register contents4
High
High
High
X
X
X
Low
High
￪+3
High
High
High
X
X
X
No effect
No effect
No effect
Latched
Latched
Latched
Transparent
Latched
Latched
High
High
X
X
High
High
Low
Low
0
High
No effect
No effect
Latched data = 0x0000
Latched data = 0x8000
Latched data = 0x0000
Latched data = 0x8000
1 For the AD5544, data appears at the SDO pin 19 clock pulses after input at the SDI pin.
2 X = don’t care.
3
￪ +is a positive logic transition.
4 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 9. AD55541 Control Logic Truth Table
CLK
MSB2 Serial Shift Register Function3
Input Register Function3
DAC Register
CS
LDAC RS
High
Low
Low
X
L
￪+3
High
High
High
High
High
High
X
X
X
No effect
No effect
Latched
Latched
Latched
Latched
Latched
Shift register data advanced one bit Latched
Low
￪+3
High
Low
High
High
High
High
X
X
No effect
No effect
Latched
Latched
Latched
Selected DAC updated with
current shift register contents4
High
High
High
X
X
X
Low
High
￪+3
High
High
High
X
X
X
No effect
No effect
No effect
Latched
Latched
Latched
Transparent
Latched
Latched
High
High
X
X
High
High
Low
Low
0
High
No effect
No effect
Latched data = 0x0000
Latched data = 0x2000
Latched data = 0x0000
Latched data = 0x2000
1 For the AD5554, data appears at the SDO pin 17 clock pulses after input at the SDI pin.
2 X = don’t care.
3
￪ +is a positive logic transition.
4 At power-on, both the input register and the DAC register are loaded with all 0s.
Rev. G | Page 16 of 24
Data Sheet
AD5544/AD5554
V
A B C D
REF
CS
EN
AD5544
V
DD
CLK
R
I
A
FB
SDI
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
DAC A
REGISTER
INPUT
REGISTER
A
DAC A
OUT
R
R
R
R
R
A
A
GND
D9
D10
D11
D12
D13
D14
D15
A0
R B
FB
INPUT
REGISTER
DAC B
REGISTER
I
B
DAC B
OUT
R
R
R
A
B
DAC A
GND
SDO
B
C
D
A1
2:4
DECODE
R
I
C
FB
INPUT
REGISTER
DAC C
REGISTER
C
DAC C
OUT
A
C
GND
R
I
D
FB
INPUT
REGISTER
DAC D
REGISTER
D
DAC D
OUT
A
D
GND
SET
MSB
SET
MSB
A
F
POWER-
ON
GND
RESET
DGND
MSB
V
RS
LDAC
SS
Figure 23. System Level Digital Interfacing
TO INPUT REGISTER
ESD PROTECTION CIRCUITS
A
B
C
D
All logic input pins contain back-biased ESD protection Zener
diodes that are connected to ground (DGND) and VDD, as
shown in Figure 25.
ADDRESS
DECODER
CS
EN
V
DD
SHIFT REGISTER
CLK
SDI
5kΩ
DIGITAL
TH
TH
CLOCK
INPUTS
19 /17
SDO
DGND
Figure 24. AD5544/AD5554 Equivalent Logic Interface
Figure 25. Equivalent ESD Production Circuits
POWER-ON RESET
POWER SUPPLY SEQUENCE
When the VDD power supply is turned on, an internal reset strobe
forces all the input and DAC registers to the zero-code state or
half-scale state, depending on the MSB pin voltage. The VDD power
supply should have a smooth positive ramp without drooping to
have consistent results, especially in the region of VDD = 1.5 V to
2.3 V. The VSS supply has no effect on the power-on reset perform-
ance. The DAC register data stays at a zero-scale or half-scale
setting until a valid serial register data load takes place.
As standard practice, it is recommended that VDD, VSS, and ground
be powered up prior to any reference. The ideal power-up sequence
is as follows: AGNDx, DGND, VDD, VSS, VREFx, and the digital inputs.
A noncompliance power-up sequence may elevate the reference
current, but the devices resume normal operation once VDD and
V
SS are powered up.
Rev. G | Page 17 of 24
AD5544/AD5554
Data Sheet
AD5544/AD5554
LAYOUT AND POWER SUPPLY BYPASSING
V
V
DD
DD
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
+
C3
10µF
C1
0.1µF
A
X
GND
C4
10µF
C2
0.1µF
V
V
SS
SS
DGND
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capaci-
tors should also be applied at VDD to minimize any transient
disturbance and filter any low frequency ripple (see Figure 26).
Users should not apply switching regulators for VDD due to the
power supply rejection ratio (PSRR) degradation over frequency.
Figure 26. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5544/AD5554 serve as
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 26).
Rev. G | Page 18 of 24
Data Sheet
AD5544/AD5554
REFERENCE SELECTION
APPLICATIONS INFORMATION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
The AD5544/AD5554 are, inherently, two-quadrant multiplying
DACs. That is, they can be easily set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
four-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external ampli-
fier (A2) configured as a summing amplifier (see Figure 27).
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
10kΩ
10kΩ
10V
5kΩ
V
REF
A2
V
OUT
AD588
–10V <
V
OUT
< +10V
V
DD
V
X
R
X
REF
FB
I
X
OUT
ONE CHANNEL
AD5544
A1
V
A
F
SS
GND
A
X
GND
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Figure 27. Four-Quadrant Multiplying Application Circuit
In this circuit, the first and second amplifiers (A1 and A2)
provide a total gain of 2, which increases the output voltage span
to 20 V. Biasing the external amplifier with a 10 V offset from
the reference voltage results in a full four-quadrant multiplying
circuit. The transfer equation of this circuit shows that both
negative and positive output voltages are created as the input
data (D) is incremented from code zero (VOUT = −10 V) to
midscale (VOUT = 0 V) to full scale (VOUT = 10 V).
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
D
(3)
(4)
VOUT
− 1 × − V
(
for the AD5544
)
REF
32,768
D
8192
− 1 × − V
VOUT
(
for the AD5554
)
REF
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
Rev. G | Page 19 of 24
AD5544/AD5554
Data Sheet
Table 10. Suitable Analog Devices Precision References
Maximum Temperature
Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C)
ISS (mA) Output Noise (μV p-p) Package(s)
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR420
ADR421
ADR423
ADR425
ADR431
ADR435
ADR391
ADR395
10
10
5.0
5.0
2.5
2.5
3.0
3.0
2.048
2.50
3.00
5.00
2.500
5.000
2.5
0.05
0.05
0.06
0.06
0.1
0.1
0.1
0.1
0.05
0.04
0.04
0.04
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
3
3
3
3
9
9
1
1
1
1
1
1
1
1
0.5
0.5
0.5
0.5
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
TSOT-5
6
10
10
1.75
1.75
2
3.4
3.5
8
5
8
5.0
TSOT-5
Table 11. Suitable Analog Devices Precision Op Amps
OS Maximum
Supply Voltage (V) (μV)
V
IB Maximum
(nA)
0.1 Hz to 10 Hz
Noise (μV p-p)
Supply
Current (μA)
Part No.
OP97
Package(s)
2 ꢀo 20
2.5 ꢀo 15
5 ꢀo 18
5 ꢀo 15
5 ꢀo 15
1.8 ꢀo 5
25
60
75
75
125
50
50
65
65
65
0.1
2
2
12
0.5
0.4
0.1
0.077
0.1
2.3
2.3
2.3
2.4
2.4
600
500
2300
3000
2000
40
SOIC-8, PDIP-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
SOIC-8, SOT-23-5
TSOT-5
MSOP-8, SOIC-8
WLCSP-5, SOT-23-5
TSOT-5
OP1177
AD8675
AD8671
ADA4004-1
AD8603
AD8607
AD8605
AD8615
AD8616
90
0.001
0.001
0.001
0.001
0.001
1.8 ꢀo 5
2.7 ꢀo 5
40
1000
2000
2000
2.7 ꢀo 5
2.7 ꢀo 5
MSOP-8, SOIC-8
Table 12. Suitable Analog Devices High Speed Op Amps
Slew Rate
Supply Voltage (V) BW at ACL (MHz) (V/μs)
Part No.
AD8065
AD8066
AD8021
AD8038
ADA4899-1
AD8057
AD8058
AD8061
AD8062
AD9631
VOS (Max) (μV)
1500
1500
1000
3000
35
5000
5000,
6000
6000
IB (Max) (nA)
0.006
0.006
10,500
750
100
500
500
350
Package(s)
5 ꢀo 24
5 ꢀo 24
5 ꢀo 24
3 ꢀo 12
5 ꢀo 12
3 ꢀo 12
3 ꢀo 12
2.7 ꢀo 8
2.7 ꢀo 8
3 ꢀo 6
145
145
490
350
600
325
325
320
320
320
180
180
120
425
310
1000
850
650
650
1300
SOIC-8, SOT-23-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, SC70-5
LFCSP-8, SOIC-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOIC-8, PDIP-8
350
7000
10,000
Rev. G | Page 20 of 24
Data Sheet
AD5544/AD5554
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
8.20
7.80
7.40
1
14
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
SEATING
PLANE
COPLANARITY
0.10
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-150-AH
Figure 28. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
24
32
1
0.50
BSC
3.65
3.50 SQ
3.45
EXPOSED
PAD
8
9
17
16
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 29. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-11)
Dimensions shown in millimeters
Rev. G | Page 21 of 24
AD5544/AD5554
Data Sheet
ORDERING GUIDE
Temperature
RES Bit INL LSB DNL LSB Range
Package
Option
Model1
Package Description
AD5544ARS
AD5544ARSZ
AD5544ARSZ-REEL7
AD5544BRSZ
AD5544BRSZ-REEL7
AD5544ACPZ-1-R2
AD5544ACPZ-1-RL7
AD5544BCPZ-R2
AD5544BCPZ-RL7
AD5554BRSZ
16
2
2
2
1
1
4
4
1
1.5
1.5
1.5
1
1
1
1
1
1
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
RS-28
RS-28
RS-28
RS-28
16
16
16
16
16
16
16
16
14
RS-28
CP-32-11
CP-32-11
CP-32-11
CP-32-11
RS-28
1
0.5
1
28-Lead Shrink Small Outline Package [SSOP]
Evaluation Board
EV-AD5544/45SDZ
1 Z = RoHS Compliant Part.
Rev. G | Page 22 of 24
Data Sheet
NOTES
AD5544/AD5554
Rev. G | Page 23 of 24
AD5544/AD5554
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2000–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00943-0-5/13(G)
Rev. G | Page 24 of 24
相关型号：
AD5544LRS
IC QUAD, SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO28, SSOP-28, Digital to Analog Converter
ADI
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