AD5544SRS-EP [ADI]
Quad, Current-Output, Serial-Input 16-/14-Bit DACs;
| 型号： | AD5544SRS-EP |
| 厂家： | 
ADI |
| 描述： | Quad, Current-Output, Serial-Input 16-/14-Bit DACs 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Current-Output,
Serial-Input 16-Bit DAC
Enhanced Product
AD5544-EP
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2 mA full-scale current 20%, with VREF
0.9 µs settling time to 0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
= 10 V
V
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
R
I
A
A
FB
SDO
INPUT
REGISTER
DAC A
REGISTER
DAC A
OUT
R
R
R
R
R
R
R
R
Midscale or zero-scale reset
A
A
GND
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
R
B
FB
INPUT
REGISTER
DAC B
REGISTER
16
D9
I
B
DAC B
DAC C
OUT
D10
D11
D12
D13
D14
D15
A0
A
B
GND
R
I
C
C
FB
INPUT
REGISTER
DAC C
REGISTER
OUT
SDI
A1
Compact 28-lead SSOP
A
C
GND
CS
R
I
D
FB
CLK
EN
ENHANCED PRODUCT FEATURES
INPUT
REGISTER
DAC D
REGISTER
D
DAC D
OUT
DAC
A
B
C
D
A
D
Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
1 assembly/test site
GND
2:4
AD5544-EP
POWER-ON
RESET
DECODE
A
F
GND
DGND
RS
MSB
LDAC
V
SS
1 fabrication site
Figure 1.
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
GENERAL DESCRIPTION
packages are used. A common, level-sensitive, load DAC strobe
LDAC
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
The AD5544-EP quad, 16-bit, current output, digital-to-analog
converter (DAC) is designed to operate from a 2.7 V to
5.5 V supply range.
(
) input allows the simultaneous update of all DAC outputs
The applied external reference input voltage (VREFx) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
RS
The MSB pin allows system reset assertion ( ) to force all registers
to zero code when MSB = 0 or to half-scale code when MSB = 1.
The AD5544-EP is packaged in the compact 28-lead SSOP.
Additional application and technical information can be found
in the AD5544 data sheet.
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
CS
(SDI), a chip select ( ), and clock (CLK) signals. In addition, a
serial data out pin (SDO) allows for daisy chaining when multiple
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD5544-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................8
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Enhanced Product
SPECIFICATIONS
AD5544-EP
VDD = 2.7 V to 5.5 V, VSS = 0 V, IOUTx = virtual GND, AGNDx = 0 V, V REFA = VREFB = VREFC = VREFD = 10 V, TA = full operating temperature
range of −55°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Condition/Comments
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
N
INL
DNL
1 LSB = VREFx/216 = 153 µV when VREF = 10 V
16
1.5
1.5
10
20
4
Bits
LSB
LSB
nA
nA
mV
IOUT
x
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = 85°C
Data = 0xFFFF
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
GFSE
TCVFS
RFBx
0.75
1
6
ppm/°C
kΩ
VDD = 5 V
4
8
REFERENCE INPUT
VREFx Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
VREF
x
−15
4
+15
8
V
kΩ
%
RREF
RREF
x
x
6
0.35
5
Channel-to-channel
CREF
x
pF
Output Current
IOUT
COUT
x
x
Data = 0xFFFF
Code dependent
1.25
2.4
4
2.5
0.8
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
35
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
V
tCH
tCL
tCSS
tCSH
tPD
25
25
0
ns
ns
ns
ns
ns
Clock Width Low
CS to Clock Setup
Clock to CS Hold
25
2
Clock to SDO Propagation
Delay
20
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
Load Hold
tLDAC
tDS
tDH
tLDS
tLDH
25
20
20
5
ns
ns
ns
ns
ns
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
ISS
PDISS
PSS
2.7
5.5
5
9
1.25
0.006
V
µA
µA
mW
%/%
Logic inputs = 0 V
Logic inputs = 0 V, VSS = −5 V
Logic inputs = 0 V
0.001
∆VDD
= 5%
Rev. 0 | Page 3 of 12
AD5544-EP
Enhanced Product
Parameter
Symbol
Test Condition/Comments
Min Typ
Max
Unit
AC CHARACTERISTICS4
Output Voltage Settling Time
Reference Multiplying
Bandwidth (BW)
tS
To 0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000
VREFx = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF,
0.9
12
µs
MHz
BW − 3 dB
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
Q
VREFx = 8 V, data = 0x0000 to 0x8000 to 0x0000
Data = 0x0000, VREFx = 100 mV rms, f = 100 kHz
Data = 0x0000, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
−1
−65
−90
nV-sec
dB
dB
VOUTx/VREF
VOUTA/VREF
x
B
Digital Feedthrough
Q
CS = 1, fCLK = 1 MHz
0.6
−98
7
nV-sec
dB
nV/√Hz
Total Harmonic Distortion
Output Spot Noise Voltage
THD
eN
VREFx = 5 V p-p, data = 0xFFFF, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1 All static performance tests (except IOUTx) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier.
TIMING DIAGRAMS
SDI
A1
A0 D15 D14 D13 D12 D11 D10
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 12
Enhanced Product
AD5544-EP
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Parameter
Rating
VDD to GND
VSS to GND
VREFx to GND
Logic Input and Output to GND
V(IOUTx) to GND
−0.3 V, +8 V
+0.3 V, −7 V
−18 V, +18 V
−0.3 V, +8 V
−0.3 V, VDD + 0.3 V
−0.3 V, +0.3 V
50 mA
(TJ max − TA)/θJA
θJA
100°C/W
AGNDx to DGND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance
28-Lead SSOP
ESD CAUTION
32-Lead LFCSP
32.5°C/W
Maximum Junction Temperature (TJ Max)
150°C
Operating Temperature Range, Enhanced
Product (EP Version)
−55°C to +125°C
Storage Temperature Range
Lead Temperature
−65°C to +150°C
Vapor Phase, 60 Sec
Infrared, 15 Sec
215°C
220°C
Rev. 0 | Page 5 of 12
AD5544-EP
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
A
A
A
GND
A
D
GND
I
OUT
I
D
OUT
3
V
REF
V
D
REF
4
R
R
D
FB
FB
5
MSB
RS
DGND
6
V
SS
AD5544-EP
7
V
A
F
DD
GND
8
CS
CLK
SDI
TOP VIEW
(Not to Scale)
LDAC
SDO
9
10
11
12
13
14
NC
R
B
B
B
B
FB
R
C
FB
V
REF
OUT
GND
V
C
REF
I
I
C
OUT
A
A
C
GND
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
AGND
A
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be tied to the
DD pin.
IOUT
A
VREFA
V
4
5
6
RFBA
MSB
RS
Establish the voltage output for DAC A by connecting to an external amplifier output.
MSB Pin. Set pin during a reset pulse (RS) or at system power-on if tied to ground or VDD
.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code, determined by
the voltage on the MSB pin. Register data = 0x0000 when MSB = 0.
7
8
VDD
CS
Positive Power Supply Input. Specified range of operation: 5 V 10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the
input register when CS/LDAC returns high. Does not affect LDAC operation.
9
CLK
SDI
RFBB
Clock Input. Positive edge clocks data into the shift register.
Serial Data Input. Input data loads directly into the shift register.
Establish the voltage output for DAC B by connecting to an external amplifier output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be tied to the
10
11
12
VREFB
V
DD pin.
13
14
15
16
17
IOUT
AGND
AGND
B
B
C
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
IOUTC
VREF
C
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be tied to the
V
DD pin.
18
19
20
RFBC
NC
SDO
Establish the voltage output for DAC C by connecting to an external amplifier output.
No Connect. Do not connect to this pin.
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for
the AD5544-EP after input at the SDI pin.
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers.
Asynchronous active low input.
22
23
24
25
AGND
VSS
DGND
RFBD
F
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
Digital Ground Pin.
Establish the voltage output for DAC D by connecting to an external amplifier output.
Rev. 0 | Page 6 of 12
Enhanced Product
AD5544-EP
Pin No.
Mnemonic Description
26
VREFD
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be tied to the
VDD pin.
27
28
IOUT
AGND
D
D
DAC D Current Output.
DAC D Analog Ground.
Rev. 0 | Page 7 of 12
AD5544-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
10
5
V
V
= 5V
REF
DD
= 10V
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
0
–5
–10
–15
–20
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
–1500
–1000
–500
0
500
1000
1500
OP AMP OFFSET (µV)
Figure 4. DNL Error vs. Code, TA = 25°C
Figure 7. Gain Error vs. Op Amp Offset
1.5
1.0
–3.88
–3.90
–3.92
–3.94
–3.96
–3.98
–4.00
–4.02
–4.04
–4.06
–4.08
V
V
= 5V
REF
DD
0x0FFF
0x7FFF
= 10V
0xF000
0x8000
0.5
0
–0.5
–1.0
–1.5
–2000 –1500 –1000 –500
0
500
1000
1500
2000
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
OP AMP OFFSET (µV)
TIME (µs)
Figure 5. INL Error vs. Op Amp Offset
Figure 8. Midscale Transition
1.00
0.75
0.50
0.25
0
V
V
= 5V
REF
V
V
= 5V
REF
DD
DD
= 10V
= 10V
V
OUT
0x0FFF
0xF000
0x8000
LDAC
–0.25
–0.50
–0.75
–1.00
–1000 –750
–500
–250
0
250
500
750
1000
OP AMP OFFSET (µV)
Figure 6. DNL Error vs. Op Amp Offset
Figure 9. Large Signal Settling Time
Rev. 0 | Page 8 of 12
Enhanced Product
AD5544-EP
0.1
4
100
90
80
70
60
50
40
30
20
10
0
V
V
= 5V
DD
= 10V
REF
0
0
–0.1
–0.2
–4
–8
–12
–16
–20
–2
0
2
4
6
8
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
TIME (µs)
Figure 12. Power Supply Rejection vs. Frequency
Figure 10. Small Signal Settling Time
10,000
1000
100
10
300
250
200
150
100
50
ZERO SCALE
MIDSCALE
FULL SCALE
0x5555
1
0
1k
10k
100k
1M
10M
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
CLOCK FREQUENCY (Hz)
LOGIC INPUT (V)
Figure 13. Power Supply Current vs. Logic Input Voltage
Figure 11. Power Supply Current vs. Clock Frequency
Rev. 0 | Page 9 of 12
AD5544-EP
Enhanced Product
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
8.20
7.80
7.40
1
14
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
SEATING
PLANE
COPLANARITY
0.10
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-150-AH
Figure 4. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model
Resolution (Bits)
INL LSB DNL LSB Temperature Range
Package Description
28-Lead Shrink Small Outline Package [SSOP]
AD5544SRS-EP
16
1.5
1.5
−55°C to +125°C
RS-28
Rev. 0 | Page 10 of 12
Enhanced Product
NOTES
AD5544-EP
Rev. 0 | Page 11 of 12
AD5544-EP
NOTES
Enhanced Product
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10083-0-4/12(0)
Rev. 0 | Page 12 of 12
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