AD5544_04 [ADI]
Quad, Current-Output, Serial-Input 16-/14-Bit DACs; 四，电流输出，串行输入16位/ 14位DAC
| 型号： | AD5544_04 |
| 厂家： | 
ADI |
| 描述： | Quad, Current-Output, Serial-Input 16-/14-Bit DACs |
| 文件： | 总20页 (文件大小：1150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
AD5544/AD5554
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
A B C D
AD5544 16-bit resolution
AD5554 14-bit resolution
2 mA full-scale current 20ꢀ, with VREF
2 µs settling time
VSS BIAS for zero-scale error reduction @ temp
midscale or zero-scale reset
REF
V
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
R
A
FB
=
10 V
SDO
INPUT
REGISTER
DAC A
REGISTER
DAC A
DAC B
DAC C
DAC D
I
A
OUT
R
R
R
R
R
R
R
R
A
A
GND
R
B
FB
INPUT
REGISTER
DAC B
REGISTER
16
D9
I
B
OUT
D10
D11
D12
D13
D14
D15
A0
Four separate, 4-Q multiplying reference inputs
A
B
GND
SPI®-compatible 3-wire interface
Double buffered registers enable
Simultaneous multichannel change
Internal power ON reset
R
I
C
FB
INPUT
REGISTER
DAC C
REGISTER
C
OUT
SDI
A1
A
C
GND
CS
R
I
D
FB
CLK
EN
Compact SSOP-28 package
INPUT
REGISTER
DAC D
REGISTER
D
OUT
DAC
A
B
C
D
A
D
GND
APPLICATIONS
Automatic test equipment
Instrumentation
2:4
POWER-
ON
RESET
AD5544
DECODE
A
F
GND
Digitally controlled calibration
DGND
RS
MSB
LDAC
V
SS
Figure 1.
GENERAL DESCRIPTION
1.0
The AD5544/AD5554 quad, 16-/14-bit, current-output, digital
to-analog converters are designed to operate from a single
5 V supply.
DAC A
DAC B
DAC C
DAC D
0.5
0
–0.5
–1.0
1.0
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
0.5
0
–0.5
–1.0
1.0
A double-buffered serial-data interface offers high speed,
3-wire, SPI- and microcontroller-compatible inputs using serial-
0.5
0
CS
data-in (SDI), a chip-select ( ), and clock (CLK) signals. In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common, level-sensitive,
–0.5
–1.0
1.0
LDAC
load-DAC strobe (
) input allows the simultaneous update
0.5
0
of all DAC outputs from previously loaded input registers.
Additionally, an internal power ON reset forces the output
voltage to zero at system turn ON. An MSB pin allows system
–0.5
–1.0
RS
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
reset assertion ( ) to force all registers to zero code when
MSB = 0, or to half-scale code when MSB = 1.
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
The AD5544/AD5554 are packaged in the compact SSOP-28.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5554/AD5554
TABLE OF CONTENTS
Specifications..................................................................................... 3
AD5544 Electrical Characteristics ............................................. 3
AD5554 Electrical Characteristics ............................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ........................................... 10
Circuit Operation ........................................................................... 14
D/A Converter............................................................................ 14
Serial Data Interface....................................................................... 16
Power On Reset .......................................................................... 17
Applications ................................................................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
12/04—Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Change to Electrical Characteristics Tables .......................................4
Change to Pin Description Table.......................................................10
Addition of Power Supply Sequence Section...................................19
Addition of Layout and Power Supply Bypassing Section .............19
Addition of Grounding Section.........................................................19
Addition of Figure 32..........................................................................19
4/00—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5544/AD5554
SPECIFICATIONS
AD5544 ELECTRICAL CHARACTERISTICS
VDD = 5 V 10ꢀ, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.
Table 1.
Parameter
Symbol
Condition
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
N
INL
DNL
1 LSB = VREF/216 = 153 µV when VREF = 10 V
16
Bits
LSB
LSB
nA
nA
mV
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
±±
±1.5
10
20
±3
IOUT
IOUT
X
X
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA max
Data = FFFFH
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
GFSE
TCVFS
RFBX
±0.ꢀ5
1
6
ppm/°C
kΩ
VDD = 5 V
±
8
REFERENCE INPUT
VREFX Range
Input Resistance
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
VREF
RREF
RREF
X
X
X
−15
±
+15
8
V
kΩ
%
6
1
5
Channel-to-channel
CREF
X
pF
Output Current
IOUT
COUT
X
X
Data = FFFFH
Code-dependent
1.25
2.±
±
2.5
0.8
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
INTERFACE TIMING2, 3
Clock Width High
80
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
1
10
0.±
IOL = 1.6 mA
IOH = 100 µA
V
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Width Low
CS
to Clock Setup
CS
25
2
25
20
20
5
Clock to
Hold
Clock to SDO Prop Delay
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
20
tLDS
tLDH
Load Hold
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
ISS
PDISS
PSS
±.5
5.5
250
1
1.25
0.006 %/%
V
Logic inputs = 0 V
Logic inputs = 0 V, VSS = –5 V
Logic inputs = 0 V
∆VDD = ±5%
50
0.001
µA
µA
mW
Rev. A | Page 3 of 20
AD5554/AD5554
Parameter
AC CHARACTERISTICS±
Symbol
Condition
Min Typ
Max
Unit
Output Voltage Settling Time tS
To ±0.1% of full scale, data = 0000H to FFFFH to
0x0000
To ±0.0015% of full scale, data = 0000H to FFFFH to
0000H
1
2
µs
Output Voltage Settling Time
tS
µs
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
BW − 3 dB
Q
VREFX = 100 mV rms, data = FFFFH, CFB = 15 pF
VREFX = 10 V, data 0000H to 8000H to 0000H
Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Data = 0000H, VREFB = 100 mV rms, adjacent
channel, f = 100 kHz
2
12
−65
−90
MHz
nV-s
dB
VOUTX/VREF
X
VOUTA/VREF
B
dB
Digital Feedthrough
Q
CS
5
nV-s
dB
nV√Hz
= 1, and fCLK = 1 MHz
Total Harmonic Distortion
Output Spot Noise Voltage
THD
eN
VREF = 5 V p-p, data = FFFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
−90
ꢀ
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1ꢀꢀ I-to-V converter amplifier. The AD55±± RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25 °C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
± All ac characteristic tests are performed in a closed-loop system using an OP±2 I-to-V converter amplifier.
AD5554 ELECTRICAL CHARACTERISTICS
VDD = 5 V 10ꢀ, VSS = 0 V, IOUTX = virtual GND, AGNDX = 0 V, VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.
Table 2.
Parameter
Symbol
Condition
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
N
INL
DNL
1 LSB = VREF/21± = 610 µV when VREF = 10 V
1±
Bits
LSB
LSB
nA
nA
mV
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
±1
±1
10
20
±10
IOUT
IOUT
X
X
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = 3FFFH
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
REFERENCE INPUT
VREFX Range
GFSE
TCVFS
RFBX
±2
1
ppm/°C
kΩ
VDD = 5 V
±
6
8
VREF
RREF
RREF
X
X
X
−15
±
+15
8
V
kΩ
%
Input Resistance
6
1
5
Input Resistance Match
Input Capacitance2
ANALOG OUTPUT
Channel-to-channel
CREF
X
pF
Output Current
IOUT
X
Data = 3FFFH
Code-dependent
1.25
2.±
2.5
0.8
mA
pF
Output Capacitance2
C
OUTX
80
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
VIL
VIH
IIL
CIL
VOL
VOH
V
V
µA
pF
V
1
10
0.±
Logic Output Low Voltage
Logic Output High Voltage
IOL = 1.6 mA
IOH = 100 µA
±
V
Rev. A | Page ± of 20
AD5544/AD5554
Parameter
Symbol
Condition
Min Typ
Max
Unit
INTERFACE TIMING2, 3
Clock Width High
Clock Width Low
tCH
tCL
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
to Clock Setup
CS
25
2
25
20
20
5
Clock to
Hold
Clock to SDO Prop Delay
Load DAC Pulse Width
Data Setup
Data Hold
Load Setup
20
Load Hold
25
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
AC CHARACTERISTICS±
Output Voltage Settling Time
Output Voltage Settling Time
VDD RANGE
IDD
ISS
PDISS
PSS
±.5
50
5.5
250
1
1.25
0.006 %/%
V
Logic inputs = 0 V
Logic inputs = 0 V, VSS = –5 V
Logic inputs = 0 V
∆VDD = ±5%
µA
µA
mW
0.001
tS
tS
To ±0.1% of full scale, data = 0000H to 3FFFH to 0000H
To ±0.0015% of full scale, data = 0000H to 3FFFH
to 0000H
1
2
µs
µs
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Crosstalk Error
BW – 3 dB
Q
VREFX = 100 mV rms, data = 3FFFH, CFB = 15 pF
VREFX = 10 V, data 0000H to 2000H to 0000H
Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Data = 0000H, VREFB = 100 mV rms, adjacent channel,
f = 100 kHz
2
12
–65
–90
MHz
nV-s
dB
VOUTX/VREF
X
VOUTA/VREF
B
dB
Digital Feedthrough
Q
CS
5
nV-s
dB
nV√Hz
= 1, and fCLK = 1 MHz
Total Harmonic Distortion
Output Spot Noise Voltage
THD
eN
VREF= 5 V p-p, data = 3FFFH, f = 1 kHz
f = 1 kHz, BW = 1 Hz
–90
ꢀ
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1ꢀꢀ I-to-V converter amplifier. The AD555± RFB terminal is
tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
± All ac characteristic tests are performed in a closed-loop system using an OP±2 I-to-V converter amplifier.
Rev. A | Page 5 of 20
AD5554/AD5554
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VSS to GND
VREF to GND
Logic Input and Output to GND
V(IOUT) to GND
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Rating
−0.3 V, +8 V
+0.3 V, −ꢀ V
−18 V, +18 V
−0.3 V, +8 V
−0.3 V, VDD+ 0.3 V
−0.3 V, + 0.3 V
±50 mA
AGNDX to DGND
Input Current to Any Pin Except Supplies
Package Power Dissipation
Thermal Resistance
(TJ Max − TA)/θJA
θJA
28-Lead Shrink Surface-Mount (RS-28)
Maximum Junction Temperature (TJ Max)
Operating Temperature Range: Model A
Storage Temperature Range
Lead Temperature:
100°C/W
150°C
−±0°C to +85°C
−65°C to +150°C
RS-28 (Vapor Phase, 60 secs)
RS-28 (Infrared, 15 secs)
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as ±000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5544/AD5554
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
A
A
A
A
A
GND
A
D
GND
I
OUT
I
D
OUT
3
V
REF
V
D
REF
4
R
R
D
FB
FB
5
MSB
RS
DGND
AD5544/ꢀ
AD5554
TOP VIEW
6
V
SS
7
V
A
F
DD
GND
8
(Not to Scale) 21
CS
CLK
SDI
LDAC
SDO
9
20
19
18
17
16
15
10
11
12
13
14
NC
R
B
B
B
B
FB
R
C
FB
V
REF
OUT
GND
V
C
REF
I
I
C
OUT
A
A
C
GND
NC = NO CONNECT
Figure 3. AD5544/AD5554 Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Name
Function
1
2
3
±
AGND
IOUT
VREF
RFBA
MSB
RS
A
A
A
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC A by connecting to external amplifier output.
MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD.
5
6
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD55±±
and 2000H for AD555±) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.
Register Data = 8000H for AD55±± and 2000H.
ꢀ
8
VDD
CS
Positive Power Supply Input. Specified range of operation 5 V ±10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input
register when CS/LDAC returns high. Does not effect LDAC operation.
9
CLK
SDI
RFBB
Clock Input. Positive edge clocks data into shift register.
Serial Data Input. Input data loads directly into the shift register.
Establish voltage output for DAC B by connecting to external amplifier output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD55±±
and 1ꢀ clock pulses for AD555± after input at the SDI pin.
10
11
12
13
1±
15
16
1ꢀ
18
19
20
VREF
B
IOUTB
AGND
AGND
B
C
IOUTC
VREF
C
RFBC
NC
SDO
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous
active low input. See Table 5 and Table 6 for operation.
22
23
2±
25
26
2ꢀ
28
AGNDF
VSS
DGND
RFBD
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
Digital Ground Pin.
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
DAC D Current Output.
VREF
IOUT
AGND
D
D
D
DAC D Analog Ground.
Rev. A | Page ꢀ of 20
AD5554/AD5554
SDI
A1
A0
D15 D14 D13 D12 D11 D10
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 4. AD5544 Timing Diagram
SDI
A1
A0
D13 D12 D11 D10 D09 D08
D1
D0
INPUT
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDS
tLDAC
tLDH
LDAC
tPD
SDO
Figure 5. AD5554 Timing Diagram
Table 5. AD55441 Control-Logic Truth Table
CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function
DAC Register
H
L
L
X
L
H
H
H
H
H
H
X
X
X
No Effect
No Effect
Shift-Register-Data Advanced
One Bit
Latched
Latched
Latched
Latched
Latched
Latched
￪+
L
H
L
H
H
H
H
X
X
No Effect
No Effect
Latched
Latched
Latched
Selected DAC Updated with Current
SR Contents
￪+
H
H
H
X
X
X
L
H
H
H
H
X
X
X
No Effect
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
Latched
￪+
H
H
H
H
X
X
L
L
0
H
No Effect
No Effect
Latched Data = 0000H
Latched Data = 8000H
Latched Data = 0000H
Latched Data = 8000H
1 For the AD55±±, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
Rev. A | Page 8 of 20
AD5544/AD5554
Table 6. AD55541 Control-Logic Truth Table
CS
CLK LDAC RS MSB Serial Shift Register2 Function
Input Register2 Function
DAC Register
H
L
L
X
L
￪+2
H
H
H
H
H
H
X3
X
X
No Effect
No Effect
Shift-Register-Data Advanced
One Bit
Latched
Latched
Latched
Latched
Latched
Latched
L
￪+2
H
L
H
H
H
H
X
X
No Effect
No Effect
Latched
Latched
Latched
Selected DAC Updated with Current
Shift-Register Contents±
H
H
H
X
X
X
L
H
H
H
H
X
X
X
No Effect
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
Latched
￪+
H
H
H
H
X
X
L
L
0
H
No Effect
No Effect
Latched Data = 0000H
Latched Data = 2000H
Latched Data = 0000H
Latched Data = 2000H
1 For the AD555±, data appears at the SDO Pin 1ꢀ clock pulses after input at the SDI pin.
2
￪
+ positive logic transition.
3 X = don’t care.
± At power on both the input register and the DAC register are loaded with all zeros.
Table 7. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
Data Word
B1ꢀ
A1
B16 B15 B1± B13 B12 B11 B10 B9 B8 Bꢀ B6 B5 B± B3 B2 B1 B0
A0 D15 D1± D13 D12 D11 D10 D9 D8 Dꢀ D6 D5 D± D3 D2 D1 D0
1
CS
Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the
line’s positive edge returns to logic high. At this point an inter-
nally generated load strobe transfers the serial register data contents (Bits D15 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any
LDAC
extra bits clocked into the AD55±± shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the
logic low to disable the DAC registers.
pin can be tied
Table 8. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
Data Word
B15
A1
B1±
A0
B13
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
Bꢀ
Dꢀ
B6
D6
B5
D5
B±
D±
B3
D3
B2
D2
B1
D1
B0
D0
1
CS
Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the
line’s positive edge returns to logic high. At this point an
internally generated load strobe transfers the serial register data contents (Bits D13 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0.
LDAC
Any extra bits clocked into the AD555± shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the
tied logic low to disable the DAC registers.
pin can be
Table 9. Address Decode
A1
A0
0
DAC Decoded
DAC A
0
0
1
DAC B
1
0
DAC C
1
1
DAC D
Rev. A | Page 9 of 20
AD5554/AD5554
TYPICAL PERFORMANCE CHARACTERISTICS
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.50
0.25
DAC A
DAC B
DAC C
0
–0.25
DAC A
–0.50
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.50
0.25
0
–0.25
DAC B
–0.50
0.75
0.50
0.25
0.50
0.25
0
0
–0.25
–0.50
–0.75
–0.25
DAC C
–0.50
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
0.50
0.25
DAC D
8192
0
–0.25
DAC D
–0.50
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
0
2048 4096
6144
10240 12288 14336 16384
CODE (Decimal)
Figure 6. AD5544 DNL vs. Code, TA = 25°C
Figure 8. AD5554 DNL vs. Code, TA = 25°C
1.0
0.5
2.0
1.5
1.0
0.5
DAC A
V
V
T
= 5V
DD
= 10V
REF
0
–0.5
–1.0
= 25°C
F000
A
H
8000
H
1.0
0.5
DAC B
DAC C
DAC D
0
–0.5
–1.0
–1.5
–2.0
7FFF
0FFF
H
H
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
0
–1500
–1000
–500
500
1000
1500
OP AMP OFFSET VOLTAGE (µV)
1.0
0.5
Figure 9. AD5544 Integral Nonlinearity Error vs. Op Amp Offset
0
–0.5
–1.0
0
2048 4096
6144
8192
10240 12288 14336 16384
CODE (Decimal)
Figure 7. AD5554 INL vs. Code, TA = 25°C
Rev. A | Page 10 of 20
AD5544/AD5554
0.75
0.50
0.25
0
10.0
7.5
V
V
= 5V
DD
V
V
= 5V
DD
= 10V
REF
= 10V
REF
T
= 25°C
A
T
= 25°C
A
3000
H
5.0
2.5
0
2000
H
1FFF
0FFF
H
H
–2.5
–5.0
–0.25
–0.50
–0.75
–7.5
–10.0
–1500
0
–2000 –1500 –1000 –500
500
1000
1500 2000
0
–1000
–500
500
1000
1500
OP AMP OFFSET VOLTAGE (µV)
OP AMP OFFSET VOLTAGE (µV)
Figure 10. AD5554 Integral Nonlinearity Error vs. Op Amp Offset
Figure 13. AD5544 Gain Error vs. Op Amp Offset
4
3
2
1.00
V
V
= 5V
DD
V
V
= 5V
DD
= 10V
REF
= 10V
0.75
REF
8000
F000
H
T
= 25°C
A
T
= 25°C
A
0.50
0.25
0
1
0
H
0FFF
H
–1
–2
–3
–4
–0.25
–0.50
–0.75
–1.00
–5
–1500
0
0
–1000 –750
–500 –250
250
500
750
1000
–1000
–500
500
1000
1500
OP AMP OFFSET VOLTAGE (µV)
OP AMP OFFSET VOLTAGE (µV)
Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset
Figure 14. AD5554 Gain Error vs. Op Amp Offset
0.3
30
SS = 120 UNITS
V
V
= 5V
2000
3000
DD
H
V
= 5V
DD
= 10V
REF
0.2
0.1
V
= 10V
REF
T
= 25°C
A
T
= –40°C TO +85°C
A
20
10
0
H
0
0FFF
H
–0.1
–0.2
–0.3
ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.
0
0
0.5
1.0
1.5
–1500
–1000
–500
500
1000
1500
FULL-SCALE TEMPCO (ppm/°C)
OP AMP OFFSET VOLTAGE (µV)
Figure 15. AD5544 Full-Scale Tempco (ppm/°C)
Figure 12. AD5554 Differential Nonlinearity Error vs. Op Amp Offset
Rev. A | Page 11 of 20
AD5554/AD5554
50
40
30
20
10
SS = 180 UNITS
V
V
T
= 5V
DD
V
OUT
(10V/DIV)
= 10V
V
V
= 5V
REF
DD
= –40°C TO +85°C
= 10V
A
REF
T
= 25°C
= –343
A
A
V
1LSB = 52mV
V
OUT
(50mV/DIV)
1µs/DIV
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
FULL-SCALE ERROR TEMPCO (ppm/°C)
Figure 19. AD5544 Small Signal Settling Time
Figure 16. AD5554 Full-Scale Tempco (ppm/°C)
10000
1000
100
7FFF
8000
V
= 5V
DD
= 10V
= 25°C
H
H
V
V
= 5V
DD
5555
H
V
REF
= 10V
REF
T
A
T
= 25°C
A
CS
(5V/DIV)
FFFF
H
8000
H
H
0000
V
OUT
(50mV/DIV)
100ns/DIV
10
1k
10k
100k
1M
10M
100M
CLOCK FREQUENCY (Hz)
Figure 17. AD5544 Midscale Transition
Figure 20. AD5544 Power Supply Current vs. Clock Frequency
10000
1000
100
0000
FFFF
V
V
= 5V
DD
H
H
V
V
= 5V
DD
1555
= 10V
H
REF
= 10V
REF
CS
(5V/DIV)
T
= 25°C
A
T
= 25°C
A
3FFF
H
2000
0000
H
H
V
OUT
(5V/DIV)
2µs/DIV
10
1k
10k
100k
1M
10M
100M
CLOCK FREQUENCY (Hz)
Figure 18. AD5544 Large Signal Settling Time
Figure 21. AD5554 Power Supply Current vs. Clock Frequency
Rev. A | Page 12 of 20
AD5544/AD5554
100
90
80
70
60
50
40
30
20
600
500
400
300
200
100
0
V
= 5V ±10%
V
V
= 5V
DD
DD
= 25°C
T
= 10V
A
REF
T
= 25°C
A
0
1
2
3
4
5
100
1k
10k
100k
1M
CLOCK FREQUENCY (Hz)
LOGIC INPUT VOLTAGE (V)
Figure 24. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage
Figure 22. AD5544/AD5554 Power Supply Rejection vs. Frequency
55
V
V
= 5V
DD
54
53
52
51
50
49
48
47
46
= 10V
REF
LOGIC = V
DD
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 23. AD5544/AD5554 Power Supply Current vs. Temperature
Rev. A | Page 13 of 20
AD5554/AD5554
CIRCUIT OPERATION
The AD5544 and AD5554 contain four, 16-bit and 14-bit, cur-
rent-output, digital-to-analog converters, respectively. Each
DAC has its own independent multiplying reference input. Both
the AD5544 and the AD5554 use a 3-wire, SPI compatible, serial
resistance of 5 kΩ, 30ꢀ. On the other hand, the DAC outputs
IOUTA, B, C, D are code-dependent and produce various out-
put resistances and capacitances. The choice of external ampli-
fier should take into account the variation in impedance
generated by the AD5544/AD5554 on the amplifiers’ inverting
input node. The feedback resistance, in parallel with the DAC
ladder resistance, dominates output voltage noise. For multi-
plying mode applications, an external feedback compensation
capacitor (CFB) may be needed to provide a critically damped
output response for step changes in reference input voltages.
Figure 26 and Figure 27 show the gain vs. frequency perfor-
mance at various attenuation settings using a 23 pF external
feedback capacitor connected across the IOUTX and RFBX ter-
minals for AD5544 and AD5554, respectively. In order to main-
tain good analog performance, power supply bypassing of
0.01 µF, in parallel with 1 µF, is recommended. Under these
conditions, a clean power supply with low ripple voltage capa-
bility should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and
PSS frequency-dependent characteristics. It is best to derive the
AD5544/AD5554’s 5 V supply from the system’s analog supply
voltages. Do not use the digital 5 V supply (see Figure 28).
RS
data interface, with a configurable asynchronous
half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition,
LDAC
pin for
an
strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
D/A CONVERTER
Each part contains four current-steering R-2R ladder DACs.
Figure 25 shows a typical equivalent DAC. Each DAC contains a
matching feedback resistor for use with an external I-to-V con-
verter amplifier. The RFBX pin connects to the output of the
external amplifier. The IOUTX terminal connects to the inverting
input of the external amplifier. The AGNDX pin should be Kelvin-
connected to the load point requiring full 16-bit accuracy. These
DACs are designed to operate with both negative or positive
reference voltage. The VDD power pin is only used by the logic to
drive the DAC switches on and off. Note that a matching switch
is used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the value of RFB, power must be applied to
VDD in order to achieve continuity. An additional VSS bias pin is
used to guard the substrate during high temperature applica-
tions, minimizing zero-scale leakage currents that double every
10°C. The DAC output voltage is determined by VREF and the
digital data (D) in the following equations:
FFFF
H
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ZS
D
65536
VOUT = −VREF
VOUT = −VREF
×
×
For AD5544
(1)
(2)
D
16384
(
For AD5554
)
V
V
= 5V
DD
= 100mV rms
REF
Note that the output polarity is opposite to the VREF polarity for
dc reference voltages.
T
= 25°C
A
100
1k
10k
100k
1M
10M
V
DD
FREQUENCY (Hz)
R
R
R
R
X
V
X
FB
REF
Figure 26. AD5554 Reference Multiplying Bandwidth vs. Code
2R
2R
2R
R
5kΩ
3FFF
H
B13
B12
B11
B10
S2
S1
I
X
OUT
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A
F
GND
A
X
GND
FROM OTHER DACS A
GND
V
DGND
SS
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED.
DD
Figure 25. Typical Equivalent DAC Channel
V
V
= 5V
DD
= 100mV rms
ZS
REF
These DACs are also designed to accommodate ac reference
input signals. Both the AD5544 and the AD5554 accommodate
input reference voltages in the range of −12 V to +12 V. The
reference voltage inputs exhibit a constant nominal input
T
C
= 25°C
= 23pF
A
F
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 27. AD5554 Reference Multiplying Bandwidth vs. Code
Rev. A | Page 1± of 20
AD5544/AD5554
15V
ANALOG
POWER
SUPPLY
2R
R
5V
+
V
DD
AD5544
R
X
RR
R
FB
V
X
REF
2R
2R
2R
R
5kΩ
15V
S2
S1
V
I
X
CC
OUT
V
A
F
OUT
GND
A1
A
X
GND
+
V
EE
LOAD
FROM OTHER DACS A
GND
DGND
V
SS
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
MUST BE POWERED.
V
DD
Figure 28. Recommended Kelvin-Sensed Hookup
Rev. A | Page 15 of 20
AD5554/AD5554
SERIAL DATA INTERFACE
the
line low between the first, second, and third byte trans-
CS
The AD5544/AD5554 uses a 3-wire ( , SDI, CLK) SPI compa-
CS
fers will result in a successful serial register update. Similarly,
two right justified data bytes can be written to the AD5554.
Keeping the
tible serial data interface. Serial data of AD5544 and AD5554 is
clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table 6
defines the 18 data-word bits for AD5544.
line low between the first and second byte
CS
transfer will result in a successful serial register update.
Once the data is properly aligned in the shift register, the posi-
Table 7 defines the 16 data-word bits for AD5554. Data is placed
on the SDI pin, and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the interface timing specifications.
CS
tive edge of the
initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For AD5544, Table 5, Table 7, Table 9, and Figure 4
define the characteristics of the software serial interface. For
AD5554, Table 6, Table 8, Table 9, and Figure 5 define the
characteristics of the software serial interface. Figure 29 and
Figure 30 show the equivalent logic interface for the key digital
control pins for the AD5544. AD5554 has a similar configura-
data can only be clocked in while the
chip select pin is active
CS
low. For AD5544, only the last 18 bits clocked into the serial
register will be interrogated when the pin returns to the
CS
logic high state, extra data bits are ignored. For AD5554, only
the last 16 bits clocked into the serial register will be inter-
RS
tion, except it has 14 data bits. Two additional pins,
and
rogated when the
pin returns to the logic high state. Since
CS
MSB, provide hardware control over the preset function and
DAC register loading.
most microcontrollers output serial data in 8-bit bytes, three
right justified data bytes can be written to the AD5544. Keeping
V
A B C D
REF
CS
EN
AD5544
V
DD
CLK
R
I
A
FB
SDI
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
DAC A
REGISTER
INPUT
REGISTER
A
DAC A
OUT
R
R
R
R
R
A
A
GND
D9
D10
D11
D12
D13
D14
D15
A0
R B
FB
INPUT
REGISTER
DAC B
REGISTER
I
B
DAC B
OUT
R
R
R
A
B
DAC A
GND
SDO
B
C
D
A1
2:4
DECODE
R
I
C
FB
INPUT
REGISTER
DAC C
REGISTER
C
DAC C
OUT
A
C
GND
R
I
D
FB
INPUT
REGISTER
DAC D
REGISTER
D
DAC D
OUT
A
D
GND
SET
MSB
SET
MSB
A
F
POWER-
ON
GND
RESET
DGND
MSB
V
LDAC
RS
SS
Figure 29. System Level Digital Interfacing
Rev. A | Page 16 of 20
AD5544/AD5554
RS
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and filter any low frequency ripple
(see Figure 32). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
If these functions are not needed, the
pin can be tied to logic
RS
high. The asynchronous input
pin forces all input and DAC
registers to either the zero-code state (MSB = 0) or the half-
scale state (MSB = 1).
TO INPUT REGISTER
ꢁ
A
AD5544/AD5554
B
C
D
ADDRESS
DECODER
CS
VDD
VDD
+
C3
C1
10µF
0.1µF
A
X
EN
GND
C4
10µF
C2
0.1µF
SHIFT REGISTER
TH
CLK
SDI
VSS
VSS
DGND
TH
19 /17
CLOCK
SDO
Figure 32. Power Supply Bypassing and Grounding Connection
Figure 30. AD5544/AD5554 Equivalent Logic Interface
Grounding
POWER ON RESET
The DGND and AGNDX pins of the AD5544/AD5554 refer as
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 32).
When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state or half-scale state, depending on the MSB pin voltage. The
VDD power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on
the power-on reset performance. The DAC register data will
stay at a zero or half-scale setting until a valid serial register
data load takes place.
APPLICATIONS
The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.
In some applications it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external ampli-
fier (A2) configured as a summing amplifier (see Figure 33). In
this circuit the first and second amplifiers (A1 and A2) provide
a total gain of 2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the refer-
ence voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = −10 V) to midscale
(VOUT = 0 V) to full-scale (VOUT = 10 V).
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and VDD, as shown in Figure 31.
V
DD
5kΩ
DIGITAL
INPUTS
DGND
Figure 31. Equivalent ESD Production Circuits
Power Supply Sequence
As standard practice, it is recommended to power VDD, VSS, and
ground prior to any reference. The ideal power up sequence is
AGNDX, DGND, VDD, VSS, VREFX, and digital inputs. A noncompli-
ance power up sequence may elevate the reference current, but
the devices resume normal operation once VDD and VSS are
powered-up.
D
32768
D
⎛
⎜
⎝
⎞
⎠
(
)
(3)
VOUT
−1 × −V
For AD5544
⎟
REF
⎛
⎜
⎝
⎞
(
)
(4)
VOUT
−1 × − V
For AD5554
⎟
REF
8192
⎠
10kΩ
10kΩ
10V
Layout and Power Supply Bypassing
5kΩ
V
REF
A2
–10V <
V
OUT
It is good practice to employ a compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
AD588
V
< +10V
OUT
V
DD
V
X
R
X
REF
FB
I
X
OUT
ONE CHANNEL
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low-ESR 1 µF to 10 µF tantalum or
AD5544
A1
V
A
F
SS
GND
A
X
GND
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
Figure 33. Four-Quadrant Multiplying Application Circuit
Rev. A | Page 1ꢀ of 20
AD5544/AD5554
OUTLINE DIMENSIONS
10.50
10.20
9.90
28
15
14
8.20
7.80
7.40
5.60
5.30
5.00
1
1.85
1.75
1.65
0.10
COPLANARITY
2.00 MAX
0.25
0.09
8°
4°
0°
0.38
0.22
0.95
0.75
0.55
0.65
BSC
0.05
MIN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AH
Figure 34. 28-Lead SSOP
(RS-28)
Dimensions Shown in Inches and (Millimeters)
ORDERING GUIDE
Model
RES Bit
INL LSB
±±
±1
DNL LSB
Temperature Range
–±0°C to +85°C
–±0°C to +85°C
Package Description
SSOP-28
SSOP-28
Package Option
RS-28
RS-28
AD55±±ARS
AD555±BRS
AD55±±EVAL
16
1±
±1.5
±1
Evaluation Board
Rev. A | Page 18 of 20
AD5544/AD5554
NOTES
Rev. A | Page 19 of 20
AD5544/AD5554
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00943-0-12/04(A)
Rev. A | Page 20 of 20
相关型号：
AD5546BRU-REEL7
Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors
ADI
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