AD5422BCPZ-REEL7_技术文档

Single Channel, 12-/16-Bit, Serial Input,

Current Source and Voltage Output DACs

AD5412/AD5422

FEATURES

GENERAL DESCRIPTION

12-/16-bit resolution and monotonicity

The AD5412/AD5422 are low-cost, precision, fully integrated

Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA,

0 mA to 24 mA

12-/16-bit digital-to-analog converters (DAC) offering a pro-

grammable current source and programmable voltage output

designed to meet the requirements of industrial process control

applications.

0.01 ꢀ FSR typical total unadjusted error (TUE)

3 ppm/°C output drift

Voltage output ranges: 0 V to 5 V, 0 V to 10 V, 5 V, 10 V

10ꢀ overrange

The output current range is programmable at 4 mA to 20 mA,

0 mA to 20 mA, or an overrange function of 0 mA to 24 mA.

0.01 ꢀ FSR typical total unadjusted error (TUE)

2 ppm/°C output drift

Flexible serial digital interface

On-chip output fault detection

On-chip reference: 10 ppm/°C maximum

Asynchronous clear function

Power supply range

AV_DD: 10.8 V to 40 V

AV_SS: −26.4 V to −3 V/0 V

Voltage output is provided from a separate pin that can be

configured to provide 0 V to 5 V, 0 V to 10 V, 5 V, or 10 V

output ranges; an overrange of 10% is available on all ranges.

Analog outputs are short and open-circuit protected and can

drive capacitive loads of 1 μF.

The device operates with an AV_DDpower supply range from

10.8 V to 40 V. Output loop compliance is 0 V to AV_DD– 2.5 V.

The flexible serial interface is SPI- and MICROWIRE™-

compatible and can be operated in 3-wire mode to minimize

the digital isolation required in isolated applications.

Output loop compliance: AV_DD– 2.5 V

Temperature range: −40°C to +85°C

TSSOP and LFCSP packages

The device also includes a power-on-reset function, ensuring

that the device powers up in a known state. The part also

includes an asynchronous clear pin (CLEAR) that sets the

outputs to zero-scale/midscale voltage output or the low

end of the selected current range.

APPLICATIONS

Process control

Actuator control

PLC

The total output error is typically 0.01% in current mode and

0.01% in voltage mode.

Table 1. Pin-Compatible Devices

Part Number

Description

AD5410

Single channel, 12-bit, serial

input current source DAC

AD5420

Single channel, 16-bit, serial

input current source DAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5412/AD5422

TABLE OF CONTENTS

Features .............................................................................................. 1

AD5412/AD5422 Features ............................................................ 31

Fault Alert.................................................................................... 31

Voltage Output Short Circuit Protection ................................ 31

Voltage Output Overrange........................................................ 31

Voltage Output Force-Sense ..................................................... 31

Asynchronous Clear (CLEAR)................................................. 31

Internal Reference ...................................................................... 31

External Current Setting Resistor ............................................ 31

Digital Power Supply.................................................................. 32

External Boost Function ........................................................... 32

External Compensation Capacitor........................................... 32

Digital Slew Rate Control.......................................................... 32

I_OUTFiltering Capacitors (LFCSP Package)............................. 33

Applications Information.............................................................. 35

Driving Inductive Loads............................................................ 35

Transient Voltage Protection .................................................... 35

Galvanically Isolated Interface ................................................. 35

Microprocessor Interfacing....................................................... 35

Layout Guidelines....................................................................... 35

Thermal and Supply Considerations....................................... 36

Industrial Analog Output Module........................................... 37

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 39

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 13

General......................................................................................... 13

Voltage Output............................................................................ 15

Current Output........................................................................... 20

Terminology .................................................................................... 24

Theory of Operation ...................................................................... 26

Architecture................................................................................. 26

Serial Interface ............................................................................ 27

Power-On State ........................................................................... 28

Data Register............................................................................... 29

Control Register.......................................................................... 29

Reset Register.............................................................................. 30

Status Register............................................................................. 30

REVISION HISTORY

8/09—Rev. 0 to Rev. A

Changes to Architecture Section.................................................. 26

Changes to AD5412/AD5422 Features Section ......................... 31

Added IOUT Filtering Capacitors (LFCSP Package)Section,

Including Figure 69 to Figure 72 and Table 24........................... 33

Changes to Thermal and Supply Considerations Section......... 36

Updated Outline Dimensions....................................................... 38

Changes to Ordering Guide.......................................................... 39

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 7

Changes to Introduction to Table 4................................................ 8

Changes to Introduction to Table 5 and to Table 5.................... 10

Changes to Pin Configurations and Function Descriptions

Section, Added Figure 6, Renumbered Subsequent Figures..... 11

Changes to Theory of Operation Section.................................... 26

5/09—Revision 0: Initial Version

Rev. A | Page 2 of 40

AD5412/AD5422

FUNCTIONAL BLOCK DIAGRAM

DV

CC

SELECT

DV

AV

DD

CC

SS

CLEAR

SELECT

R2

R3

AD5412/AD5422

BOOST

CLEAR

LATCH

SCLK

SDIN

12/16

INPUT SHIFT

REGISTER

AND CONTROL

LOGIC

12-/16-BIT

DAC

I

OUT

SDO

FAULT

R

SET

POWER-ON

RESET

R

SET

VREF

+V

SENSE

RANGE

SCALING

V

OUT

–V

SENSE

REFOUT

REFIN

GND

C

COMP

Figure 1.

Rev. A | Page 3 of 40

AD5412/AD5422

SPECIFICATIONS

AV_DD= 10.8 V to 26.4 V, AV_SS= −26.4 V to −3 V/0 V, AV_DD+ |AV_SS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DV_CC= 2.7 V to 5.5 V.

V_OUT: R_LOAD= 1 kΩ, C_L= 200 pF, I_OUT: R_LOAD= 350 ꢀ; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE OUTPUT

Output Voltage Ranges

0

−5

−10

5

V

10

+5

+10

Accuracy

Resolution

Output unloaded

AD5422

AD5412

16

12

Bits

Total Unadjusted Error (TUE)

B Version

−0.1

−0.05

−0.3

−0.1

−0.008

−0.032

−1

+0.1

+0.05

+0.3

+0.1

+0.008

+0.032

+1

% FSR

LSB

0.01

T_A= 25°C

A Version

0.05

T_A= 25°C

AD5422

AD5412

Relative Accuracy (INL)²

Differential Nonlinearity (DNL)

Bipolar Zero Error

Guaranteed monotonic

Bipolar output range

T_A= 25°C, bipolar output range

Bipolar output range

−6

+6

mV

−1.5

0.2

3

+1.5

mV

ppm FSR/°C

Bipolar Zero Error Temperature

Coefficient (TC)³

Zero-Scale Error

−5

+5

mV

−3.5

0.3

2

+3.5

mV

ppm FSR/°C

T_A= 25°C

Zero-Scale Error Temperature

Coefficient (TC)³

Offset Error

−4

+4

mV

Unipolar output range

−1.5

0.2

2

+1.5

mV

ppm FSR/°C

T_A= 25°C, unipolar output range

Unipolar output range

Offset Error Temperature

Coefficient (TC)³

Gain Error

−0.07

−0.05

+0.07

0.004 +0.05

1

% FSR

ppm FSR/°C

T_A= 25°C

Gain Error Temperature

Coefficient (TC)³

Full-Scale Error

−0.07

−0.05

+0.07

0.001 +0.05

1

% FSR

ppm FSR/°C

Full-Scale Error Temperature

Coefficient (TC)³

OUTPUT CHARACTERISTICS³

Headroom

0.5

0.8

V

Output unloaded

Output Voltage Drift vs. Time

Short-Circuit Current

Load

90

20

ppm FSR

mA

kΩ

Drift after 1000 hours, T_A= 125°C

1

Capacitive Load Stability

R_LOAD= ∞

T_A= 25°C

20

5

1

nF

μF

R_LOAD= 1 kΩ

R_LOAD= ∞

External compensation capacitor of 4 nF

connected

DC Output Impedance

Power-On Time

0.3

10

Ω

μs

Rev. A | Page 4 of 40

AD5412/AD5422

Parameter¹

Min

Typ

90

3

Max

130

12

Unit

μV/V

Test Conditions/Comments

DC PSRR

Output unloaded

CURRENT OUTPUT

Output Current Ranges

0

4

24

20

mA

Accuracy (Internal R_SET

Resolution

)

16

12

Bits

AD5422

AD5412

Total Unadjusted Error (TUE)

B Version

−0.3

−0.13

−0.5

+0.3

+0.13

+0.5

% FSR

LSB

% FSR

ppm FSR/°C

0.08

T_A= 25°C

A Version

−0.3

0.15

+0.3

T_A= 25°C

AD5422

AD5412

Guaranteed monotonic

Relative Accuracy (INL)⁴

−0.024

−0.032

−1

−0.27

−0.12

+0.024

+0.032

+1

+0.27

+0.12

Differential Nonlinearity (DNL)

Offset Error

0.08

16

T_A= 25°C

Offset Error Temperature

Coefficient (TC)³

Gain Error

−0.18

−0.03

−0.22

−0.06

+0.18

0.006 +0.03

+0.22

0.006 +0.06

10

% FSR

ppm FSR/°C

% FSR

AD5422

AD5422, T_A= 25°C

AD5412

AD5412, T_A= 25°C

Gain Temperature Coefficient (TC)³

Full-Scale Error

−0.2

−0.1

+0.2

+0.1

0.08

6

T_A= 25°C

Full-Scale Temperature Coefficient

(TC)³

ppm FSR/°C

Accuracy (External R_SET

Resolution

)

16

12

Bits

AD5422

AD5412

Total Unadjusted Error (TUE)

B Version

−0.15

−0.06

−0.3

+0.15

+0.06

+0.3

% FSR

LSB

0.01

0.02

T_A= 25°C

A Version

−0.1

+0.1

T_A= 25°C

AD5422

AD5412

Guaranteed monotonic

Relative Accuracy (INL)⁴

−0.012

−0.032

−1

+0.012

+0.032

+1

Differential Nonlinearity (DNL)

Offset Error

−0.1

+0.1

% FSR

−0.03

0.006 +0.03

3

T_A= 25°C

Offset Error Temperature

Coefficient (TC)³

μA/°C

Gain Error

−0.08

−0.05

+0.08

0.003 +0.05

4

% FSR

ppm FSR/°C

% FSR

T_A= 25°C

Gain Temperature Coefficient (TC)³

Full-Scale Error

−0.15

−0.06

+0.15

0.01

7

+0.06

Full-Scale Temperature Coefficient

(TC)³

ppm FSR/°C

Rev. A | Page 5 of 40

AD5412/AD5422

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS³

Current Loop Compliance Voltage

Output Current Drift vs. Time

0

AV_DD− 2.5

V

Drift after 1000 hours, T_A= 125°C

Internal R_SET

External R_SET

50

20

ppm FSR

Ω

mH

μA/V

MΩ

Resistive Load

Inductive Load

DC PSRR

Output Impedance

Output Current Leakage When

Output Is Disabled

1200

1

50

T_A= 25 °C

50

60

pA

REFERENCE INPUT/OUTPUT

Reference Input³

Reference Input Voltage

DC Input Impedance

Reference Output

4.95

27

5

40

5.05

V

kΩ

For specified performance

T_A= 25°C

Output Voltage

4.995

5

1.8

5.005

10

Reference Temperature

ppm/°C

Coefficient (TC)^{3, 5}

Output Noise (0.1 Hz to 10 Hz)³

Noise Spectral Density³

Output Voltage Drift vs. Time³

Capacitive Load³

10

100

50

600

5

μV p-p

nV/√Hz

ppm

nF

mA

At 10 kHz

Drift after 1000 hours, T_A= 125°C

Load Current³

Short-Circuit Current³

Load Regulation³

7

95

mA

ppm/mA

DIGITAL INPUTS³

JEDEC compliant

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Current

2

V

μA

pF

0.8

+1

−1

Per pin

Pin Capacitance

10

DIGITAL OUTPUTS³

SDO

Output Low Voltage, V_OL

Output High Voltage, V_OH

High Impedance Leakage Current

High Impedance Output

Capacitance

0.4

+1

V

μA

pF

Sinking 200 μA

Sourcing 200 μA

DV_CC− 0.5

−1

5

FAULT

Output Low Voltage, V_OL

Output High Voltage, V_OH

POWER REQUIREMENTS

AV_DD

0.4

V

10 kΩ pull-up resistor to DV_CC

At 2.5 mA

10 kΩ pull-up resistor to DV_CC

0.6

3.6

10.8

−26.4

10.8

40

0

52.8

V

AV_SS

|AV_SS| + AV_DD

DV_CC

Input Voltage

2.7

5.5

V

Internal supply disabled

Output Voltage

Output Load Current³

Short-Circuit Current³

4.5

5

20

V

mA

DV_CC, which can be overdriven up to 5.5 V

Rev. A | Page 6 of 40

AD5412/AD5422

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

AI_DD

Outputs unloaded

2.5

3.4

3.9

3

4

4.4

mA

Outputs disabled

Current output enabled

Voltage output enabled

Outputs unloaded

AI_SS

0.24

0.5

1.1

0.3

0.6

1.4

1

mA

mW

Outputs disabled

Current output enabled

Voltage output enabled

V_IH= DV_CC, V_IL= GND

AV_DD= 40 V, AV_SS= 0 V, outputs unloaded

AV_DD= +24 V, AV_SS= −24 V, outputs

unloaded

DI_CC

Power Dissipation

128

120

¹Temperature range: −40°C to +85°C; typical at +25°C.

²When the AD5412/AD5422 is powered with AV_SS= 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16

for the AD5412.

³Guaranteed by design and characterization; not production tested.

⁴For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412.

⁵The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

AC PERFORMANCE CHARACTERISTICS

AV_DD= 10.8 V to 26.4 V, AV_SS= −26.4 V to −3 V/0 V, AV_DD+ |AV_SS| < 52.8 V, GND = 0 V, REFIN = +5 V external; DV_CC= 2.7 V to 5.5 V.

V

_OUT: R_LOAD= 1 kΩ, C_L= 200 pF, I_OUT: R_LOAD= 350 ꢀ; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter¹

Min Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Voltage Output

Output Voltage Settling Time

25

18

μs

10 V step to 0.03 % FSR

20 V step to 0.03 % FSR

5 V step to 0.03 % FSR

32

8

μs

512 LSB step to 0.03 % FSR (16-Bit LSB)

Slew Rate

0.8

10

20

1

V/μs

nV-sec

mV

nV-sec

LSB p-p

Power-On Glitch Energy

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Digital Feedthrough

Output Noise (0.1 Hz to 10 Hz

Bandwidth)

0.1

16-bit LSB

Output Noise (100 kHz Bandwidth)

1/f Corner Frequency

200

1

μV rms

kHz

Output Noise Spectral Density

AC PSRR

150

−75

nV/√Hz

dB

Measured at 10 kHz, midscale output, 10 V range

200 mV 50 Hz/60 Hz sine wave superimposed on power

supply voltage

Current Output

Output Current Settling Time

10

40

−75

μs

dB

16 mA step to 0.1% FSR

16 mA step to 0.1% FSR, L = 1 mH

200 mV 50 Hz/60 Hz sine wave superimposed on power

supply voltage

AC PSRR

¹Guaranteed by characterization, not production tested.

Rev. A | Page 7 of 40

AD5412/AD5422

TIMING CHARACTERISTICS

AV_DD= 10.8 V to 26.4 V, AV_SS= −26.4 V to −3 V/0 V, AV_DD+ |AV_SS| < 52.8V, GND = 0 V, REFIN = +5 V external; DV_CC= 2.7 V to 5.5 V.

V_OUT: R_LOAD= 1 kΩ, C_L= 200 pF, I_OUT: R_LOAD= 300 ꢀ; all specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Parameter^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

WRITE MODE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

33

13

40

5

40

20

5

ns min

μs min

ns min

μs max

SCLK cycle time

SCLK low time

SCLK high time

LATCH delay time

LATCH high time

LATCH high time (after a write to the control register)

Data setup time

Data hold time

LATCH low time

t₈

t₉

t₁₀

CLEAR pulse width

CLEAR activation time

READBACK MODE

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

90

40

13

40

5

ns min

ns max

SCLK cycle time

SCLK low time

SCLK high time

LATCH delay time

LATCH high time

Data setup time

Data hold time

LATCH low time

5

40

35

4

t₁₉

t₂₀

Serial output delay time (C_{L SDO}= 15 pF)

LATCH rising edge to SDO tristate (C_{L SDO}⁴= 15 pF)

DAISY-CHAIN MODE

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

90

40

13

40

5

40

35

ns min

ns max

SCLK cycle time

SCLK low time

SCLK high time

LATCH delay time

LATCH high time

Data setup time

Data hold time

LATCH low time

Serial output delay time (C_{L SDO}⁴= 15 pF)

¹Guaranteed by characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, and Figure 4.

⁴C_{L SDO}= capacitive load on SDO output.

Rev. A | Page 8 of 40

AD5412/AD5422

t₁

SCLK

1

2

24

t₂

t₃

t₄

t₅

LATCH

SDIN

t₇

t₈

DB0

t₆

DB23

t₉

CLEAR

t₁₀

I

/V

OUT OUT

Figure 2. Write Mode Timing Diagram

t₁₁

SCLK

1

2

8

9

22

23

24

t₁₄

1

2

t₁₂

t₁₃

t₁₅

LATCH

SDIN

t₁₇

t₁₈

DB0

t₁₆

DB23

X

DB0

NOP CONDITION

INPUT WORD SPECIFIES

REGISTER TO BE READ

t₂₀

t₁₉

SDO

X

DB15

DB0

FIRST 8 BITS ARE

DON’T CARE BITS

SELECTED REGISTER

DATA CLOCKED OUT

UNDEFINED DATA

Figure 3. Readback Mode Timing Diagram

t₂₁

SCLK

26

48

25

1

2

24

t₂₂

t₂₃

t₂₄

t₂₅

LATCH

t₂₇

t₂₈

t₂₆

SDIN

SDO

DB23

DB0

DB23

DB0

INPUT WORD FOR DAC N

UNDEFINED

INPUT WORD FOR DAC N – 1

t₂₉

t₂₀

DB23

DB0

DB23

INPUT WORD FOR DAC N

Figure 4. Daisy-Chain Mode Timing Diagram

Rev. A | Page 9 of 40

AD5412/AD5422

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted. Transient currents of up to

80 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

AV_DDto GND

AV_SSto GND

AV_DDto AV_SS

DV_CCto GND

Digital Inputs to GND

−0.3 V to +48 V

+0.3 V to −48 V

−0.3 V to +60 V

−0.3 V to +7 V

−0.3 V to DV_CC+ 0.3 V or 7 V

(whichever is less)

ESD CAUTION

Digital Outputs to GND

−0.3 V to DV_CC+ 0.3 V or 7 V

(whichever is less)

REFIN/REFOUT to GND

V_OUTto GND

−0.3 V to +7 V

AV_SSto AV_DD

I_OUTto GND

−0.3 V to AV_DD

Operating Temperature Range (T_A)

Industrial¹

−40°C to +85°C

−65°C to +150°C

125°C

Storage Temperature Range

Junction Temperature (T_Jmax)

24-Lead TSSOP Package

θ_JAThermal Impedance

40-Lead LFCSP Package

θ_JAThermal Impedance

Power Dissipation

42°C/W

28°C/W

(T_Jmax – T_A)/θ_JA

JEDEC industry standard

J-STD-020

Lead Temperature

Soldering

ESD (Human Body Model)

2 kV

¹Power dissipated on chip must be derated to keep the junction temperature

below 125°C, assuming that the maximum power dissipation condition is

sourcing 24 mA into GND from I_OUTwith a 4 mA on-chip current.

Rev. A | Page 10 of 40

AD5412/AD5422

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

15

14

13

AV

–V

+V

SS

CC

DD

DV

SENSE

FAULT

GND

PIN 1

NC

FAULT

GND

1

2

3

4

5

6

7

8

9

30 NC

V

OUT

AD5412/

AD5422

INDICATOR

29 CAP2

28 CAP1

CLEAR SELECT

CLEAR

LATCH

SCLK

BOOST

27

26

25

24

CLEAR SELECT

CLEAR

TOP VIEW

AD5412/AD5422

TOP VIEW

I

OUT

(Not to Scale)

I

OUT

LATCH

NC

C

SCLK

(Not to Scale)

COMP

NC

SDIN

23 DV

22 NC

21 NC

SELECT

CC

SDO

C

COMP

NC 10

9

SDIN

DV SELECT

CC

REFIN

REFOUT

10

11

12

SDO

GND

R

SET

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT

VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT

ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION

NOTES

1. NC = NO CONNECT

2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE

IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED

PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AV PIN. IT IS

IS MADE AT THE AV PIN. IT IS RECOMMENDED THAT THE PADDLE BE

SS

RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A

COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.

THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED

THERMAL PERFORMANCE.

Figure 5. TSSOP Pin Configuration

Figure 6. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP

LFCSP

Mnemonic

Description

1

14, 37

AV_SS

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be

connected to 0 V if the output voltage range is unipolar.

2

3

39

2

DV_CC

FAULT

Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.

Fault Alert. This pin is asserted low when an open circuit is detected in current mode or

an overtemperature is detected. Open drain output must be connected to a pull-up resistor.

4, 12

18

3, 15

GND

These pins must be connected to 0 V.

No Connection. Do not connect to these pins.

1, 10, 11, 19, 20, NC

21, 22, 25, 30,

31, 35, 38, 40

5

6

7

8

4

5

6

7

CLEAR

SELECT

CLEAR

Selects the voltage output clear value, either zero-scale or midscale code (see Table 21).

Active High Input. Asserting this pin sets the current output to the bottom of the selected

range or sets the voltage output to the user selected value (zero-scale or midscale).

Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register

data into the DAC register, also updating the output.

Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This

operates at clock speeds of up to 30 MHz.

LATCH

SCLK

9

10

8

9

SDIN

SDO

Serial Data Input. Data must be valid on the rising edge of SCLK.

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback

mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4).

11

13

12, 13

16

GND

R_SET

Ground Reference Pin.

An external, precision, low drift 15 kΩ current setting resistor can be connected to this

pin to improve the I_OUTtemperature drift performance. See the AD5412/AD5422 Features

section.

14

15

17

18

REFOUT

REFIN

Internal Reference Voltage Output. REFOUT = 5 V 2 mV.

External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a

specified performance.

Rev. A | Page 11 of 40

AD5412/AD5422

Pin No.

TSSOP

LFCSP

Mnemonic

Description

16

23

DV_CC

SELECT

When connected to GND, this pin disables the internal supply, and an external supply

must be connected to the DV_CCpin. Leave this pin unconnected to enable the internal

supply. See the AD5412/AD5422 Features section.

17

24

C_COMP

Optional compensation capacitor connection for the voltage output buffer. Connecting

a 4 nF capacitor between this pin and the V_OUTpin allows the voltage output to drive up

to 1 μF. It should be noted that the addition of this capacitor reduces the bandwidth of

the output amplifier, increasing the settling time.

19

20

26

27

I_OUT

BOOST

Current Output Pin.

Optional External Transistor Connection. Connecting an external transistor reduces the

power dissipated in the AD5412/AD5422. See theAD5412/AD5422 Features section.

N/A

21

28, 29

32

CAP1, CAP2 Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features

section.

V_OUT

Buffered Analog Output Voltage. The output amplifier is capable of directly driving a

1 kΩ, 2000 pF load.

22

23

24

33

34

36

+V_SENSE

−V_SENSE

AV_DD

Sense connection for the positive voltage output load connection.

Sense connection for the negative voltage output load connection.

Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V.

25 (EPAD)

41 (EPAD)

Exposed

paddle

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be

connected to 0 V if the output voltage range is unipolar. The paddle can be left

electrically unconnected provided that a supply connection is made at the AV_SSpin. It is

recommended that the paddle be thermally connected to a copper plane for enhanced

thermal performance.

Rev. A | Page 12 of 40

AD5412/AD5422

TYPICAL PERFORMANCE CHARACTERISTICS

GENERAL

900

9

8

7

6

5

4

3

2

1

0

T

= 25°C

A

T

= 25°C

800

700

600

500

400

300

200

100

0

A

DV

= 5V

CC

DV

= 3V

2.5

CC

0

0.5

1.0

1.5

2.0

3.0

3.5

4.0

4.5

5.0

–21 –19 –17 –15 –13 –11 –9

–7

–5

–3

–1

1

LOGIC VOLTAGE (V)

LOAD CURRENT (mA)

Figure 7. DI_CCvs. Logic Input Voltage

Figure 10. DV_CCOutput Voltage vs. Load Current

5

4

AI

DD

AV

DD

3

T

V

= 25°C

= 0V

A

2

OUT

OUTPUT UNLOADED

3

1

REFERENCE OUTPUT

0

AI

SS

–1

–2

1

CH1 2.00V

CH3 5.00V

M200µs

CH3

2.1V

10

12

14

16

18

20

22

24

26

28

AV /|AV | (V)

DD SS

Figure 8. AI_DD/AI_SSvs. AV_DD/|AV_SS|

Figure 11. REFOUT Turn-on Transient

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

T

OUT

= 25°C

A

I

= 0mA

1

CH1 2µV

M2.00s

LINE

1.8V

10

15

20

25

AV (V)

30

35

40

DD

Figure 9. AI_DDvs. AV_DD

Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)

Rev. A | Page 13 of 40

AD5412/AD5422

45

40

35

30

25

20

15

10

5

AV

= 24V

DD

1

0

CH1 20µV

M2.00s

LINE

0V

0

1

2

3

4

5

6

7

8

9

10

TEMPERATURE COEFFICIENT (ppm/°C)

Figure 13. REFOUT Output Noise (100 kHz Bandwidth)

Figure 15. Reference Temperature Coefficient Histogram

5.003

5.0005

5.0000

4.9995

4.9990

4.9985

4.9980

4.9975

4.9970

4.9965

4.9960

4.9955

50 DEVICES SHOWN

AV = 24V

T

= 25°C

A

DD

AV

= 24V

DD

5.002

5.001

5.000

4.999

4.998

4.997

–40

–20

0

20

40

60

80

0

1

2

3

4

5

6

7

8

9

TEMPERATURE (°C)

LOAD CURRENT (mA)

Figure 14. Reference Voltage vs. Temperature

Figure 16. Reference Voltage vs. Load Current

Rev. A | Page 14 of 40

AD5412/AD5422

VOLTAGE OUTPUT

0.0025

1.0

0.8

AV

= +24V

DD

AV = –24V

AV

AV = 0V

= 24V

DD

+5V RANGE

+10V RANGE

0.0020

0.0015

0.0010

0.0005

0

SS

T

= 25°C

SS

= 25°C

A

T

A

0.6

0.4

0.2

0

–0.0005

–0.0010

–0.0015

–0.0020

–0.0025

–0.2

–0.4

–0.6

–0.8

–1.0

±10V RANGE

±5V RANGE

+5V RANGE

+10V RANGE

0

10,000

20,000

30,000 40,000

CODE

50,000

60,000

0

10,000

20,000

30,000

CODE

40,000

50,000

60,000

Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply

Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply

0.0025

0.005

AV

= +24V

DD

AV = –24V

AV

AV = 0V

= 24V

DD

+5V RANGE

+10V RANGE

0.0020

0.0015

0.0010

0.0005

0

SS

= 25°C

0.003

0.001

T

= 25°C

A

T

A

–0.001

–0.003

–0.005

–0.007

–0.009

–0.0005

–0.0010

–0.0015

–0.0020

–0.0025

±10V RANGE

±5V RANGE

+5V RANGE

+10V RANGE

0

10,000

20,000

30,000

CODE

40,000

50,000

60,000

0

10,000

20,000

30,000 40,000

CODE

50,000

60,000

Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply

Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply

1.0

0.030

AV

= +24V

DD

AV = –24V

AV

AV = 0V

= 24V

+5V RANGE

+10V RANGE

0.8

0.6

DD

SS

0.025

0.020

0.015

0.010

0.005

0

T

= 25°C

SS

= 25°C

A

T

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

±10V RANGE

±5V RANGE

+10V RANGE

+5V RANGE

–0.005

–0.010

0

10,000

20,000

30,000 40,000

CODE

50,000

60,000

0

10,000

20,000

30,000

CODE

40,000

50,000

60,000

Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply

Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply

Rev. A | Page 15 of 40

AD5412/AD5422

0.0015

0.012

0.010

0.008

0.006

0.004

0.002

0

AV = +24V

DD

AV = +24V

DD

AV = –24V

SS

AV = –24V

SS

0.0010

0.0005

0

OUTPUT UNLOADED

–0.0005

–0.0010

–0.0015

–0.002

–0.004

–0.006

–0.008

+5V RANGE

+10V RANGE

±5V RANGE

±10V RANGE

+5V RANGE MAX INL

+10V RANGE MAX INL

±10V RANGE MAX INL

+10V RANGE MIN INL

±10V RANGE MIN INL

±5V RANGE MAX INL

+5V RANGE MIN INL

±5V RANGE MIN INL

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 23. Integral Nonlinearity Error vs. Temperature

Figure 26. Full-Scale Error vs. Temperature

1.5

1.0

0.8

AV

= +24V

DD

AV = +24V

DD

AV = –24V

ALL RANGES

SS

AV = –24V

SS

OUTPUT UNLOADED

+10V RANGE

0.6

0.4

0.5

0.2

0

+5V RANGE

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 27. Offset Error vs. Temperature

Figure 24. Differential Nonlinearity Error vs. Temperature

1.5

1.0

0.015

AV = +24V

DD

AV = +24V

DD

AV = –24V

SS

AV = –24V

SS

OUTPUT UNLOADED

+10V RANGE

0.010

0.005

0

OUTPUT UNLOADED

0.5

0

+5V RANGE

–0.5

–1.0

–1.5

–0.005

–0.010

–0.015

+5V RANGE

+10V RANGE

±5V RANGE

±10V RANGE

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 25. Total Unadjusted Error vs. Temperature

Figure 28. Bipolar Zero Error vs. Temperature

Rev. A | Page 16 of 40

AD5412/AD5422

0.014

0.012

0.010

0.008

0.006

0.004

0.002

0

1.0

0.8

AVDD = +24V

AVSS = –24V

OUTPUT UNLOADED

T

= 25°C

A

±10V RANGE

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.002

–0.004

–0.006

–0.008

+5V RANGE

+10V RANGE

±5V RANGE

±10V RANGE

–40

–20

0

20

40

60

80

10

12

14

16

18

20

22

24

26

28

TEMPERATURE (°C)

AV /|AV | (V)

DD SS

Figure 32. Differential Nonlinearity Error vs. AV_DD/|AV_SS|

Figure 29. Gain Error vs. Temperature

0.0050

0.0045

0.0040

0.0035

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

0

1.3

0.8

AV = +24V

DD

AV = –24V

SS

OUTPUT UNLOADED

T

= 25°C

A

±10V RANGE

0.3

–0.2

–0.7

–1.2

+5V RANGE

+10V RANGE

±5V RANGE

±10V RANGE

10

12

14

16

18

20

22

24

26

28

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

AV /|AV | (V)

DD SS

Figure 33. Total Unadjusted Error vs. AV_DD/|AV_SS|

Figure 30. Zero-Scale Error vs. Temperature

0.05

0.04

0.03

0.02

0.01

0

0.0015

0.0010

0.0005

0

T

= 25°C

A

AV = +15V

DD

AV = –15V

SS

±10V RANGE

T

= 25°C

A

±10V RANGE

–0.01

–0.02

–0.03

–0.04

–0.05

–0.0005

–0.0010

–0.0015

10

12

14

16

18

20

22

24

26

28

–20

–15

–10

–5

0

5

10

15

20

AV /|AV | (V)

SOURCE/SINK CURRENT (mA)

DD SS

Figure 34. Source and Sink Capability of Output Amplifier,

Full-Scale Code Loaded

Figure 31. Integral Nonlinearity Error vs. AV_DD/|AV_SS|

Rev. A | Page 17 of 40

AD5412/AD5422

0.05

12

8

AV

= +15V

DD

AV = –15V

0.04

0.03

0.02

0.01

0

SS

= 25°C

T

A

±10V RANGE

AV

= +24V

4

DD

AV = –24V

SS

±10V RANGE

T

= 25°C

A

0

OUTPUT UNLOADED

–0.01

–0.02

–0.03

–0.04

–0.05

–4

–8

–12

–20

–15

–10

–5

0

5

10

15

20

–10

–5

0

5

10

15

20

25

30

SOURCE/SINK CURRENT (mA)

TIME (µs)

Figure 35. Source and Sink Capability of Output Amplifier,

Zero-Scale Loaded

Figure 37. Full-Scale Negative Step

12

8

4

2

AV

= +24V

DD

SS

AV = –24V

±10V RANGE

0

T

= 25°C

A

OUTPUT UNLOADED

–2

4

0x8000 TO 0x7FFF

0x7FFF TO 0x8000

–4

0

–6

–8

–4

–8

–12

–10

–12

–14

–16

AV

= +24V

DD

AV = –24V

SS

= 25°C

T

A

±10V RANGE

–1

1

3

5

7

9

11

13

15

–10

–5

0

5

10

15

20

25

30

TIME (µs)

Figure 36. Full-Scale Positive Step

Figure 38. Digital-to-Analog Glitch

Rev. A | Page 18 of 40

AD5412/AD5422

35

30

25

20

15

10

5

AV = +15V

DD

AV = –15V

SS

T

= 25°C

A

1

AV

= +24V

SS

= 25°C

DD

AV = –24V

T

A

0

CH1 5.0µV

M 5.00ms

LINE

1.8V

0

2

4

6

8

10

12

14

16

18

20

TIME (µs)

Figure 39. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)

Figure 41. V_OUTvs. Time on Power-Up

1

AV

= +24V

DD

SS

AV = –24V

T

= 25°C

A

CH1 50.0µV

M 5.00ms

LINE

0V

Figure 40. Peak-to-Peak Noise (100 kHz Bandwidth)

Rev. A | Page 19 of 40

AD5412/AD5422

CURRENT OUTPUT

0.004

0.002

0

EXTERNAL R

SET

0.004

0.002

0

AV

= 24V

DD

INTERNAL R

SET

AV = –24V/0V

SS

EXTERNAL R

, BOOST TRANSISTOR

0mA TO 24mA RANGE

SET

INTERNAL R

, BOOST TRANSISTOR

SET

–0.002

–0.004

–0.006

–0.008

–0.010

–0.002

–0.004

–0.006

–0.008

–0.010

AV

= 24V

DD

AV = –24V/0V

SS

T

= 25°C

A

R

= 250Ω

LOAD

0

10,000 20,000

30,000

CODE

40,000

50,000

60,000

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 42. Integral Nonlinearity vs. Code

Figure 45. Integral Nonlinearity vs. Temperature, Internal R_SET

1.0

0.8

0.003

AV

= 24V

DD

AV

= 24V

DD

AV = –24V/0V

0mA TO 24mA RANGE

SS

AV = –24V/0V

SS

T

= 25°C

A

0.002

0.001

0

R

= 250Ω

0.6

LOAD

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.001

–0.002

–0.003

EXTERNAL R

INTERNAL R

EXTERNAL R

INTERNAL R

SET

, BOOST TRANSISTOR

SET

, BOOST TRANSISTOR

0

10,000 20,000

30,000

CODE

40,000

50,000

60,000

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 43. Differential Nonlinearity vs. Code

Figure 46. Integral Nonlinearity vs. Temperature, External R_SET

0.05

0.03

1.0

AV

= 24V

DD

AV = –24V/0V

SS

0.8

0.6

ALL RANGES

INTERNAL AND EXTERNAL R

SET

0.01

–0.01

–0.03

–0.05

–0.07

–0.09

–0.11

–0.13

–0.15

0.4

0.2

AV

= 24V

0

DD

AV = –24V/0V

SS

= 25°C

T

–0.2

–0.4

–0.6

–0.8

–1.0

A

R

= 250Ω

LOAD

EXTERNAL R

SET

INTERNAL R

SET

EXTERNAL R

, BOOST TRANSISTOR

SET

, BOOST TRANSISTOR

INTERNAL R

SET

0

10,000 20,000

30,000

CODE

40,000

50,000

60,000

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 44. Total Unadjusted Error vs. Code

Figure 47. Differential Nonlinearity vs. Temperature

Rev. A | Page 20 of 40

AD5412/AD5422

0.10

0.05

0.015

0.010

0.005

0

AV

= 24V

DD

T

= 25°C

A

AV = –24V/0V

SS

0mA TO 24mA RANGE

AV = 0V

SS

0

–0.05

–0.10

–0.15

–0.20

–0.25

4mA TO 20mA INTERNAL R

0mA TO 20mA INTERNAL R

0mA TO 24mA INTERNAL R

4mA TO 20mA EXTERNAL R

0mA TO 20mA EXTERNAL R

0mA TO 24mA EXTERNAL R

SET

–0.005

–0.010

–0.015

SET

–40

–20

0

20

40

60

80

10

15

20

25

DD

30

35

40

AV

(V)

TEMPERATURE (°C)

Figure 48. Total Unadjusted Error vs. Temperature

Figure 51. Integral Nonlinearity Error vs. AV_DD, External R_SET

0.10

0.05

0.020

AV

= 24V

DD

0.015

0.010

0.005

0

AV = –24V/0V

T

= 25°C

SS

A

0mA TO 24mA RANGE

AV = 0V

SS

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.005

–0.010

–0.015

–0.020

4mA TO 20mA INTERNAL R

0mA TO 20mA INTERNAL R

0mA TO 24mA INTERNAL R

4mA TO 20mA EXTERNAL R

0mA TO 20mA EXTERNAL R

0mA TO 24mA EXTERNAL R

SET

–40

–20

0

20

40

60

80

10

15

20

25

DD

30

35

40

AV

(V)

TEMPERATURE (°C)

Figure 49. Offset Error vs. Temperature

Figure 52. Integral Nonlinearity Error vs. AV_DD, Internal R_SET

0.06

0.04

1.0

0.8

AV

= 24V

DD

T

= 25°C

A

AV = –24V/0V

SS

0mA TO 24mA RANG

0.6

AV = 0V

SS

0.02

0.4

0

0.2

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

4mA TO 20mA INTERNAL R

0mA TO 20mA INTERNAL R

0mA TO 24mA INTERNAL R

4mA TO 20mA EXTERNAL R

0mA TO 20mA EXTERNAL R

0mA TO 24mA EXTERNAL R

SET

–40

–20

0

20

40

60

80

10

15

20

25

30

35

40

AV (V)

DD

TEMPERATURE (°C)

Figure 50. Gain Error vs. Temperature

Figure 53. Differential Nonlinearity Error vs. AV_DD, External R_SET

Rev. A | Page 21 of 40

AD5412/AD5422

1.0

0.8

2.5

2.0

1.5

1.0

0.5

0

AV

AV = 0V

= 15V

DD

SS

= 24mA

I

OUT

T

= 25°C

A

R

= 500Ω

LOAD

0.6

0.4

0mA TO 24mA RANGE

AV = 0V

SS

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

10

15

20

25

DD

30

35

40

–40

–20

0

20

40

60

80

AV

(V)

TEMPERATURE (°C)

Figure 54. Differential Nonlinearity Error vs. AV_DD, Internal R_SET

Figure 57. Compliance Voltage Headroom vs. Temperature

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.025

AV

AV = 0V

= 24V

T

= 25°C

DD

A

0.020

0.015

0.010

0.005

0

0mA TO 24mA RANGE

AV = 0V

SS

= 25°C

T

A

SS

R

= 250Ω

LOAD

–0.005

–0.010

–0.015

0

100

200

300

400

500

600

10

15

20

25

DD

30

35

40

TIME (µs)

AV

(V)

Figure 55. Total Unadjusted Error vs. AV_DD, External R_SET

Figure 58. Output Current vs. Time on Power-Up

20

10

0.05

0.03

0.01

AV

= 24V

DD

AV = 0V

0

–0.01

–0.03

–0.05

–0.07

–0.09

–0.11

–0.13

–0.15

SS

= 25°C

T

A

R

= 250Ω

–10

–20

–30

–40

–50

LOAD

T

= 25°C

A

0mA TO 24mA RANGE

AV = 0V

SS

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

10

15

20

25

AV (V)

30

35

40

TIME (µs)

DD

Figure 56. Total Unadjusted Error vs. AV_DD, Internal R_SET

Figure 59. Output Current vs. Time on Output Enable

Rev. A | Page 22 of 40

AD5412/AD5422

70

60

50

40

30

20

10

0

25

20

15

10

5

T

= 25°C

= 24V

A

AV

DD

AV = 0V

SS

R

= 300Ω

LOAD

T

AV

= 25°C

A

= 40V

DD

AV = 0V

OUTPUT DISABLED

SS

–10

0

5

10

15

20

25

30

35

40

45

–1

0

1

2

3

4

5

6

7

8

COMPLIANCE VOLTAGE (V)

TIME (µs)

Figure 60. Output Leakage Current vs. Compliance Voltage

Figure 62. 4 mA to 20 mA Output Current Step

30

0x8000 TO 0x7FFF

0x7FFF TO 0x8000

AV

AV = 0V

= 24V

DD

SS

= 25°C

20

10

T

A

R

= 250Ω

LOAD

0

–10

–20

–30

0

2

4

6

8

10

12

14

16

18

20

TIME (µs)

Figure 61. Digital to Analog Glitch

Rev. A | Page 23 of 40

AD5412/AD5422

TERMINOLOGY

Slew Rate

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy, or INL, is a measure of the

maximum deviation, in LSBs, from a straight line passing

through the endpoints of the DAC transfer function. A typical

INL vs. code plot can be seen in Figure 17.

The slew rate of a device is a limitation in the rate of change

of the output voltage. The output slewing speed of a voltage-

output DAC is usually limited by the slew rate of the amplifier

used at its output. Slew rate is measured from 10% to 90% of the

output signal and is expressed in V/μs.

Differential Nonlinearity (DNL)

Gain Error

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures monoton-

icity. This DAC is guaranteed monotonic by design. A typical

DNL vs. code plot can be seen in Figure 19.

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal expressed in % FSR. A plot of gain error vs. temperature

can be seen in Figure 29.

Gain Error Temperature Coefficient (TC)

Gain error TC is a measure of the change in gain error with

changes in temperature. Gain error TC is expressed in ppm

FSR/°C.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant for increasing digital input code. The AD5412/AD5422

are monotonic over their full operating temperature range.

Total Unadjusted Error (TUE)

Bipolar Zero Error

TUE is a measure of the output error taking all the various

errors into account, namely INL error, offset error, gain error,

and output drift over supplies, temperature, and time. TUE is

expressed in % FSR.

Bipolar zero error is the deviation of the analog output from the

ideal half-scale output of 0 V when the DAC register is loaded

with 0x8000 (straight binary coding) or 0x0000 (twos comple-

ment coding). A plot of bipolar zero error vs. temperature can

be seen in Figure 28.

Current Loop Voltage Compliance

The maximum voltage at the I_OUTpin for which the output

current is equal to the programmed value.

Bipolar Zero Temperature Coefficient (TC)

Bipolar zero TC is a measure of the change in the bipolar zero

error with a change in temperature. It is expressed in ppm FSR/°C.

Power-On Glitch Energy

Power-on glitch energy is the impulse injected into the analog

output when the AD5412/AD5422 is powered on. It is specified

as the area of the glitch in nV-sec. See Figure 41 and Figure 58.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code is loaded to the DAC register. Ideally, the output should be

full-scale − 1 LSB. Full-scale error is expressed in percent of

full-scale range (% FSR).

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state, but the output voltage remains constant. It is normally

specified as the area of the glitch in nV-sec and is measured

when the digital input code is changed by 1 LSB at the major

carry transition (0x7FFF to 0x8000). See Figure 38 and

Figure 61.

Negative Full-Scale Error/Zero-Scale Error

Negative full-scale error is the error in the DAC output voltage

when 0x0000 (straight binary coding) or 0x8000 (twos comple-

ment coding) is loaded to the DAC register. Ideally, the output

voltage should be negative full-scale − 1 LSB. A plot of zero-

scale error vs. temperature can be seen in Figure 30.

Glitch Impulse Peak Amplitude

Zero-Scale Temperature Coefficient (TC)

Zero-scale TC is a measure of the change in zero-scale error

with a change in temperature. Zero-scale error TC is expressed

in ppm FSR/°C.

Glitch impulse peak amplitude is the peak amplitude of the

impulse injected into the analog output when the input code in

the DAC register changes state. It is specified as the amplitude

of the glitch in millivolt and is measured when the digital input

code is changed by 1 LSB at the major carry transition (0x7FFF

to 0x8000). See Figure 38 and Figure 61.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the

output to settle to a specified level for a full-scale input change.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC but is measured when the DAC output is not updated.

It is specified in nV-sec and measured with a full-scale code

change on the data bus.

Rev. A | Page 24 of 40

AD5412/AD5422

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes

in the power supply voltage.

where:

_REFmaxis the maximum reference output measured over the

total temperature range.

_REFminis the minimum reference output measured over the total

temperature range.

_REFnomis the nominal reference output voltage, 5 V.

V

Voltage Reference TC

Voltage reference TC is a measure of the change in the reference

output voltage with a change in temperature. The reference TC

is calculated using the box method, which defines the TC as the

maximum change in the reference output over a given temperature

range expressed in ppm/°C, as follows:

V

TempRange is the specified temperature range, −40°C to +85°C.

Load Regulation

Load regulation is the change in reference output voltage due to

a specified change in load current. It is expressed in ppm/mA.

⎡

⎢

⎣

⎤

⎥

⎦

V_REFmax−V_REFmin

_REFnom×TempRange

TC =

×10⁶

V

Rev. A | Page 25 of 40

AD5412/AD5422

THEORY OF OPERATION

The AD5412/AD5422 are precision digital-to-current loop and

voltage output converters designed to meet the requirements of

industrial process control applications. They provide a high

precision, fully integrated, low cost single-chip solution for

generating current loop and unipolar/bipolar voltage outputs.

Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA

to 20 mA; the voltage ranges available are 0 V to 5 V, 5 V, 0 V

to 10 V, and 10 V; a 10% overrange is available on all voltage

output ranges. The current and voltage outputs are available on

separate pins, and only one is active at any time. The desired

output configuration is user selectable via the control register.

+V

–V

AD5412/AD5422

SENSE

R1

V

OUT

RANGE

SCALING

12-/16-BIT

DAC

R

LOAD

SENSE

REFIN

V

–1V TO +3V

CM

Figure 65. Voltage Output

Voltage Output Amplifier

The voltage output amplifier is capable of generating both

ARCHITECTURE

unipolar and bipolar output voltages. It is capable of driving

a load of 1 kΩ in parallel with 1 μF (with an external compen-

sation capacitor) to GND. The source and sink capabilities of

the output amplifier can be seen in Figure 35. The slew rate

is 1 V/μs with a full-scale settling time of 25 μs maximum (10 V

The DAC core architecture of the AD5412/AD5422 consists

of two matched DAC sections. A simplified circuit diagram is

shown in Figure 63. The four MSBs of the 12-/16-bit data-word

are decoded to drive 15 switches, E1 to E15. Each of these switches

connects one of 15 matched resistors to either ground or the

reference buffer output. The remaining 8/12 bits of the data-

word drive the S0 to S7/S11 switches of an 8-/12-bit voltage

mode R-2R ladder network.

step). Figure 65 shows the voltage output driving a load, R_LOAD

on top of a common-mode voltage (V_CM) of −1 V to +3 V. In

output module applications where a cable could possibly

become disconnected from +V_SENSE, resulting in the amplifier

loop being broken and possibly resulting in large destructive

voltages on V_OUT, include an optional resistor (R1) between

+V_SENSEand V_OUT, as shown in Figure 65, of a value between

2 kꢀ and 5 kꢀ to ensure the amplifier loop is kept closed. If

remote sensing of the load is not required, connect +V_SENSE

directly to V_OUTand connect −V_SENSEdirectly to GND. When

,

V

OUT

2R 2R

S0

2R

S1

2R

E1

2R

E2

2R

S7/S11

E15

changing ranges on the voltage output, a glitch may occur. For

this reason, it is recommended that the output be disabled by

setting the OUTEN bit of the control register to logic low before

changing the output voltage range; this prevents a glitch from

occurring.

8-12 BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 63. DAC Ladder Structure

The voltage output from the DAC core is either converted to

a current (see Figure 64) which is then mirrored to the supply

rail so that the application simply sees a current source output

with respect to ground or it is buffered and scaled to output a

software selectable unipolar or bipolar voltage range (see

Figure 65). The current and voltage are output on separate

pins and cannot be output simultaneously.

Driving Large Capacitive Loads

The voltage output amplifier is capable of driving capacitive

loads of up to 1 μF with the addition of a nonpolarized 4 nF

compensation capacitor between the C_COMPand V_OUTpins.

Without the compensation capacitor, up to 20 nF capacitive

loads can be driven.

AV

DD

R2

R3

T2

A2

T1

12-/16-BIT

DAC

I

A1

OUT

R

SET

Figure 64. Voltage-to-Current Conversion Circuitry

Rev. A | Page 26 of 40

AD5412/AD5422

SERIAL INTERFACE

CONTROLLER

AD5412/

AD5422¹

The AD5412/AD5422 are controlled over a versatile 3-wire

serial interface that operates at clock rates of up to 30 MHz. It is

compatible with SPI, QSPI™, MICROWIRE, and DSP standards.

DATA OUT

SDIN

SERIAL CLOCK

CONTROL OUT

SCLK

LATCH

Input Shift Register

DATA IN

SDO

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. Data is clocked in on the rising edge of

SCLK. The input register consists of eight address bits and

16 data bits, as shown in Table 7. The 24-bit word is uncondi-

tionally latched on the rising edge of the LATCH pin. Data

continues to be clocked in irrespective of the state of LATCH.

On the rising edge of LATCH, the data that is present in the

input register is latched; in other words, the last 24 bits to be

clocked in before the rising edge of LATCH is the data that is

latched. The timing diagram for this operation is shown in

Figure 2.

SDIN

AD5412/

AD5422¹

SCLK

LATCH

SDO

SDIN

AD5412/

AD5422¹

Table 7. Input Shift Register Format

MSB

SCLK

LATCH

LSB

D23 to D16

Address byte

D15 to D0

SDO

Data-word

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Table 8. Address Byte Functions

Address Word Function

Figure 66. Daisy Chaining the AD5412/AD5422

00000000

00000001

00000010

No operation (NOP)

Data register

Readback register value as per read address

(see Table 9)

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be

used to daisy-chain the devices together as shown in Figure 66.

This daisy-chain mode can be useful in system diagnostics and

in reducing the number of serial interface lines. Daisy-chain

mode is enabled by setting the DCEN bit of the control register

to 1. The first rising edge of SCLK that clocks in the MSB of the

data-word marks the beginning of the write cycle. SCLK is

continuously applied to the input shift register. If more than 24

clock pulses are applied, the data ripples out of the shift register

and appears on the SDO line. This data is valid on the rising

edge of SCLK, having been clocked out on the previous falling

SCLK edge. By connecting the SDO of the first device to the

SDIN input of the next device in the chain, a multidevice

interface is constructed. Each device in the system requires

24 clock pulses. Therefore, the total number of clock cycles

must equal 24 × n, where n is the total number of AD5412/

AD5422 devices in the chain. When the serial transfer to all

devices is complete, LATCH is taken high. This latches the

input data in each device in the daisy chain. The serial clock can

be a continuous or a gated clock.

01010101

01010110

Control register

Reset register

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can be used

only if LATCH is taken high after the correct number of data

bits have been clocked in. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used, and

LATCH must be taken high after the final clock to latch the

data. The rising edge of SCLK that clocks in the MSB of the

data-word marks the beginning of the write cycle. Exactly 24

rising clock edges must be applied to SCLK before LATCH is

brought high. If LATCH is brought high before the 24^thrising

SCLK edge, the data written is invalid. If more than 24 rising

SCLK edges are applied before LATCH is brought high, the

input data is also invalid.

A continuous SCLK source can be used only if LATCH is taken

high after the correct number of clock cycles. In gated clock

mode, a burst clock containing the exact number of clock cycles

must be used, and LATCH must be taken high after the final

clock to latch the data (see Figure 4 for a timing diagram).

Rev. A | Page 27 of 40

AD5412/AD5422

Readback Operation

calibration registers and ensures specified operation of the

AD5412/AD5422.

Readback mode is invoked by setting the address byte and

read address when writing to the input register (see Table 9 and

Table 11). The next write to the AD5412/AD5422 should be a

NOP command, which clocks out the data from the previously

addressed register as shown in Figure 3.

Voltage Output

For a unipolar voltage output range, the output voltage can be

expressed as

D

2





V_OUTV_REFINGain

By default the SDO pin is disabled after having addressed the

AD5412/AD5422 for a read operation; a rising edge on LATCH

enables the SDO pin in anticipation of data being clocked out.

After the data has been clocked out on SDO, a rising edge on

LATCH disables (tristate) the SDO pin. To read back the data

register, for example, implement the following sequence:

N









For a bipolar voltage output range, the output voltage can be

expressed as

Gain V_REFIN

D

2





V_OUTV_REFINGain



N









2

1. Write 0x020001 to the input register. This configures the

part for read mode with the data register selected.

2. Follow this with a second write: a NOP condition, which is

0x000000. During this write, the data from the register is

clocked out on the SDO line.

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the bit resolution of the DAC.

V_REFINis the reference voltage applied at the REFIN pin.

Gain is an internal gain whose value depends on the output

range selected by the user as shown in Table 10.

Table 9. Read Address Decoding

Read Address

Function

Table 10. Internal Gain Value

00

01

10

Read status register

Read data register

Read control register

Output Range

Gain Value

+5 V

+10 V

5 V

1

2

4

POWER-ON STATE

10 V

During power-on of the AD5412/AD5422, the power-on-reset

circuit ensures that all registers are loaded with zero-code. As

such, both outputs are disabled; that is, the V_OUTand I_OUTpins

are in tristate. The +V_SENSEpin is internally connected to ground

through a 40 kΩ resistor. Therefore, if the V_OUTand +V_SENSEpins

are connected together, V_OUTis effectively clamped to ground

through a 40 kΩ resistor. Also upon power-on, internal

calibration registers are read, and the data is applied to internal

calibration circuitry. For a reliable read operation, there must be

sufficient voltage on the AV_DDsupply when the read event is

triggered by the DV_CCpower supply powering up. Powering up

the DV_CCsupply after the AV_DDsupply ensures this. If DV_CCand

AV_DDare powered up simultaneously or the internal DV_CCis

enabled, the supplies should be powered up at a rate greater

than, typically, 500 V/sec or 24 V/50 ms. If this cannot be

achieved, issue a reset command to the AD5412/AD5422 after

power-on; this performs a power-on-reset event, reading the

Current Output

For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA

current output ranges, the output current is respectively

expressed as

20 mA

2^N





I_OUT



 D









24 mA

2^N





 D









16 mA

2^N





 D  4 mA









where:

D is the decimal equivalent of the code loaded to the DAC.

N is the bit resolution of the DAC.

Table 11. Input Shift Register Contents for a Read Operation

MSB

LSB

D0

Read address

D23

D22

D21

D20

D19

D18

D17

D16

D15 to D2

D1

0

1

0

X¹

¹X = don’t care.

Rev. A | Page 28 of 40

AD5412/AD5422

DATA REGISTER

The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is

entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 12 and Table 13.

Table 12. Programming the AD5412 Data Register

MSB

LSB

D0

X

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

12-bit data-word

X

Table 13. Programming the AD5422 Data Register

MSB

LSB

D0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D3

D2

D1

16-bit data-word

CONTROL REGISTER

The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control

register is entered in the D15 to D0 positions, as shown in Table 14. The control register functions are shown in Table 15.

Table 14. Programming the Control Register

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CLRSEL

OVRRNG

REXT

OUTEN

SR clock

SR step

SREN

DCEN

R2

R1

R0

Table 15. Control Register Functions

Option

CLRSEL

OVRRNG

REXT

Description

See Table 21 for a description of the CLRSEL operation.

Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section).

Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section).

OUTEN

SR clock

SR step

SREN

Output enable. This bit must be set to enable the outputs. The range bits select which output is functional.

Digital slew rate control (see the AD5412/AD5422 Features section).

Digital slew rate control enable.

DCEN

Daisy chain enable.

R2, R1, R0

Output range select (see Table 16).

Table 16. Output Range Options

R2

R1

R0

0

1

Output Range Selected

0 V to 5 V voltage range

0 V to 10 V voltage range

5 V voltage range

0

1

0

1

10 V voltage range

1

0

1

0

1

4 mA to 20 mA current range

0 mA to 20 mA current range

0 mA to 24 mA current range

Rev. A | Page 29 of 40

AD5412/AD5422

RESET REGISTER

The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is

entered in the D0 position as shown in Table 17. The reset register options are shown in Table 17 and Table 18.

Table 17. Programming the Reset Register

MSB

LSB

D0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

Reserved

Reset

Table 18. Reset Register Functions

Option

Description

Reset

Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state.

STATUS REGISTER

The status register is a read-only register. The status register functionality is shown in Table 19 and Table 20.

Table 19. Decoding the Status Register

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8 D7

D6 D5

D4

D3

D2

D1

D0

Reserved

I_OUTfault

Slew active

Over temp

Table 20. Status Register Functions

Option

Description

I_OUTFault

This bit is set if a fault is detected on the I_OUTpin.

Slew Active

Over Temp

This bit is set while the output value is slewing (slew rate control enabled).

This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C.

Rev. A | Page 30 of 40

AD5412/AD5422

AD5412/AD5422 FEATURES

FAULT ALERT

ASYNCHRONOUS CLEAR (CLEAR)

The CLEAR pin is an active high clear that allows the voltage

output to be cleared to either zero-scale code or midscale code,

user selectable via the CLEAR SELECT pin, or the CLRSEL bit

of the control register, as described in Table 21. (The clear select

feature is a logical OR function of the CLEAR SELECT pin and

the CLRSEL bit.) The current output clears to the bottom of its

programmed range. It is necessary for CLEAR to be high for a

minimum amount of time to complete the operation (see

Figure 2). When the CLEAR signal is returned low, the output

remains at the cleared value. The preclear value can be restored

by pulsing the LATCH signal low without clocking any data. A

new value cannot be programmed until the CLEAR pin is

returned low.

FAULT

The AD5412/AD5422 are equipped with a

is an open-drain output allowing several AD5412/AD5422

devices to be connected together to one pull-up resistor for

pin, which

FAULT

global fault detection. The

of the following fault scenarios:

pin is forced active by one

•

The voltage at I_OUTattempts to rise above the compliance

range, due to an open-loop circuit or insufficient power

supply voltage. The I_OUTcurrent is controlled by a PMOS

transistor and internal amplifier, as shown in Figure 64.

The internal circuitry that develops the fault output avoids

using a comparator with window limits because this would

FAULT

require an actual output error before the

output

becomes active. Instead, the signal is generated when the

internal amplifier in the output stage has less than ~1 V

of remaining drive capability (when the gate of the output

Table 21. CLRSEL Options

Output Value

CLRSEL Unipolar Output Range

Bipolar Output Range

0 V

Negative full scale

FAULT

PMOS transistor nearly reaches ground). Thus, the

0

1

0 V

Midscale

output activates slightly before the compliance limit is

reached. Because the comparison is made within the

feedback loop of the output amplifier, the output accuracy

is maintained by its open-loop gain, and an output error

In addition to defining the output value for a clear operation,

the CLRSEL bit and CLEAR SELECT pin also define the default

output value. During selection of a new voltage range, the

output value is as defined in Table 21. To avoid glitches on the

output, it is recommended that, before changing voltage ranges,

the user disable the output by setting the OUTEN bit of the

control register to logic low. When OUTEN is set to logic high,

the output goes to the default value as defined by CLRSEL and

CLEAR SELECT.

FAULT

does not occur before the

output becomes active.

•

If the core temperature of the AD5412/AD5422 exceeds

approximately 150°C.

The I_OUTfault and over temp bits of the status register are used

FAULT

in conjunction with the

pin to inform the user which

FAULT

one of the fault conditions caused the

(see Table 19 and Table 20).

pin to be asserted

VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION

INTERNAL REFERENCE

Under normal operation, the voltage output sinks/sources

10 mA. The maximum current that the voltage output delivers

is ~20 mA; this is the short-circuit current.

The AD5412/AD5422 contain an integrated 5 V voltage

reference with initial accuracy of 5 mV maximum and a

temperature drift coefficient of 10 ppm/°C maximum. The

reference voltage is buffered and externally available for use

elsewhere within the system. See Figure 16 for a load regulation

graph of the integrated reference.

VOLTAGE OUTPUT OVERRANGE

An overrange facility is provided on the voltage output. When

enabled via the control register, the selected output range is

overranged by, typically, 10%.

EXTERNAL CURRENT SETTING RESISTOR

VOLTAGE OUTPUT FORCE-SENSE

R_SETis an internal sense resistor as part of the voltage-to-current

conversion circuitry (see Figure 64). The stability of the output

current over temperature is dependent on the stability of the

value of R_SET. As a method of improving the stability of the

output current over temperature, an external precision 15 kꢀ

low drift resistor can be connected to the R_SETpin of the

AD5412/AD5422 to be used instead of the internal resistor

(R_SET). The external resistor is selected via the control register

(see Table 14).

The +V_SENSEand −V_SENSEpins are provided to facilitate remote

sensing of the load connected to the voltage output. If the load

is connected at the end of a long or high impedance cable,

sensing the voltage at the load allows the output amplifier to

compensate and ensure that the correct voltage is applied across

the load. This function is limited only by the available power

supply headroom.

Rev. A | Page 31 of 40

AD5412/AD5422

SR step bits. SR clock defines the rate at which the digital slew is

updated; SR step defines by how much the output value changes

at each update. Both parameters together define the rate of

change of the output voltage or current. Table 22 and Table 23

outline the range of values for both the SR clock and SR step

parameters. Figure 68 shows the output current changing for

ramp times of 10 ms, 50 ms, and 100 ms.

DIGITAL POWER SUPPLY

By default, the DV_CCpin accepts a power supply of 2.7 V to

5.5 V. Alternatively, via the DV_CCSELECT pin, an internal 4.5 V

power supply can be output on the DV_CCpin for use as a digital

power supply for other devices in the system or as a termination

for pull-up resistors. This facility offers the advantage of not

having to bring a digital supply across an isolation barrier. The

internal power supply is enabled by leaving the DV_CCSELECT

pin unconnected. To disable the internal supply, tie DV_CC

SELECT to 0 V. DV_CCis capable of supplying up to 5 mA of

current (for a load regulation graph, see Figure 10).

Table 22. Slew Rate Step Size Options

AD5412 Step Size

(LSB)

AD5422 Step

Size (LSB)

SR Step

000

001

010

011

100

101

110

111

1/16

1/8

1/4

1/2

1

2

4

8

1

2

4

8

16

32

64

128

EXTERNAL BOOST FUNCTION

The addition of an external boost transistor, as shown in

Figure 67, reduces the power dissipated in the AD5412/AD5422

by reducing the current flowing in the on-chip output transistor

(dividing it by the current gain of the external circuit). A

discrete NPN transistor with a breakdown voltage, BV_CEO

,

greater than 40 V can be used. The external boost capability

has been developed for users who may wish to use the

AD5412/AD5422 at the extremes of the supply voltage, load

current, and temperature range. The boost transistor can also

be used to reduce the amount of temperature-induced drift in

the part. This minimizes the temperature-induced drift of the

on-chip voltage reference, which improves on drift and

linearity.

Table 23. Slew Rate Update Clock Options

SR Clock

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Update Clock Frequency (Hz)

257,730

198,410

152,440

131,580

115,740

69,440

37,590

25,770

20,160

16,030

10,290

8280

BOOST

MJD31C

OR

AD5412/

PBSS8110Z

AD5422

I

OUT

1kΩ

0.022µF

R

LOAD

Figure 67. External Boost Configuration

6900

5530

4240

3300

EXTERNAL COMPENSATION CAPACITOR

The voltage output can ordinarily drive capacitive loads of up to

20 nF; if there is a requirement to drive greater capacitive loads,

of up to 1 μF, an external compensation capacitor can be con-

nected between the C_COMPand V_OUTpins. The addition of the

capacitor keeps the output voltage stable but also reduces the

bandwidth and increases the settling time of the voltage output.

The time it takes for the output to slew over a given output

range can be expressed as follows:

Output Change

Slew Time =

(1)

Step Size ×Update Clock Frequency × LSB Size

DIGITAL SLEW RATE CONTROL

The slew rate control feature of the AD5412/AD5422 allows the

user to control the rate at which the output voltage or current

changes. With the slew rate control feature disabled, the output

changes at a rate limited by the output drive circuitry and the

attached load. See Figure 62 for current output step and

Figure 36 for voltage output step. To reduce the slew rate, enable

the slew rate control feature. With the feature enabled via the

SREN bit of the control register (see Table 14), the output, instead

of slewing directly between two values, steps digitally at a rate

defined by two parameters accessible via the control register, as

shown in Table 14. The parameters are set by the SR clock and

where:

Slew Time is expressed in seconds.

Output Change is expressed in amps for I_OUTor volts for V_OUT

.

When the slew rate control feature is enabled, all output

changes change at the programmed slew rate; if the CLEAR

pin is asserted, the output slews to the zero-scale value at the

programmed slew rate. The output can be halted at its current

value with a write to the control register. To avoid halting the

output slew, the slew active bit (see Table 19) can be read to

check that the slew has completed before writing to any of the

Rev. A | Page 32 of 40

AD5412/AD5422

AD5410/AD5420 registers. The update clock frequency for any

given value is the same for all output ranges. The step size,

however, varies across output ranges for a given value of step

size because the LSB size is different for each output range.

Table 24 shows the range of programmable slew times for a full-

scale change on any of the output ranges. The values in Table 24

were obtained using Equation 1.

smoothing out the steps caused by the digital code increments,

as shown in Figure 72.

C1

C2

AV

CAP1

CAP2

DD

The digital slew rate control feature results in a staircase

formation on the current output, as shown in Figure 72. This

figure also shows how the staircase can be removed by

connecting capacitors to the CAP1 and CAP2 pins, as described

in the I_OUTFiltering Capacitors (LFCSP Package) section.

4kΩ

40Ω

BOOST

DAC

12.5kΩ

I

OUT

25

R1

T

= 25°C

A

AV

= 24V

DD

R

= 300Ω

LOAD

20

15

10

5

Figure 70. I_OUTFilter Circuitry

25

20

15

10

5

T

AV

R

= 25°C

A

= 24V

DD

= 300Ω

LOAD

10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5

50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7

100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5

0

–10

NO CAPACITOR

10nF ON CAP1

10nF ON CAP2

47nF ON CAP1

47nF ON CAP2

0

10 20 30 40 50 60 70 80 90 100 110

TIME (ms)

Figure 68. Output Current Slewing Under Control of the Digital Slew Rate

Control Feature

0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

I_OUTFILTERING CAPACITORS (LFCSP PACKAGE)

TIME (ms)

Capacitors can be placed between CAP1 and AV_DD, and CAP2

and AV_DD, as shown in Figure 69.

Figure 71. Slew Controlled 4 mA to 20 mA Output Current Step Using

External Capacitors on the CAP1 and CAP2 Pins

AV

DD

6.8

T

= 25°C

C1

C2

A

AV

= 24V

= 300Ω

6.7

6.6

6.5

6.4

6.3

6.2

6.1

AV

DD

R

LOAD

CAP1

CAP2

AD5412/

AD5422

I

GND

OUT

Figure 69. I_OUTFiltering Capacitors

The CAP1 and CAP2 pins are available only on the LFCSP

package. The capacitors form a filter on the current output

circuitry, as shown in Figure 70, reducing the bandwidth and

the slew rate of the output current. Figure 71 shows the effect

the capacitors have on the slew rate of the output current. To

achieve significant reductions in the rate of change, very large

capacitor values are required, which may not be suitable in

some applications. In this case, the digital slew rate control

feature can be used. The capacitors can be used in conjunction

with the digital slew rate control feature as a means of

NO EXTERNAL CAPS

10nF ON CAP1

10nF ON CAP2

–1

0

1

2

3

4

5

6

7

8

TIME (ms)

Figure 72. Smoothing Out the Steps Caused by the Digital Slew

Rate Control Feature

Rev. A | Page 33 of 40

AD5412/AD5422

Table 24. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range

Update Clock

Step Size (LSB)

Frequency (Hz)

1

2

4

8

16

32

64

128

257,730

198,410

152,440

131,580

115,740

69,440

37,590

25,770

20,160

16,030

10,290

8280

0.25

0.33

0.43

0.50

0.57

0.9

1.7

2.5

3.3

4.1

6.4

7.9

9.5

12

0.13

0.17

0.21

0.25

0.28

0.47

0.87

1.3

1.6

2.0

3.2

4.0

0.06

0.08

0.11

0.12

0.14

0.24

0.44

0.64

0.81

1.0

1.6

2.0

2.4

3.0

3.9

5.0

0.03

0.04

0.05

0.06

0.07

0.12

0.22

0.32

0.41

0.51

0.80

1.0

0.016

0.021

0.027

0.031

0.035

0.06

0.11

0.16

0.20

0.26

0.40

0.49

0.59

0.74

0.97

1.24

0.008

0.010

0.013

0.016

0.018

0.03

0.05

0.08

0.10

0.13

0.20

0.25

0.30

0.37

0.48

0.62

0.004

0.005

0.007

0.008

0.009

0.015

0.03

0.04

0.05

0.06

0.10

0.12

0.15

0.19

0.24

0.31

0.0020

0.0026

0.0034

0.0039

0.0044

0.007

0.014

0.020

0.025

0.03

0.05

0.06

0.07

0.09

0.12

0.16

6900

5530

4240

3300

4.8

5.9

7.7

9.9

1.2

1.5

1.9

2.5

15

20

Rev. A | Page 34 of 40

AD5412/AD5422

APPLICATIONS INFORMATION

ADuM1400¹

ENCODE

CONTROLLER

DRIVING INDUCTIVE LOADS

V

IA

IB

IC

ID

OA

OB

OC

OD

TO

SERIAL

CLOCK IN

When driving inductive or poorly defined loads, connect a

0.01 μF capacitor between I_OUTand GND. This ensures stability

with loads above 50 mH. There is no maximum capacitance

limit. The capacitive component of the load may cause slower

settling. The digital slew rate control feature may also prove

useful in this situation.

DECODE

SCLK

TO

SDIN

SERIAL

DATA OUT

ENCODE

TO

LATCH

SYNC OUT

TRANSIENT VOLTAGE PROTECTION

CONTROL

OUT

TO

CLEAR

The AD5412/AD5422 contain ESD protection diodes that

prevent damage from normal handling. The industrial control

environment can, however, subject I/O circuits to much higher

transients. To protect the AD5412/AD5422 from excessively

high voltage transients, external power diodes and a surge

current limiting resistor are required, as shown in Figure 73.

The constraint on the resistor value is that, during normal

operation, the output level at I_OUTmust remain within its voltage

compliance limit of AV_DD– 2.5 V, and the two protection diodes

and resistor must have appropriate power ratings. Further

protection can be provided with transient voltage suppressors or

transorbs; these are available as both unidirectional suppressors

(protect against positive high voltage transients) and

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 74. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5412/AD5422 is via a serial

bus that uses a protocol compatible with microcontrollers and

DSP processors. The communications channel is a 3-wire

minimum interface consisting of a clock signal, a data signal,

and a latch signal. The AD5412/AD5422 require a 24-bit data-

word with data valid on the rising edge of SCLK.

bidirectional suppressors (protect against both positive and

negative high voltage transients) and are available in a wide

range of standoff and breakdown voltage ratings. It is

For all interfaces, the DAC output update is initiated on the

rising edge of LATCH. The contents of the registers can be

read using the readback function.

recommended that all field connected nodes be protected.

LAYOUT GUIDELINES

AV

DD

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps to

ensure the rated performance. Design the printed circuit board

(PCB) on which the AD5412/AD5422 is mounted so that the

analog and digital sections are separated and confined to

certain areas of the board. If the AD5412/AD5422 is in a system

where multiple devices require an analog ground-to-digital

ground connection, make the connection at one point only.

Establish the star ground point as close as possible to the device.

AV

DD

R

P

AD5412/

AD5422

I

OUT

R

LOAD

GND

Figure 73. Output Transient Voltage Protection

The AD5412/AD5422 should have ample supply bypassing

of 10 μF in parallel with 0.1 μF on each supply located as close

to the package as possible, ideally right up against the device.

The 10 μF capacitors are the tantalum bead type. The 0.1 μF

capacitor should have low effective series resistance (ESR)

and low effective series inductance (ESI), such as the common

ceramic types, which provide a low impedance path to ground

at high frequencies to handle transient currents due to internal

logic switching.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that may occur. The

iCoupler® products from Analog Devices, Inc., provide voltage

isolation in excess of 2.5 kV. The serial loading structure of the

AD5412/AD5422 makes the parts ideal for isolated interfaces

because the number of interface lines is kept to a minimum.

Figure 74 shows a 4-channel isolated interface to the AD5412/

AD5422 using an ADuM1400. For further information, visit

http://www.analog.com/icouplers.

Rev. A | Page 35 of 40

AD5412/AD5422

The power supply lines of the AD5412/AD5422 should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with a

digital ground to avoid radiating noise to other parts of the

board. Never run these near the reference inputs. A ground line

routed between the SDIN and SCLK lines helps reduce crosstalk

between them (this is not required on a multilayer board that

has a separate ground plane, but separating the lines helps). It

is essential to minimize noise on the REFIN line because it

couples through to the DAC output.

To ensure that the junction temperature does not exceed 125°C

while driving the maximum current of 24 mA directly into

ground (also adding an on-chip current of 3 mA), reduce AV_DD

from the maximum rating to ensure that the package is not

required to dissipate more power than previously stated (see

Table 25, Figure 75, and Figure 76).

2.5

LFCSP

2.0

1.5

Avoid crossover of digital and analog signals. Traces on

opposite sides of the PCB should run at right angles to each

other. This reduces the effects of feed through the board. A

microstrip technique is by far the best but not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to the ground plane, and signal

traces are placed on the solder side.

TSSOP

1.0

0.5

0

40

45

50

55

60

65

70

75

80

85

THERMAL AND SUPPLY CONSIDERATIONS

AMBIENT TEMPERATURE (°C)

The AD5412/AD5422 are designed to operate at a maximum

junction temperature of 125°C. It is important that the devices

not be operated under conditions that cause the junction

temperature to exceed this value. Excessive junction tempera-

ture can occur if the AD5412/AD5422 are operated from the

maximum AV_DDwhile driving the maximum current (24 mA)

directly to ground. In this case, control the ambient temperature

or reduce AV_DD. The conditions depend on the device package.

Figure 75. Maximum Power Dissipation vs. Ambient Temperature

45

43

LFCSP

41

39

TSSOP

37

35

33

31

29

27

25

At the maximum ambient temperature of 85°C, the 24-lead

TSSOP package can dissipate 950 mW, and the 40-lead LFCSP

package can dissipate 1.42 mW.

25

35

45

55

65

75

85

AMBIENT TEMPERATURE (°C)

Figure 76. Maximum Supply Voltage vs. Ambient Temperature

Table 25. Thermal and Supply Considerations for Each Package

Considerations

TSSOP

LFCSP

T_Jmax − T_A125 − 85

T_Jmax − T_A

Maximum Allowed Power

Dissipation When Operating

at an Ambient Temperature

of 85°C

125 − 85

=

= 950 mW

=

= 1.42 mW

θ _JA

28

θ_JA

42

Maximum Allowed Ambient

Temperature When

T_Jmax − P_D×θ_JA=125−(40× 0.028) × 42 = 78°C

T_Jmax − P_D×θ_JA=125 − (40 × 0.028) × 28 = 94°C

Operating from a Supply of

40 V and Driving 24 mA

Directly to Ground

Maximum Allowed Supply

Voltage When Operating at

an Ambient Temperature of

85°C and Driving 24 mA

Directly to Ground

T_Jmax − T_A

AI_DD×θ_JA

125 − 85

0.028× 28

T_Jmax − T_A

AI_DD×θ_JA

125 − 85

0.028× 42

=

= 51V

=

= 34 V

Rev. A | Page 36 of 40

AD5412/AD5422

Isolation between the AD5412/AD5422 and the backplane

circuitry is provided with ADuM1400 and ADuM1200

iCoupler digital isolators; further information on iCoupler

products is available at www.analog.com/icouplers. The

internally generated digital power supply of the AD5412/

AD5422 powers the field side of the digital isolaters, removing

the need to generate a digital power supply on the field side of

the isolation barrier. The AD5412/AD5422 digital supply

output supplies up to 5 mA, which is more than enough to

supply the 2.8 mA requirements of the ADuM1400 and

ADuM1200 operating at a logic signal frequency of up to

1 MHz. To reduce the number of isolators required, nonessen-

INDUSTRIAL ANALOG OUTPUT MODULE

Many industrial control applications have requirements for

accurately controlled current and voltage output signals. The

AD5412/AD5422 are ideal for such applications. Figure 77

shows the AD5412/AD5422 in a circuit design for an output

module, specifically for use in an industrial control application.

The design provides for a current or voltage output. The module

is powered from a field supply of 24 V. This supplies AV_DDdirectly.

An inverting buck regulator generates the negative supply for

AV_SS. For transient overvoltage protection, transient voltage

suppressors (TVS) are placed on all field accessible connections.

A 24 V volt TVS is placed on each I_OUT, V_OUT, +V_SENSE, and

−V_SENSEconnection, and a 36 V TVS is placed on the field

supply input. For added protection, clamping diodes are

connected from the I_OUT, V_OUT, +V_SENSE, and −V_SENSEpins to the

AV_DDand AV_SSpower supply pins. If remote voltage load sensing

is not required, the +V_SENSEpin can be directly connected to the

FAULT

tial signals such as CLEAR can be connected to GND.

and SDO can be left unconnected, reducing the isolation

requirements to just three signals.

V_OUTpin and the –V_SENSEpin can be connected to GND.

–15V

INVERTING

BUCK

REGULATOR

24V FIELD SUPPLY

FIELD GROUND

10µF

36V

SMAJ36CA

0.1µF

BACKPLANE

SUPPLY

0.1µF

ADuM1400

4nF

0.1µF

10kΩ

V

DD1

DD2

NC

V

E2

AV

C

COMP

DV

CC

DV

SELECT

DD

CC

V

IA

OA

OB

OC

OD

+V

SENSE

+V

SENSE

V

IB

CLEAR SELECT

V

4.7kΩ

100Ω

IC

V

ID

V

+V

–V

I

OUT

CLEAR

LATCH

SCLK

SDIN

GND

2

1

AD5412/

AD5422¹

–V

SENSE

V

DD1

V

DD2

18Ω

I

FAULT

OUT

OA

OB

IA

OUT

SDO

GND

IB

24V

SMAJ24CA

AV

SS

REFIN

REFOUT

GND GND

2

1

ADuM1200

0.1µF

10µF

0.1µF

–15V

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 77. AD5412/AD5422 in an Industrial Analog Output Module Application

Rev. A | Page 37 of 40

AD5412/AD5422

OUTLINE DIMENSIONS

5.02

5.00

4.95

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

3.25

3.20

3.15

EXPOSED

PAD

(Pins Up)

6.40 BSC

1

BOTTOM VIEW

TOP VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

1.05

1.00

0.80

1.20 MAX

8°

0°

SECTION OF THIS DATA SHEET.

0.20

0.09

0.15

0.05

0.30

0.19

0.65

BSC

0.75

0.60

0.45

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-ADT

Figure 78. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

(RE-24)

Dimensions shown in millimeters

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BSC SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

20

11

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 79. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

Rev. A | Page 38 of 40

AD5412/AD5422

ORDERING GUIDE

Model

Resolution I_OUTTUE

12 Bits

V_OUTTUE

Temperature Range Package Description Package Option

AD5412AREZ¹

0.5% FSR max 0.3% FSR max −40°C to +85°C

0.5% FSR max 0.3% FSR max −40°C to+85°C

0.3% FSR max 0.1% FSR max −40°C to+85°C

0.5% FSR max 0.3% FSR max −40°C to+85°C

0.3% FSR max 0.1% FSR max −40°C to+85°C

24 Lead TSSOP_EP

40 Lead LFCSP_VQ

24 Lead TSSOP_EP

40 Lead LFCSP_VQ

Evaluation Board

RE-24

CP-40-1

RE-24

CP-40-1

AD5412AREZ-REEL7¹12 Bits

AD5412ACPZ-REEL¹

AD5412ACPZ-REEL7¹12 Bits

AD5422AREZ¹

AD5422AREZ-REEL¹

AD5422BREZ¹

AD5422BREZ-REEL¹

AD5422ACPZ-REEL¹

AD5422ACPZ-REEL7¹16 Bits

AD5422BCPZ-REEL¹

16 Bits

AD5422BCPZ-REEL7¹16 Bits

12 Bits

16 Bits

EVAL-AD5422EBZ

¹Z = RoHS Compliant Part.

Rev. A | Page 39 of 40

AD5412/AD5422

NOTES

registered trademarks are the property of their respective owners.

D06996-0-8/09(A)

Rev. A | Page 40 of 40


型号：	AD5422BCPZ-REEL7
厂家：	ADI
描述：	Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs 单通道， 12位/ 16位，串行输入，电流源和电压输出DAC
文件：	总40页 (文件大小：1159K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5422BCPZ-REEL7 [ADI]

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AD5424YCP-REEL

AD5424YCP-REEL7

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