AD5424YCP-REEL [ADI]
8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface; 8位/ 10位/ 12位，高带宽，乘法DAC ，并行接口
| 型号： | AD5424YCP-REEL |
| 厂家： | 
ADI |
| 描述： | 8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface |
| 文件： | 总32页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-/10-/12-Bit, High Bandwidth
Multiplying DACs with Parallel Interface
AD5424/AD5433/AD5445
GENERAL DESCRIPTION
FEATURES
2.5 V to 5.5 V supply operation
Fast parallel interface (17 ns write cycle)
Update rate of 20.4 MSPS
INL of 1 LSB for 12-bit DAC
10 MHz multiplying bandwidth
10 V reference input
The AD5424/AD5433/AD54451 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respect-
ively. These devices operate from a 2.5 V to 5.5 V power supply,
making them suitable for battery-powered applications and
many other applications. These DACs utilize data readback,
allowing the user to read the contents of the DAC register via
the DB pins. On power-up, the internal register and latches are
Extended temperature range: –40°C to +125°C
20-lead TSSOP and chip scale (4 mm × 4 mm) packages
8-, 10-, and 12-bit current output DACs
Upgrades to AD7524/AD7533/AD7545
Pin-compatible 8-, 10-, and 12-bit DACs in chip scale
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
Readback function
filled with 0s and the DAC outputs are at zero scale.
As a result of manufacturing with a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
0.4 μA typical power consumption
While these devices are upgrades of the AD7524/AD7533/
AD7545 in multiplying bandwidth performance, they have a
latched interface and cannot be used in transparent mode.
APPLICATIONS
Portable battery-powered applications
Waveform generators
The AD5424 is available in small, 20-lead LFCSP and 16-lead
TSSOP packages, while the AD5433/AD5445 DACs are
available in small, 20-lead LFCSP and TSSOP packages.
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
1 U.S Patent No. 5,689,257.
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
REF
R
FB
AD5424/
AD5433/
AD5445
R
I
I
1
2
OUT
OUT
8-/10-/12-BIT
R-2R DAC
POWER-ON
RESET
DAC REGISTER
INPUT LATCH
CS
R/W
GND
DB0
DB7/DB9/DB11
DATA
INPUTS
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
AD5424/AD5433/AD5445
TABLE OF CONTENTS
Features .............................................................................................. 1
Bipolar Operation....................................................................... 18
Single-Supply Applications ....................................................... 19
Positive Output Voltage............................................................. 19
Adding Gain................................................................................ 20
DACs Used as a Divider or Programmable Gain Element ... 20
Reference Selection .................................................................... 21
Amplifier Selection .................................................................... 21
Parallel Interface......................................................................... 22
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling................................ 23
Evaluation Board for the AD5424/AD5433/AD5445 ........... 23
Power Supplies for Evaluation Board ...................................... 23
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Terminology................................................................................ 16
Theory of Operation ...................................................................... 17
Circuit Operation ....................................................................... 17
REVISION HISTORY
8/09—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 29
3/05—Rev. 0 to Rev. A
Updated Format................................................................ Universal
Changes to Specifications...............................................................4
Changes to Figure 49.....................................................................17
Changes to Figure 50.....................................................................18
Changes to Figure 51, Figure 52, and Figure 54 ........................19
Added Microprocessor Interfacing Section ...............................22
Added Figure 59.............................................................................24
Added Figure 60.............................................................................25
10/03—Initial Version: Revision 0
Rev. B | Page 2 of 32
AD5424/AD5433/AD5445
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured with OP177and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ Max
Unit
Conditions
STATIC PERFORMANCE
AD5424
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5433
±±.25
±±.5
Guaranteed monotonic
Guaranteed monotonic
Resolution
1±
±±.5
±1
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5445
Resolution
12
±1
–1/+2
±1±
Bits
LSB
LSB
mV
Relative Accuracy
Differential Nonlinearity
Gain Error
Guaranteed monotonic
Gain Error Temperature Coefficient1
Output Leakage Current1
±5
ppm FSR/°C
nA
nA
±1±
±2±
Data = ±×±±±±, TA = 25°C, IOUT1
Data = ±×±±±±, T = −4±°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Resistance
±1±
1±
1±
V
kΩ
kΩ
8
8
12
12
Input resistance TC = –5± ppm/°C
Input resistance TC = –5± ppm/°C
Input Capacitance
Code Zero Scale
Code Full Scale
3
5
6
8
pF
pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
1.7
V
V
V
V
V
V
μA
pF
±.6
VDD − 1
VDD − ±.5
VDD = 4.5 V to 5 V, ISOURCE = 2±± μA
VDD = 2.5 V to 3.6 V, ISOURCE = 2±± μA
VDD = 4.5 V to 5 V, ISINK = 2±± μA
VDD = 2.5 V to 3.6 V, ISINK = 2±± μA
Output Low Voltage, VOL
±.4
±.4
1
Input Leakage Current, IIL
Input Capacitance
4
1±
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
Output Voltage Settling Time
1±
MHz
VREF = ±3.5 V; DAC loaded all 1s
VREF = ±3.5 V, RLOAD = 1±± Ω, DAC latch
alternately loaded with ±s and 1s
Measured to ±16 mV of full scale
Measured to ±4 mV of full scale
Measured to ±1 mV of full scale
Digital Delay
1±% to 9±% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
3±
35
8±
2±
15
2
6±
7±
12±
4±
ns
ns
ns
ns
ns
nV-s
Interface delay time
3±
Rise and fall time, VREF = 1± V, RLOAD = 1±± Ω
1 LSB change around major carry, VREF = ± V
DAC latch loaded with all ±s, VREF = ±3.5 V
Reference = 1 MHz
7±
48
dB
dB
Reference = 1± MHz
Rev. B | Page 3 of 32
AD5424/AD5433/AD5445
Parameter
Min
Typ Max
Unit
Conditions
Output Capacitance
IOUT
1
12
25
22
10
1
17
30
25
12
pF
pF
pF
pF
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz
Clock = 10 MHz, VREF = 3.5 V
IOUT
2
Digital Feedthrough
nV-s
Analog THD
Digital THD
81
dB
50 kHz fOUT
65
25
dB
nV√Hz
Output Noise Spectral Density
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
@ 1 kHz
AD5445, VREF = 3.5 V
55
63
65
dB
dB
dB
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50
60
62
dB
dB
dB
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
AD5445, VREF = 3.5 V
73
80
82
dB
dB
dB
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
70
75
80
dB
dB
dB
50 kHz fOUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
AD5445, VREF = 3.5 V
65
72
dB
dB
51
65
dB
dB
2.5
5.5
0.6
5
V
μA
μA
%/%
TA = 25°C, logic inputs = 0 V or VDD
Logic inputs = 0 V or VDD, T= −40°C to +125°C
ΔVDD = 5%
0.4
Power Supply Sensitivity
0.001
1 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 32
AD5424/AD5433/AD5445
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.
Parameter1
VDD = 2.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
Unit
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time (write cycle)
Data setup time
Data hold time
R/W high to CS low
CS min high time
t1
t2
t3
t4
t5
t6
t7
t8
0
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns typ
ns max
0
0
10
6
0
10
6
0
5
5
9
7
20
40
5
10
20
5
Data access time
t9
Bus relinquish time
10
10
1 Guaranteed by design, not subject to production test.
t2
t2
t6
t1
R/W
t7
t3
t4
CS
t9
t8
t5
DATA
DATA VALID
DATA VALID
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
AD5424/AD5433/AD5445
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
VDD to GND
VREF, RFB to GND
Rating
–0.3 V to +7 V
–12 V to +12 V
–0.3 V to +7 V
IOUT1, IOUT2 to GND
Logic Inputs and Output1
Operating Temperature Range
Extended Industrial (Y Version)
Storage Temperature Range
Junction Temperature
–0.3 V to VDD + 0.3 V
–40°C to +125°C
–65°C to +150°C
150°C
1
CS
W
Overvoltages at DBx, , and R/ , are clamped by internal diodes.
16-Lead TSSOP θJA Thermal Impedance
20-Lead TSSOP θJA Thermal Impedance
20-Lead LFCSP θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
150°C/W
143°C/W
135°C/W
300°C
235°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 32
AD5424/AD5433/AD5445
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
I
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
OUT
FB
I
2
V
2019181716
OUT
REF
DD
GND
DB7
DB6
V
GND 1
15 R/W
PIN 1
R/W
CS
AD5424
INDICATOR
DB7
DB6
CS
NC
2
3
14
13
(Not to Scale)
AD5424
TOP VIEW
DB5 4
DB4
12 NC
11 NC
5
DB5
DB4
DB3
DB0 (LSB)
DB1
6
7 8 9 10
DB2
Figure 3. AD5424 Pin Configuration (TSSOP)
NC = NO CONNECT
Figure 4. AD5424 Pin Configuration (LFCSP)
Table 4. AD5424 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
2
3
19
20
1
IOUT
IOUT
GND
1
2
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground.
4–11
2–9
DB7–DB0
Parallel Data Bits 7 to 0.
10–13 NC
No Internal Connection.
12
13
14
15
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to
read data from the DAC register. Rising edge of CS loads data.
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read
back contents of DAC register.
14
15
16
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier
output.
Rev. B | Page 7 of 32
AD5424/AD5433/AD5445
I
I
1
2
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
R
V
OUT
OUT
FB
REF
DD
GND
DB9
DB8
V
2019181716
R/W
CS
AD5433
GND 1
15 R/W
PIN 1
INDICATOR
(Not to Scale)
DB9
DB8
CS
NC
2
3
14
13
DB7
DB6
DB5
DB4
NC
NC
AD5433
TOP VIEW
DB7 4
DB6
12 NC
5
11
DB0
13 DB0 (LSB)
12 DB1
6
7 8 9 10
DB3
10
11 DB2
NC = NO CONNECT
NC = NO CONNECT
Figure 6 AD5433 Pin Configuration (LFCSP).
Figure 5. AD5433 Pin Configuration (TSSOP)
Table 5. AD5433 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic
Description
1
2
19
20
IOUT
IOUT
1
2
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
DB9–DB0
NC
Ground.
Parallel Data Bits 9 to 0.
Not Internally Connected.
4–13
14, 15
16
2–11
12, 13
14
CS
Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to read data
from the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read back
contents of DAC register.
18
19
20
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
I
I
1
2
1
2
3
4
5
20
19
18
17
16
15
14
R
OUT
OUT
FB
V
REF
DD
2019181716
GND
V
GND 1
15 R/W
DB11
DB10
R/W
PIN 1
INDICATOR
DB11
DB10
CS
DB0
2
3
14
13
CS
AD5445
AD5445
TOP VIEW
DB9 4
DB8
12 DB1
(Not to Scale)
6
7
8
9
DB9
DB8
DB7
DB6
DB0 (LSB)
DB1
5
11
DB2
6
7 8 9 10
13 DB2
12 DB3
11 DB4
Figure 8. AD5445 Pin Configuration (LFCSP)
DB5
10
Figure 7. AD5445 Pin Configuration (TSSOP)
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
19
Mnemonic
Description
1
IOUT1
2
DAC Current Output.
2
20
IOUT
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
Ground Pin.
4–15
16
2–13
14
DB11–DB0
CS
Parallel Data Bits 11 to 0.
W
Chip Select Input. Active low. Used in conjunction with R/ to load parallel data to the input latch or to read data from
CS
the DAC register. Rising edge of
loads data.
17
15
W
R/
CS
CS
to load parallel data. When high, use with to read back contents
Read/Write. When low, use in conjunction with
of DAC register.
18
19
20
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
Rev. B | Page 8 of 32
AD5424/AD5433/AD5445
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.15
0.10
0.05
0
T
= 25°C
T
= 25°C
A
A
V
V
= 10V
V
V
= 10V
REF
= 5V
REF
= 5V
0.15
0.10
0.05
0
DD
DD
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
0
50
100
150
200
250
0
50
100
150
200
250
CODE
CODE
Figure 9. INL vs. Code (8-Bit DAC)
Figure 12. DNL vs. Code (8-Bit DAC)
0.5
0.4
0.5
0.4
T
V
V
= 25°C
T
V
V
= 25°C
A
A
= 10V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
Figure 13. DNL vs. Code (10-Bit DAC)
Figure 10. INL vs. Code (10-Bit DAC)
1.0
0.8
1.0
0.8
T
V
V
= 25°C
T
V
V
= 25°C
A
A
= 10V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000
1500 2000 2500 3000 3500 4000
CODE
0
500
1000
1500 2000 2500 3000 3500 4000
CODE
Figure 14. DNL vs. Code (12-Bit DAC)
Figure 11. INL vs. Code (12-Bit DAC)
Rev. B | Page 9 of 32
AD5424/AD5433/AD5445
0.6
0.5
0.4
2.0
1.5
T
V
V
= 25°C
A
MAX INL
= 0V
1.0
REF
= 3V
DD
MAX INL
0.3
0.5
0.2
0.1
MAX DNL
T
V
= 25°C
A
0
= 5V
DD
–0.5
–1.0
–1.5
–2.0
0
MIN INL
MIN DNL
–0.1
–0.2
–0.3
MIN INL
2
3
4
5
6
7
8
9
10
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
V
(V)
REFERENCE VOLTAGE
BIAS
Figure 15. INL vs. Reference Voltage, AD5445
Figure 18. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
–0.40
4
3
T
V
= 25°C
= 5V
T
= 25°C
A
A
V
V
= 2.5V
= 3V
DD
REF
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
MAX DNL
DD
2
MAX INL
1
0
–1
–2
–3
–4
–5
MIN DNL
MIN INL
MIN DNL
2
3
4
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
REFERENCE VOLTAGE
V
(V)
BIAS
Figure 16. DNL vs. Reference Voltage, AD5445
Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
5
4
0.5
0.4
T
V
V
= 25°C
A
= 0V
REF
= 3V AND 5V
3
DD
0.3
V
= 5V
DD
GAIN ERROR
2
0.2
1
0.1
0
0
V
= 2.5V
DD
–1
–2
–3
–4
–5
–0.1
–0.2
–0.3
–0.4
–0.5
OFFSET ERROR
V
= 10V
REF
–60 –40 –20
0
20
40
60
80
100 120 140
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
TEMPERATURE (°C)
V
(V)
BIAS
Figure 17. Gain Error vs. Temperature
Figure 20. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT
2
Rev. B | Page 10 of 32
AD5424/AD5433/AD5445
0.5
0.4
8
7
6
5
4
3
2
1
0
0.3
0.2
GAIN ERROR
0.1
V
= 5V
DD
0
–0.1
–0.2
–0.3
–0.4
–0.5
OFFSET ERROR
T
V
V
= 25°C
A
V
= 3V
DD
= 2.5V
REF
= 3V AND 5V
V
= 2.5V
2.5
DD
DD
0
0.5
1.0
1.5
2.0
3.0
3.5
4.0
4.5
5.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VOLTAGE (V)
V
(V)
BIAS
Figure 21. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT
2
Figure 24. Supply Current vs. Logic Input Voltage (Driving DB0 to DB11,
All Other Digital Inputs @ Supplies)
3
1.6
1.4
1.2
T
V
V
= 25°C
A
MAX INL
= 0V
REF
= 5V
DD
2
1
I
V
5V
OUT1 DD
1.0
0.8
0.6
0.4
0.2
0
MAX DNL
I
V
3V
OUT1 DD
0
–1
–2
–3
MIN INL
MIN DNL
–40
–20
0
20
40
60
80
100
120
0.5
1.0
1.5
2.0
2.5
TEMPERATURE (°C)
V
(V)
BIAS
Figure 25. IOUT1 Leakage Current vs. Temperature
Figure 22. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
4
3
T
V
V
= 25°C
A
= 2.5V
REF
= 5V
DD
V
= 5V
DD
MAX DNL
2
ALL 0s
ALL 1s
1
0
MAX INL
–1
–2
–3
–4
–5
V
= 2.5V
DD
MIN DNL
ALL 1s
ALL 0s
MIN INL
–60 –40 –20
0
20
40
60
80
100 120 140
0.5
1.0
1.5
2.0
TEMPERATURE (°C)
V
(V)
BIAS
Figure 26. Supply Current vs. Temperature
Figure 23. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
Rev. B | Page 11 of 32
AD5424/AD5433/AD5445
14
3
0
T
= 25°C
A
T = 25°C
A
LOADING ZS TO FS
V
= 5V
DD
AD5445
12
10
8
V
= 5V
DD
–3
–6
–9
6
V
= 3V
DD
4
V
V
V
V
V
= ±2V, AD8038 C 1.47pF
C
REF
REF
REF
REF
REF
V
= 2.5V
DD
= ±2V, AD8038 C 1pF
C
2
= ±0.15V, AD8038 C 1pF
C
= ±0.15V, AD8038 C 1.47pF
C
= ±3.51V, AD8038 C 1.8pF
C
0
1
10
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. Supply Current vs. Update Rate
Figure 30. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
0.045
6
0
–6
ALL ON
0x7FF TO 0x800
V
T
V
= 25°C
= 0V
T
= 25°C
A
A
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
LOADING
ZS TO FS
REF
= 5V
AD8038 AMPLIFIER
DD
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
C
= 1.8pF
COMP
V
= 3V
DD
0x800 TO 0x7FF
= 3V
T
V
= 25°C
A
V
DD
= 5V
DD
V
= ±3.5V
INPUT
= 1.8pF
REF
C
COMP
AD8038 AMPLIFIER
ALL OFF
–0.005
–0.010
AD5445 DAC
V
= 5V
DD
1
10
100
1k
10k
100k
1M
10M 100M
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 31. Midscale Transition, VREF = 0 V
0.2
0
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
T
V
= 25°C
= 3.5V
A
0x7FF TO 0x800
= 5V
REF
AD8038 AMPLIFIER
= 1.8pF
V
DD
C
COMP
–0.2
–0.4
V
= 3V
DD
V
= 5V
V
DD
T
V
V
= 25°C
A
= 3V
DD
= 5V
DD
–0.6
–0.8
= ±3.5V
REF
C
= 1.8pF
COMP
AD8038 AMPLIFIER
AD5445 DAC
0x800 TO 0x7FF
20 40 60
1
10
100
1k
10k
100k
1M
10M
100M
0
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 29. Reference Multiplying Bandwidth—All 1s Loaded
Figure 32. Midscale Transition, VREF = 3.5 V
Rev. B | Page 12 of 32
AD5424/AD5433/AD5445
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
80
60
40
20
0
T
= 25°C
A
MCLK = 1MHz
V
IH
MCLK = 200kHz
V
IL
MCLK = 0.5MHz
T
V
= 25°C
A
= 3.5V
REF
AD8038 AMPLIFIER
AD5445
2.5
3.0
3.5
4.0
VOLTAGE (V)
4.5
5.0
5.5
0
20
40
60
80
100 120 140 160 180 200
fOUT (kHz)
Figure 33. Threshold Voltages vs. Supply Voltage
Figure 36. Wideband SFDR vs. fOUT Frequency
20
0
90
80
70
60
50
40
30
20
10
0
T
V
= 25°C
A
= 3V
DD
AMP = AD8038
MCLK = 5MHz
MCLK = 10MHz
–20
–40
–60
–80
–100
–120
MCLK = 25MHz
FULL SCALE
ZERO SCALE
T
V
= 25°C
A
= 3.5V
REF
AD8038 AMPLIFIER
AD5445
1
10
100
1k
10k
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
fOUT (kHz)
FREQUENCY (Hz)
Figure 34. Power Supply Rejection vs. Frequency
Figure 37. Wideband SFDR vs. fOUT Frequency
–60
–65
–70
–75
–80
–85
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
V
= 25°C
= 3V
A
T
V
= 25°C
= 5V
A
DD
= 3.5V p-p
DD
REF
AMP = AD8038
AD5445
65k CODES
1
10
100
1k
10k
100k
1M
0
2
4
6
8
10
12
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 35. THD and Noise vs. Frequency
Figure 38. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. B | Page 13 of 32
AD5424/AD5433/AD5445
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
20
0
T
V
= 25°C
= 3V
T
V
= 25°C
= 5V
A
A
DD
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
–20
–40
–60
–80
–100
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
50
60
70
80
90
100 110 120 130 140 150
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 39. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Figure 42. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
T
V
= 25°C
= 5V
T
V
= 25°C
= 3V
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
DD
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
200 250 300 350 400 450 500 550 600 650 700
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 40. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Figure 43. Narrow-Band IMD, fOUT = 400 kHz, 500 kHz, Clock = 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
T
V
= 25°C
T = 25°C
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 3V
V
= 3V
DD
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
250 300 350 400 450 500 550 600 650 700 750
70
75
80
85
90
95
100 105 110 115 120
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 41. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
Figure 44. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Rev. B | Page 14 of 32
AD5424/AD5433/AD5445
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
T = 25°C
A
A
= 5V
V
= 5V
DD
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
MCLK 10MHz
5V
V
DD
20
25
30
35
40
45
50
55
60
65
70
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 45. Narrow-Band IMD, fOUT = 40 kHz, 50 kHz, Clock = 10 MHz
Figure 47. Wideband IMD, fOUT = 60 kHz, 50 kHz, Clock = 10 MHz
0
T
V
= 25°C
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 5V
DD
AMP = AD8038
AD5445
65k CODES
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
Figure 46. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
Rev. B | Page 15 of 32
AD5424/AD5433/AD5445
TERMINOLOGY
Digital Feedthrough
Relative Accuracy
When the device is not selected, high frequency logic activity
on the device digital inputs may be capacitively coupled
through the device to show up as noise on the IOUT pins and
subsequently in the following circuitry. This noise is called
digital feedthrough.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting zero scale and full scale and is normally expressed in
LSBs or as a percentage of full-scale reading.
Multiplying Feedthrough Error
Differential Nonlinearity
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB maximum
over the operating temperature range ensures monotonicity.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower order harmonics are included,
such as second to fifth.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF – 1 LSB. Gain error of the
DACs is adjustable to 0 with external resistance.
2
2
2
2
V2 +V3 +V4 +V5
)
THD = 20 log
Output Leakage Current
V1
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it
can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current flows in the IOUT2 line
when the DAC is loaded with all 1s.
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated
digitally by the DAC and the second-order products at 2fa − fb
and 2fb − fa.
Output Capacitance
Capacitance from IOUT1, or IOUT2, to AGND.
Spurious-Free Dynamic Range (SFDR)
SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. It is mea-
sured by the difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate,
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case, 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.
The settling time specification includes the digital delay from
the
rising edge to the full-scale output change.
CS
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA seconds or nV
seconds, depending upon whether the glitch is measured as a
current or voltage signal.
Rev. B | Page 16 of 32
AD5424/AD5433/AD5445
THEORY OF OPERATION
The AD5424, AD5433, and AD5445 are 8-, 10-, and 12-bit
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit
AD5424 is shown in Figure 48. The matching feedback resistor
RFB has a value of R. The value of R is typically 10 kΩ (mini-
mum 8 kΩ and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at
the same potential, a constant current flows in each ladder leg,
regardless of digital input code. Therefore, the input resistance
presented at VREF is always constant and nominally of resistance
value R. The DAC output (IOUT) is code-dependent, producing
various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the DAC on the amplifiers inverting input node.
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5424)
= 0 to 1023 (10-bit AD5433)
= 0 to 4095 (12-bit AD5445)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal digital logic to drive the DAC switches’ on and
off states.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
R
R
R
V
REF
2R
S1
2R
S2
2R
S3
2R
S8
2R
With a fixed 10 V reference, the circuit shown in Figure 49 gives
a unipolar 0 V to –10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
R
R
I
A
1
FB
OUT
OUT
I
2
Table 7 shows the relationship between digital code and
expected output voltage for unipolar operation (AD5424,
8-bit device).
DAC DATA LATCHES
AND DRIVERS
Figure 48. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for
example, to provide a unipolar output, 4-quadrant multipli-
cation in bipolar mode or in single-supply modes of operation.
Note that a matching switch is used in series with the internal
RFB feedback resistor. If users attempt to measure RFB, power
must be applied to VDD to achieve continuity.
Table 7. Unipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
–VREF (255/256)
–VREF (128/256) = –VREF/2
VREF (1/256)
V
REF (0/256) = 0
V
V
DD
R2
CIRCUIT OPERATION
Unipolar Mode
C1
R
DD
FB
AD5424/
AD5433/
AD5445
I
1
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 49.
OUT
V
V
REF
A1
REF
I
2
R1
OUT
V
=
OUT
0 TO –V
REF
GND
R/W CS
When an output amplifier is connected in unipolar mode, the
output voltage is given by
AGND
DATA
INPUTS
D
VOUT = −VREF
×
NOTES:
2n
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 49. Unipolar Operation
Rev. B | Page 17 of 32
AD5424/AD5433/AD5445
R3
20kΩ
R2
C1
V
DD
R5
20kΩ
V
R
FB
DD
R4
R1
AD5424/
AD5433/
AD5445
I
I
1
10kΩ
OUT
OUT
V
±10V
REF
A1
V
REF
2
A2
V
= –V
TO +V
REF REF
OUT
GND
R/W CS
AGND
DATA
INPUTS
NOTES:
1.
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
OUT
2.
3.
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
Figure 50. Bipolar Operation (4-Quadrant Multiplication)
Stability
BIPOLAR OPERATION
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as closely as
possible and proper PCB layout techniques must be employed.
Since every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in closed-
loop applications.
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 50. In
this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage, results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = –VREF) to midscale (VOUT
0 V) to full scale (VOUT = +VREF).
=
An optional compensation capacitor, C1, can be added in
parallel with RFB for stability, as shown in Figure 49 and
Figure 50. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for compensation.
VOUT
=
(
VREF ×D / 2n−1
−VREF
)
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5424)
= 0 to 1023 (10-bit AD5433)
= 0 to 4095 (12-bit AD5445)
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 8 shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5424,
8-bit device).
Table 8. Bipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+VREF (127/128)
0
–VREF (127/128)
–VREF (128/128)
Rev. B | Page 18 of 32
AD5424/AD5433/AD5445
V
V
DD
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
R1
R2
R
FB
DD
The current mode circuit in Figure 51 shows a typical circuit for
operation with a single 2.5 V to 5 V supply. IOUT2 and therefore
V
A1
I
I
1
2
V
IN
OUT
OUT
V
DAC
GND
REF
OUT
I
OUT1 is biased positive by the amount applied to VBIAS. In this
configuration, the output voltage is given by
NOTES:
V
OUT = [D × (RFB/RDAC) × (VBIAS – VIN)] + VBIAS
1.
2.
ADDITIONAL PINS OMITTED FOR CLARITY
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
As D varies from 0 to 255 (AD5424), 0 to 1023 (AD5433),
or 0 to 4095 (AD5445), the output voltage varies from
Figure 52. Single-Supply Voltage-Switching Mode Operation
V
OUT = VBIAS to VOUT = 2VBIAS − VIN.
It is important to note that VIN is limited to low voltages because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC. See Figure 18 to Figure 23.
Also, VIN must not go negative by more than 0.3 V,;otherwise,
an internal diode turns on, exceeding the maximum ratings of
the device. In this type of application, the full range of
multiplying capability of the DAC is lost.
VBIAS should be a low impedance source capable of sinking and
sourcing all possible variations in current at the IOUT2 terminal.
V
DD
C1
V
R
DD
FB
I
1
2
OUT
V
V
DAC
A1
REF
IN
I
V
OUT
OUT
GND
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting ampli-
fier because of the resistor tolerance errors. To generate a
negative reference, the reference can be level-shifted by an op
amp such that the VOUT and GND pins of the reference become
the virtual ground and –2.5 V respectively, as shown
in Figure 53.
V
BIAS
NOTES:
1.
2.
ADDITIONAL PINS OMITTED FOR CLARITY
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 51. Single-Supply Current Mode Operation
It is important to note that VIN is limited to low voltages because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result, their on resistance differs and
the linearity of the DAC degrades.
V
= 5V
DD
ADR03
V
V
IN
OUT
GND
+5V
–5V
C1
V
DD
R
FB
Voltage Switching Mode of Operation
I
I
1
2
OUT
–2.5V
V
REF
Figure 52 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin,
OUT2 is connected to AGND, and the output voltage is available
OUT
V
= 0V TO +2.5V
OUT
GND
I
at the VREF terminal. In this configuration, a positive reference
voltage results in a positive output voltage, making single-
supply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 53. Positive Voltage Output with Minimum of Components
Rev. B | Page 19 of 32
AD5424/AD5433/AD5445
As D is reduced, the output voltage increases. For small values
of D, it is important to ensure that the amplifier does not
saturate and that the required accuracy is met.
ADDING GAIN
In applications where the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the thin
film resistors of the DAC. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, the circuit shown in Figure 54 is a
recommended method of increasing the gain of the circuit. R1,
R2, and R3 should have similar temperature coefficients, but
they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains greater
than 1 are required.
For example, in the circuit shown in Figure 55, an 8-bit DAC
driven with the binary code 0x10 (00010000), that is,
16 decimal, should cause the output voltage to be 16 × VIN.
However, if the DAC has a linearity specification of 0.5 LSB,
then D can in fact have a weight anywhere in the range 15.5/256
to 16.5/256 so that the possible output voltage falls in the range
15.5 VIN to 16.5 VIN—an error of 3% even though the DAC itself
has a maximum error of 0.2%.
V
DD
V
IN
R
V
FB
DD
V
I
I
1
2
DD
OUT
V
REF
OUT
GND
C1
R
V
FB
DD
R1
I
I
1
2
OUT
8-/10-/12-BIT
DAC
V
V
IN
OUT
V
OUT
V
REF
OUT
R3
R2
GND
R2 + R3
R2
NOTE:
ADDITIONAL PINS OMITTED FOR CLARITY
GAIN =
R1 =
NOTES:
1.
R2R3
R2 + R3
ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 55. Current-Steering DAC Used as a Divider or
Programmable Gain Element
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction, D, of the current into the VREF terminal is
routed to the IOUT1 terminal, the output voltage has to change
as follows:
Figure 54. Increasing the Gain of the Current Output DAC
DACS USED AS A DIVIDER OR PROGRAMMABLE
GAIN ELEMENT
Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor, as shown in Figure 55, then the output voltage is
inversely proportional to the digital input fraction, D.
Output Error Voltage due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
For D = 1 – 2–n the output voltage is
V
OUT = –VIN/D = –VIN/(1 – 2–n)
Rev. B | Page 20 of 32
AD5424/AD5433/AD5445
Table 9. Suitable ADI Precision References
Part No. Output Voltage (V) Initial Tolerance (%)
Temp Drift (ppm/°C)
ISS (mA)
Output Noise (μV p-p) Package
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
10
10
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
20
20
10
10
6
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
5
2.5
2.5
3
3
2.5
5
6
10
10
3.5
8
5
8
2.5
5
Table 10. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Noise (μV p-p)
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
2 to 20
2.5 to 15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (μV)
IB (Max) (nA)
Supply Current (μA)
Package
25
60
5
50
5
0.1
2
0.05
0.001
0.1
0.5
0.4
1
2.3
0.5
600
500
975
50
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
850
TSOT, SOIC-8
Table 11. Suitable ADI High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
BW @ ACL (MHz)
Slew Rate (V/μs)
VOS (Max) (μV) IB (Max) (nA)
Package
5 to 24
2.5 to 12
3 to 12
145
490
350
320
180
120
425
1300
1500
1000
3000
10000
6000
10500
750
SOIC-8, SOT-23,MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
3 to 6
7000
REFERENCE SELECTION
of the DAC) of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. In general, the input offset voltage should
be <1/4 LSB to ensure monotonic behavior when stepping
through codes.
When selecting a reference for use with the AD5424/AD5433/
AD5445 family of current output DACs, pay attention to the
reference’s output voltage temperature coefficient specification.
This parameter not only affects the full-scale error, but can also
affect the linearity (INL and DNL) performance. The reference
temperature coefficient should be consistent with the system
accuracy specifications. For example, an 8-bit system required
to hold its overall specification to within 1 LSB over the temp-
erature range 0°C to 50°C dictates that the maximum system
drift with temperature should be less than 78 ppm/°C.
The input bias current of an op amp also generates an offset
at the voltage output as a result of the bias current flowing
into the feedback resistor, RFB. Most op amps have input bias
currents low enough to prevent significant errors in
12-bit applications.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient this error source can be minimized.
Table 9 suggests some references available from Analog Devices
that are suitable for use with this range of current output DACs.
Common-mode rejection of the op amp is important in
voltage-switching circuits, since it produces a code dependent
error at the voltage output of the circuit. Most op amps have
adequate common mode rejection for use at 8-, 10-, and 12-bit
resolution.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code dependent output resistance
Rev. B | Page 21 of 32
AD5424/AD5433/AD5445
Provided the DAC switches are driven from true wideband low
impedance sources (VIN and AGND), they settle quickly. Conse-
quently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is impor-
tant to minimize capacitance at the VREF node (voltage output
node in this application) of the DAC. This is done by using low
inputs capacitance buffer amplifiers and careful board design.
8xC51-to-AD5424/AD5433/AD5445 Interface
Figure 57 shows the interface between the AD5424/AD5433/
AD5445 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to external memory. AD0 to AD7 are the
multiplexed low order addresses and data bus and require
strong internal pull-ups when emitting 1s. During access to
external memory, A8 to A15 are the high order address bytes.
Since these ports are open drained, they also require strong
internal pull-ups when emitting 1s.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. There is a large range of single-supply
amplifiers available from Analog Devices.
A8 TO A15
ADDRESS BUS
PARALLEL INTERFACE
Data is loaded to the AD5424/AD5433/AD5445 in the format
AD5424/
AD5433/
AD5445*
8051*
of an 8-, 10-, or 12-bit parallel word. Control lines
and R/
CS
allow data to be written to or read from the DAC register. A
write event takes place when and R/ are brought low, data
W
ADDRESS
DECODER
CS
CS
available on the data lines fills the shift register, and the rising
edge of latches the data and transfers the latched data-word
W
WR
R/W
CS
to the DAC register. The DAC latches are not transparent, thus
a write sequence must consist of a falling and rising edge on
DB0 TO DB11
8-BIT
LATCH
ALE
CS
AD0 TO AD7
DATA BUS
to ensure that data is loaded to the DAC register and its analog
equivalent is reflected on the DAC output.
*ADDITIONAL PINS OMITTED FOR CLARITY
A read event takes place when R/ is held high and
is
CS
W
Figure 57. 8xC51-to-AD5424/AD5433/AD5445 Interface
brought low. New data is loaded from the DAC register back to
the input register and out onto the data line where it can be read
back to the controller for verification or diagnostic purposes.
ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface
Figure 58 shows a typical interface between the AD5424/
AD5433/AD5445 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5424/AD5433/AD5445 Interface
digital inputs of the DAC. The
x line is actually four
AMS
memory select lines. Internal ADDR lines are decoded into
3-0 , these lines are then inserted as chip selects. The rest of
Figure 56 shows the AD5424/AD5433/AD5445 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5424/
AD5433/AD5445 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family user’s manual for details).
AMS
the interface is a standard handshaking operation.
ADDR TO
1
ADDRESS BUS
ADRR
19
AD5424/
AD5433/
AD5445*
ADSP-BF5xx
AMSx
ADDR TO
0
ADDRESS BUS
ADDRESS
DECODER
ADRR
13
CS
AD5424/
AD5433/
AD5445*
AWE
R/W
ADSP-21xx*
DB0 TO DB11
ADDRESS
DECODER
DMS
CS
WR
R/W
DATA 0 TO
DATA 23
DATA BUS
DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 58. ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface
DATA 0 TO
DATA 23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 56. ADSP21xx-to-AD5424/AD5433/AD5445 Interface
Rev. B | Page 22 of 32
AD5424/AD5433/AD5445
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5424/AD5433/AD5445 is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE
AD5424/AD5433/AD5445
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply, located as close to the
package as possible and ideally right up against the device. The
0.1 μF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
The board consists of a 12-bit AD5445 and a current-to-voltage
amplifier, the AD8065. Included on the evaluation board is a
10 V reference, the ADR01. An external reference may also be
applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software allows the user to
simply write a code to the device.
POWER SUPPLIES FOR EVALUATION BOARD
The board requires 12 V and 5 V supplies. The 12 V VDD
and VSS are used to power the output amplifier, while the
+5 V VDD and VSS are used to power the DAC (VDD1) and
transceivers (VCC).
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A micro-strip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
Both supplies are decoupled to their respective ground plane
with 10 μF tantalum and 0.1 μF ceramic capacitors.
Link1 (LK1) is provided to allow selection between the on-
board reference (ADR01) and an external reference applied
through J2.
component side of the board is dedicated to the ground plane,
while signal traces are placed on the solder side.
Rev. B | Page 23 of 32
AD5424/AD5433/AD5445
Figure 59. Evaluation Board Schematic
Rev. B | Page 24 of 32
AD5424/AD5433/AD5445
P1
C1
R2
R4
C12
DB11
DB9
DB7
DB5
DB3
DB1
U3
DB10
DB8
DB6
DB4
DB2
DB0
U1
J1
OUTPUT
U5
C2
TP1
C7
R5
R1
C6
C5
C4
C3
C8
U2
LK1
CS
RW
EXT
VREF
U4
J4
J2
C18 C14
J3
R3
C16
CS
R/W
C19
C17
C13
C15
P2
C20
EVAL-AD5424/ꢀ
AD5433/AD5445EB
Figure 60. Silkscreen—Component-Side View
Figure 61. Component-Side Artwork
Rev. B | Page 25 of 32
AD5424/AD5433/AD5445
Figure 62. Solder-Side Artwork
Table 12. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board
Name
Part Description
Value
Tolerance
PCB Decal
Stock Code
C1, C2, C4, C6, C8
C10, C12, C13
X7R Ceramic Capacitor
0.1 μF
10%
0603
FEC 499–675
C15
X7R Ceramic Capacitor
0.1 μF
10 μF 20 V
0.1 μF
10 μF 10 V
4.7 pF
10%
10%
10%
10%
10%
0603
CAP\TAJ_B
0603
CAP\TAJ_A
0603
TESTPOINT
TESTPOINT
SMB
FEC 499–675
FEC 197–427
FEC 499–675
FEC 197–130
C3, C5, C9, C11, C14 Tantalum Capacitor, Taj Series
C17, C19
C16, C18, C20
C7
X7R Ceramic Capacitor
Tantalum Capacitor, Taj Series
X7R Ceramic Capacitor
Test Point
Red Test Point
SMB Socket
CS
FEC 240–345 (Pack)
FEC 240–345 (Pack)
FEC 310–682
DB0–DB11
J1–J4
LK1
P1
P2
R1
R2, R3, R4, R5
RW, TP1, TP2
U1
U2
3-Pin Header (3 × 1)
36-Pin Centronics Connector
6-Pin Terminal Block
0.063 W Resistor
0.063 W Resistor
Red Test Point
AD5445
ADR425/ADR01/ADR02/ADR03
AD8065
LINK–3P–
36WAY
CON\POWER6
0603
FEC 511–717 and 150–411
FEC 147–753
FEC 151–792
Not Inserted
FEC 911–355
FEC 240–345 (Pack)
AD5445YRU
ADR01AR
10 kΩ
1%
0603
TESTPOINT
TSSOP20
SO8NB
U3
SO8NB
AD8065AR
U4
U5
74ABT543
74ABT543
Rubber Stick-On Feet
TSSOP24
TSSOP24
Fairchild 74ABT543CMTC
Fairchild 74ABT543CMTC
FEC 148–922
Each Corner
Rev. B | Page 26 of 32
AD5424/AD5433/AD5445
Table 13. Overview of AD54xx and AD55xx Devices
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
No. DACs
INL(LSB)
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package
RU-16, CP-20
RM-10
RU-20
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.25
1
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
50 MHz serial interface
8
8
8
8
RU-10
RJ-8
RM-10
RU-20, CP-20
RU-16
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
RJ-8
RM-10
RM-8
RU-24
CP-40
0.5
1
1
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
1
RU-20, CP-20
RU-24
1
1
0.5
1
2
1
RU-16
RJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
1
1
RM-8
RU-38
2
2
RM-8
RU-28
2
2
RU-16
RU-38
Rev. B | Page 27 of 32
AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
6.60
6.50
6.40
5.10
5.00
4.90
20
11
10
16
9
4.50
4.40
4.30
4.50
4.40
4.30
6.40
BSC
6.40 BSC
1
1
8
PIN 1
0.65
BSC
PIN 1
1.20
MAX
1.20 MAX
0.15
0.05
0.20
0.09
0.15
0.05
0.75
0.60
0.45
0.20
0.09
8°
0°
0.75
0.60
0.45
0.30
0.19
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
0.65
BSC
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
COPLANARITY
0.10
Figure 64. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
3.75
BCS SQ
EXPOSED
PAD
(BOTTOM VIEW)
10
6
11
0.75
0.60
0.50
0.25 MIN
TOP VIEW
0.80 MAX
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.65 TYP
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
Rev. B | Page 28 of 32
AD5424/AD5433/AD5445
ORDERING GUIDE
Model
AD5424YRU
AD5424YRU-REEL
AD5424YRU-REEL7
AD5424YRUZ1
AD5424YRUZ-REEL1
AD5424YRUZ-REEL71
AD5424YCP
AD5424YCP-REEL
AD5424YCP-REEL7
AD5424YCPZ-REEL1
AD5424YCPZ-REEL71
AD5433YRU
AD5433YRU-REEL
AD5433YRU-REEL7
AD5433YRUZ1
AD5433YRUZ-REEL1
AD5433YRUZ-REEL71
AD5433YCP
AD5433YCP-REEL
AD5433YCP-REEL7
AD5433YCPZ1
Resolution (Bits)
INL (LSB)
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
Package Option
RU-16
RU-16
RU-16
RU-16
8
8
8
8
8
8
8
8
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
20-Lead LFCSP_VQ
Evaluation Kit
RU-16
RU-16
CP-20-1
CP-20-1
CP-20-1
CP-20-1
CP-20-1
RU-20
RU-20
RU-20
RU-20
RU-20
8
8
8
10
10
10
10
10
10
10
10
10
10
12
12
12
12
12
12
12
12
12
12
RU-20
CP-20-1
CP-20-1
CP-20-1
CP-20-1
RU-20
RU-20
RU-20
RU-20
RU-20
AD5445YRU
AD5445YRU-REEL
AD5445YRU-REEL7
AD5445YRUZ1
AD5445YRUZ-REEL1
AD5445YRUZ-REEL71
AD5445YCP
AD5445YCP-REEL
AD5445YCP-REEL7
AD5445YCPZ1
EVAL-AD5424EBZ1
EVAL-AD5433EBZ1
EVAL-AD5445EBZ1
1
1
1
1
1
1
1
1
RU-20
CP-20-1
CP-20-1
CP-20-1
CP-20-1
1
Evaluation Kit
Evaluation Kit
1 Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
AD5424/AD5433/AD5445
NOTES
Rev. B | Page 30 of 32
AD5424/AD5433/AD5445
NOTES
Rev. B | Page 31 of 32
AD5424/AD5433/AD5445
NOTES
©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03160-0-8/09(B)
Rev. B | Page 32 of 32
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