AD5422BREZ [ADI]
Single Channel, 16-Bit, Serial Input, Current Source & Voltage Output DAC; 单通道， 16位，串行输入，电流源和电压输出DAC
| 型号： | AD5422BREZ |
| 厂家： | 
ADI |
| 描述： | Single Channel, 16-Bit, Serial Input, Current Source & Voltage Output DAC |
| 文件： | 总37页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Channel, 16-Bit, Serial Input,
Current Source & Voltage Output DAC
Preliminary Technical Data
AD5422
FEATURES
GENERAL DESCRIPTION
The AD5422 is a low-cost, precision, fully integrated 16-bit
converter offering a programmable current source and
programmable voltage output designed to meet the
16-Bit Resolution and Monotonicity
Current Output Ranges: 4–20mA, 0–20mA or 0–24mA
0.1% typ Total Unadjusted Error (TUE)
5ppm/°C Output Drift
Voltage Output Ranges: 0-5V, 0-10V, 5V, 10V,
10% over-range
requirements of industrial process control applications.
The output current range is programmable to 4mA to 20 mA,
0mA to 20mA or an overrange function of 0mA to 24mA.
Voltage output is provided from a separate pin that can be
configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V
output ranges, an over-range of 10% is available on all ranges.
Analog outputs are short and open circuit protected and can
drive capacitive loads of 1uF and inductive loads of 1H.
The device is specified to operate with a power supply range
0.05% Total Unadjusted Error (TUE)
3ppm/°C Output Drift
Flexible Serial Digital Interface
On-Chip Output Fault Detection
On-Chip Reference (10 ppm/°C Max)
Asynchronous CLEAR Function
Power Supply Range
from 10.8 V to 40 V. Output loop compliance is 0 V to AVDD
2.5 V.
The flexible serial interface is SPI and MICROWIRE
–
AVDD : 10.8V to 40 V
compatible and can be operated in 3-wire mode to minimize the
digital isolation required in isolated applications.
The device also includes a power-on-reset function ensuring
that the device powers up in a known state and an
asynchronous CLEAR pin which sets the outputs to zero-scale /
mid-scale voltage output or the low end of the selected current
range.
AVSS : -26.4V to -3V/0V
Output Loop Compliance to AVDD – 2.5 V
Temperature Range: -40°C to +85°C
TSSOP and LFCSP Packages
APPLICATIONS
Process Control
Actuator Control
PLC
The total output error is typically ±0.1% in current mode and
±0.05% in voltage mode.
Table 1. Related Devices
Part Number
Description
AD5412
Single Channel, 12-Bit, Serial
Input Current Source and
Voltage Output DAC
AD5420
AD5410
Single Channel, 16-Bit, Serial
Input Current Source DAC
Single Channel, 12-Bit, Serial
Input Current Source DAC
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD5422
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
RESET register............................................................................ 29
Status register.............................................................................. 30
Features............................................................................................ 31
fault alert...................................................................................... 31
voltage output short circuit protection.................................... 31
Asynchronous Clear (CLEAR)................................................. 31
Internal Reference ...................................................................... 31
External current setting resistor............................................... 31
Voltage ouTput over-range........................................................ 31
Digital Power Supply.................................................................. 31
External boost function............................................................. 31
digital Slew rate control............................................................. 32
IOUT Filtering Capacitors............................................................ 32
Applications Information.............................................................. 33
driving inductive loads.............................................................. 33
Transient voltage protection ..................................................... 33
Layout Guidelines....................................................................... 33
Galvanically Isolated Interface ................................................. 33
Microprocessor Interfacing....................................................... 33
Thermal and supply considerations......................................... 34
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 35
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
AC Performance Characteristics................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics Voltage output............... 13
Typical Performance Characteristics current output ............... 17
Typical Performance Characteristics general ............................ 20
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 24
Architecture................................................................................. 24
Serial Interface ............................................................................ 24
Default configuration................................................................. 28
Transfer Function....................................................................... 28
Data Register............................................................................... 29
Control Register.......................................................................... 29
REVISION HISTORY
PrE – Preliminary Version, November 22, 2007
Rev. PrE | Page 2 of 37
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
DVCC
AD5422
DVCC
CAP1
CAP2
AVSS
AVDD
SELECT
AD5422
CLEAR
SELECT
R2
R3
BOOST
CLEAR
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
LATCH
SCLK
SDIN
16
/
16-BIT
DAC
I
OUT
SDO
FAULT
R
SET
R1
POWER
ON
VREF
+VSENSE
RESET
RANGE
V
OUT
SCALING
-VSENSE
DGND*
REFIN
AGND
C
COMP2
C
REFOUT
COMP1
*LFCSP Package
Figure 1.
Rev. PrE | Page 3 of 37
AD5422
Preliminary Technical Data
SPECIFICATIONS
AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DVCC = 2.7 V to 5.5 V, VOUT : RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH;
all specifications TMIN to TMAX, 10 V / 0 to 24 mA range unless otherwise noted.
Table 2.
Parameter
Value1
Unit
Test Conditions/Comments
VOLTAGE OUTPUT
Output Voltage Ranges
0 to 5
0 to 10
-5 to +5
-10 to +10
V
V
V
V
ACCURACY
Bipolar Output
Resolution
Output unloaded
16
Bits
Total Unadjusted Error (TUE)
0.1
% FSR max
Over temperature, supplies, and time, typically 0.05%
FSR
TUE TC2
±3
±0.012
±1
ppm typ
% FSR max
LSB max
mV max
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Bipolar Zero Error
Guaranteed monotonic
@ 25°C, error at other temperatures obtained using
bipolar zero TC
±5
Bipolar Zero TC2
Zero-Scale Error
±3
±1
ppm FSR/°C max
mV max
@ 25°C, error at other temperatures obtained using zero
scale TC
Zero-Scale TC2
Gain Error
±3
±0.05
ppm FSR/°C max
% FSR max
@ 25°C, error at other temperatures obtained using gain
TC
Gain TC2
Full-Scale Error
±±
0.05
ppm FSR/°C max
% FSR max
@ 25°C, error at other temperatures obtained using gain
TC
Full-Scale TC2
±3
ppm FSR/°C max
Unipolar Output
Resolution
AVSS = 0 V
16
Bits
Total Unadjusted Error (TUE)
0.1
% FSR max
Over temperature, supplies, and time, typically 0.05%
FSR
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero Scale Error
±0.012
±1
+10
% FSR max
LSB max
mV max
Guaranteed monotonic (at 16 bit-resolution)
@ 25°C, error at other temperatures obtained using gain
TC
Zero Scale TC2
Offset Error
Gain Error
±3
±10
±0.05
ppm FSR/°C max
mV max
% FSR max
@ 25°C, error at other temperatures obtained using gain
TC
Gain TC2
Full-Scale Error
±3
0.05
ppm FSR/°C max
% FSR max
@ 25°C, error at other temperatures obtained using gain
TC
Full-Scale TC2
OUTPUT CHARACTERISTICS2
Headroom
±3
ppm FSR/°C max
0.±
0.5
±3
±12
±15
12
V max
V typ
ppm FSR/°C max
ppm FSR/500 hr typ
ppm FSR/1000 hr typ
mA typ
Output Voltage TC
Output Voltage Drift vs. Time
Vout = ¾ of Full-Scale
Short-Circuit Current
Rev. PrE | Page 4 of 37
Preliminary Technical Data
AD5422
Parameter
Load
Value1
Unit
Test Conditions/Comments
2
kΩ min
For specified performance
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
20
TBD
1
0.3
10
TBD
nF max
nF max
µF max
Ω typ
µs typ
µV/V
RL = ∞
External compensation capacitor of 4nF connected.
DC Output Impedance
Power-On Time
DC PSRR
CURRENT OUTPUT
Output Current Ranges
0 to 24
0 to 20
4 to 20
mA
mA
mA
ACCURACY
Resolution
16
Bits
Total Unadjusted Error (TUE)
TUE TC2
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Offset Error
±0.3
±5
±0.012
±1
±0.05
±5
±0.02
% FSR max
ppm/°C typ
% FSR max
LSB max
% FSR max
µv/°C typ
% FSR max
Over temperature, supplies, and time, typically 0.1% FSR
Guaranteed monotonic
Offset Error Drift
Gain Error
@ 25°C, error at other temperatures obtained using gain
TC
Gain TC2
Full-Scale Error
±±
0.05
ppm FSR/°C max
% FSR max
@ 25°C, error at other temperatures obtained using gain
TC
Full-Scale TC2
±±
ppm FSR/°C
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage
Output Current Drift vs. Time
AVDD - 2.5
V max
TBD
TBD
TBD
1
ppm FSR/500 hr typ
ppm FSR/1000 hr typ
Ω max
Resistive Load
Inductive Load
H max
DC PSRR
10
µA/V max
Output Impedance
REFERENCE INPUT/OUTPUT
Reference Input2
50
MΩ typ
Reference Input Voltage
DC Input Impedance
Reference Range
5
30
4 to 5
V nom
kΩ min
V min to V max
±1% for specified performance
Typically 40 kΩ
Reference Output
Output Voltage
Reference TC
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Voltage Drift vs. Time2
4.99± to 5.002
±10
1±
120
±40
±50
TBD
5
V min to V max
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
nF max
@ 25°C
@ 10 kHz
Capacitive Load
Load Current
mA typ
Short Circuit Current
Line Regulation2
Load Regulation2
Thermal Hysteresis2
7
10
TBD
TBD
mA typ
ppm/V typ
ppm/mA
ppm
Rev. PrE | Page 5 of 37
AD5422
Preliminary Technical Data
Parameter
Value1
Unit
Test Conditions/Comments
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
DVCC = 2.7 V to 5.5 V, JEDEC compliant
2
V min
0.±
±1
10
V max
µA max
pF typ
Per pin
Per pin
Pin Capacitance
2
DIGITAL OUTPUTS
SDO
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage
Current
0.4
DVCC − 0.5
±1
V max
V min
µA max
sinking 200 µA
sourcing 200 µA
High Impedance Output
Capacitance
5
pF typ
FAULT
VOL, Output Low Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
0.4
0.6
3.6
V max
V typ
V min
10kΩ pull-up resistor to DVCC
@ 2.5 mA
10kΩ pull-up resistor to DVCC
POWER REQUIREMENTS
AVDD
AVSS
10.± to 40
-26.4 to 0
V min to V max
V min to V max
DVCC
Input Voltage
Output Voltage
Output Load Current
Short Circuit Current
AIDD
2.7 to 5.5
4.5
5
V min to V max
V typ
mA typ
mA typ
mA
Internal supply disabled
DVCC can be overdriven up to 5.5V
20
TBD
TBD
1
TBD
TBD
TBD
Output unloaded
Output unloaded
VIH = DVCC, VIL = GND, TBD mA typ
AVDD = 40V, AVSS = 0 V, VOUT unloaded
AVDD = 40V, AVSS = -15 V, VOUT unloaded
AVDD = 15V, AVSS = -15 V, VOUT unloaded
AISS
DICC
mA
mA max
mW typ
mW typ
mW typ
Power Dissipation
1 Temperature range: -40°C to +±5°C; typical at +25°C.
2 Guaranteed by characterization. Not production tested.
Rev. PrE | Page 6 of 37
Preliminary Technical Data
AD5422
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DVCC = 2.7 V to 5.5 V, VOUT : RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH;
all specifications TMIN to TMAX
,
10 V / 0 to 24 mA range unless otherwise noted.
Table 3.
Parameter1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
VOLTAGE OUTPUT
Output Voltage Settling Time
±
µs typ
Full-scale step (10 V) to ±0.03% FSR
10
5
10
1
10
10
20
1
0.1
±0
1
µs max
µs max
µs max
512 LSB step settling
To 0.1% FSR
Output Current Settling Time
Slew Rate
Power-On Glitch Energy
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz Bandwidth)
Output Noise (100 kHz Bandwidth)
1/f Corner Frequency
V/µs typ
nV-sec typ
nV-sec typ
mV typ
nV-sec typ
LSB p-p typ
µV rms max
kHz typ
Output Noise Spectral Density
AC PSRR
100
TBD
nV/√Hz typ
dB
Measured at 10 kHz
200mV 50/60Hz Sinewave
superimposed on power supply voltage.
CURRENT OUTPUT
Output Current Settling Time
TBD
TBD
µs typ
µs typ
To 0.1% FSR , L = 1H
To 0.1% FSR , L < 1mH
1 Guaranteed by characterization, not production tested.
Rev. PrE | Page 7 of 37
AD5422
Preliminary Technical Data
TIMING CHARACTERISTICS
AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DVCC = 2.7 V to 5.5 V, VOUT : RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH;
all specifications TMIN to TMAX, 10 V / 0 to 24 mA range unless otherwise noted.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
Write Mode
t1
t2
t3
t4
t5
t5
t6
t7
33
13
13
13
40
5
5
5
40
20
5
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
µs max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
LATCH high time (After a write to the CONTROL register)
Data setup time
Data hold time
LATCH low time
t±
t9
t10
CLEAR pulsewidth
CLEAR activation time
Readback Mode
t11
t12
t13
t14
t15
t16
t17
t1±
±2
33
33
13
40
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
5
40
40
33
t19
t20
Serial output delay time (CL SDO4 = 15pF)
LATCH rising edge to SDO tri-state
Daisychain Mode
t21
t22
t23
t24
t25
t26
t27
t2±
t29
±2
33
33
13
40
5
5
40
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15pF)
1 Guaranteed by characterization. Not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = Capacitive load on SDO output.
Rev. PrE | Page ± of 37
Preliminary Technical Data
AD5422
t1
SCLK
1
2
24
t3
t2
t4
t5
LATCH
t7
t8
t6
SDIN
DB23
DB0
t9
CLEAR
t10
OUTPUT
Figure 2. Write Mode Timing Diagram
t11
2
1
9
23
SCLK
1
2
24
22
24
8
t13
t12
t14
t15
LATCH
SDIN
t17
t18
t16
DB23
DB0
DB23
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
t20
t19
SDO
X
X
X
X
DB15
DB0
UNDEFINED DATA
FIRST 8 BITS ARE
DON’T CARE BITS
SELECTED REGISTER
DATA CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
t21
26
48
25
SCLK
1
2
24
t23
t22
t24
t25
LATCH
SDIN
t27
t28
t26
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N-1
t29
DB23
DB0
SDO
DB23
DB0
INPUT WORD FOR DAC N
Figure 4. Daisychain Mode Timing Diagram
Rev. PrE | Page 9 of 37
AD5422
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AVDD to AGND, DGND
AVSS to AGND, DGND
AVDD to AVSS
DVCC to AGND, DGND
Digital Inputs to AGND, DGND
−0.3V to 4±V
+0.3 V to −4± V
-0.3V to 60V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
ESD CAUTION
Digital Outputs to AGND, DGND
−0.3 V to DVCC + 0.3 V or 7V
(whichever is less)
REFIN/REFOUT to AGND, DGND
VOUT to AGND, DGND
IOUT to AGND, DGND
−0.3 V to +7 V
AVSS to AVDD
−0.3V to AVDD
-0.3V to +0.3V
AGND to DGND
Operating Temperature Range
Industrial
−40°C to +±51°C
−65°C to +150°C
125°C
Storage Temperature Range
Junction Temperature (TJ max)
24-Lead TSSOP Package
θJA Thermal Impedance
40-Lead LFCSP Package
θJA Thermal Impedance
Power Dissipation
1 Power dissipated on chip must be de-rated to keep junction temperature
below 125°C. Assumption is max power dissipation condition is sourcing
24mA into Ground from AVDD with a 3mA on-chip current.
42°C/W
2±°C/W
(TJ max – TA)/ θJA
JEDEC Industry Standard
J-STD-020
Lead Temperature
Soldering
Rev. PrE | Page 10 of 37
Preliminary Technical Data
AD5422
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AV
AV
DV
1
2
3
4
5
6
7
8
9
24
23
22
21
DD
SS
-VSENSE
+VSENSE
40 39 38 37 36 35 34 33 32 31
CC
NC
FAULT
1
2
30
29
28
27
26
25
24
23
22
AD5422
NC
FAULT
GND
CAP2
CAP1
V
OUT
GND
3
20 BOOST
CLEAR SELECT
CLEAR
CLEAR SELECT
CLEAR
LATCH
SCLK
4
BOOST
TOP VIEW
(Not to Scale)
I
19
18
17
16
5
I
OUT
OUT
AD5422
TOP VIEW
(Not to Scale)
6
C
C
COMP2
COMP1
C
LATCH
COMP2
7
C
SCLK
COMP1
SDIN
8
DVCC SELECT
NC
DV
SELECT
SDIN
CC
SDO
9
15 REFIN
14 REFOUT
SDO 10
NC
10
21 NC
11 12 13 14 15 16 17 18 19 20
11
12
AGND
GND
R
13
SET
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
TSSOP Pin No. LFCSP Pin No. Mnemonic
Description
1
14,37
AVSS
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.
2
3
39
2
DVCC
FAULT
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Fault alert, This pin is asserted low when an open circuit is detected in current mode or
an over temperature is detected. Open drain output, must be connected to a pull-up
resistor.
4,12
3,15
GND
NC
These pins must be connected to 0V.
No Connection.
1,10,11,19,
20,21,22,30,
31,35,3±,40
4
5
6
CLEAR
SELECT
CLEAR
Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 20
5
Active High Input. Asserting this pin will set the current output to the bottom of the
selected range or will set the voltage output to the user selected value (zero-scale or
mid-scale).
7
±
6
7
LATCH
SCLK
Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds up to 30 MHz.
9
10
±
9
SDIN
SDO
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is clocked out on the falling edge of SCLK . See Figure 3 and Figure 4.
11
N/A
12
13
AGND
DGND
Ground reference pin for analog circuitry.
Ground reference pin for digital circuitry. (AGND and DGND are internally connected in
TSSOP package).
13
16
RSET
An external, precision, low drift 15kΩ current setting resistor can be connected to this
pin to improve the IOUT temperature drift performance. Refer to Features section.
14
15
17
1±
REFOUT
REFIN
Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for
specified performance.
16
23
DVCC
SELECT
This pin when connected to GND disables the internal supply and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. Refer to features section.
17
1±
24
25
CCOMP1
CCOMP2
Optional compensation capacitor connection for the voltage output buffer. Connecting
a 4nF capacitor between these pins will allow the voltage output to drive up to 1µF.
Rev. PrE | Page 11 of 37
AD5422
Preliminary Technical Data
TSSOP Pin No. LFCSP Pin No. Mnemonic
Description
19
20
26
27
IOUT
BOOST
Current output pin.
Optional external transistor connection. Connecting an external transistor will reduce
the power dissipated in the AD5422. Refer to the features section.
N/A
N/A
21
2±
29
32
CAP1
CAP2
VOUT
Connection for optional output filtering capacitor. Refer to Features section.
Connection for optional output filtering capacitor. Refer to Features section.
Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 2
kΩ, 2000 pF load.
22
23
24
33
34
36
+VSENSE
-VSENSE
AVDD
Sense connection for the positive voltage output load connection.
Sense connection for the negative voltage output load connection.
Positive Analog Supply Pin. Voltage ranges from 10.±V to 60V.
Paddle
Paddle
AVSS
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.
Rev. PrE | Page 12 of 37
Preliminary Technical Data
AD5422
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUT
Figure 7. Integral Non Linearity Error vs DAC Code (Four Traces)
Figure 10. Integral Non Linearity vs. Temperature (Four Traces)
Figure 8. Differential Non Linearity Error vs. DAC Code (Four Traces)
Figure 11. Differential Non Linearity vs. Temperature (Four Traces)
Figure 9. Total Unadjusted Error vs. DAC Code (Four Traces)
Figure 12. Integral Non Linearity vs. Supply Voltage (Four Traces)
Rev. PrE | Page 13 of 37
AD5422
Preliminary Technical Data
Figure 13.Differential Non Linearity Error vs. Supply Voltage (Four Traces)
Figure 14. Integral Non Linearity Error vs. Reference Voltage (Four traces)
Figure 15. Differential Non Linearity Error vs. Reference Voltage (Four Traces)
Figure 16. Total Unadjusted Error vs.Reference Voltage (Four Traces)
Figure 17. Total Unadjusted Error vs. Supply Voltage (Four Traces)
Figure 18. Offset Error vs.Temperature
Rev. PrE | Page 14 of 37
Preliminary Technical Data
AD5422
Figure 19. Bipolar Zero Error vs. Temperature
Figure 22. Source and Sink Capability of Output Amplifier
Zero-Scale Loaded
Figure 20. Gain Error vs. Temperature
Figure 23.Full-Scale Positive Step
Figure 21. Source and Sink Capability of Output Amplifier
Full-Scale Code Loaded
Figure 24. Full-Scale Negative Step
Rev. PrE | Page 15 of 37
AD5422
Preliminary Technical Data
Figure 25. Digital-to-Analog Glitch Energy
Figure 28. VOUT vs. Time on Power-up
Figure 26. Peak-to-Peak Noise (0.1Hz to 10Hz Bandwidth)
Figure 29. VOUT vs, Time on Output Enabled
Figure 27. Peak-to-Peak Noise (100kHz Bandwidth)
Rev. PrE | Page 16 of 37
Preliminary Technical Data
AD5422
TYPICAL PERFORMANCE CHARACTERISTICS
CURRENT OUTPUT
Figure 30. Integral Non Linearity vs. Code
Figure 31.Differential Non Linearity vs. Code
Figure 32. Total Unadjusted Error vs. Code
Figure 33. Integral Non Linearity vs. Temperature
Figure 34. Differential Non Linearity vs. Temperature
Figure 35. Integral Non Linearity vs. Supply
Rev. PrE | Page 17 of 37
AD5422
Preliminary Technical Data
Figure 36. Differential Non Linearity vs. Supply Voltage
Figure 39. Total Unadjusted Error vs. Reference Voltage
Figure 40. Total Unadjusted Error vs. Supply Voltage
Figure 41. Offset Error vs. Temperature
Figure 37. Integral Non Linearity vs. Reference Voltage
Figure 38. Differential Non Linearity vs. Reference Voltage
Rev. PrE | Page 1± of 37
Preliminary Technical Data
AD5422
Figure 42. Gain Error vs. Temperature
Figure 44. IOUT vs. Time on Power-up
Figure 43. Voltage Compliance vs. Temperature
Figure 45. IOUT vs. Time on Output Enabled
Rev. PrE | Page 19 of 37
AD5422
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
GENERAL
Figure 46. DICC vs.Logic Input Voltage
Figure 47. AIDD/AISS vs AVDD/AVSS
Figure 48. AIDD vs AVDD
Figure 49. DVCC Output Voltage vs. DICC Load Current
Figure 50. Refout Turn-on Transient
Figure 51. Refout Output Noise (0.1Hz to 10Hz Bandwidth)
Rev. PrE | Page 20 of 37
Preliminary Technical Data
AD5422
Figure 52. Refout Output Noise (100kHz Bandwidth)
Figure 55. Refout Histogram of Thermal Hysteresis
Figure 53. Refout Line Transient
Figure 56. Refout Voltage vs. Load Current
Figure 54. Refout Load Transient
Rev. PrE | Page 21 of 37
AD5422
Preliminary Technical Data
TERMINOLOGY
Slew Rate
Relative Accuracy or Integral Nonlinearity (INL)
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage-
output D/A converter is usually limited by the slew rate of the
amplifier used at its output. Slew rate is measured from 10% to
90% of the output signal and is given in V/µs.
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 7.
Differential Nonlinearity (DNL)
Gain Error
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 10.
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % FSR. A plot of gain error vs. temperature can be
seen in Table TBD
Gain TC
This is a measure of the change in gain error with changes in
temperature. Gain Error TC is expressed in ppm FSR/°C.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5724R/
AD5734R/AD5754R are monotonic over their full operating
temperature range.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account, namely INL error,
offset error, gain error, and output drift over supplies,
temperature, and time. TUE is expressed in % FSR.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Table TBD.
Current Loop Voltage Compliance
The maximum voltage at the IOUT pin for which the output
currnet will be equal to the programmed value.
Power-On Glitch Energy
Bipolar Zero TC
Power-on glitch energy is the impulse injected into the analog
output when the AD5422 is powered-on. It is specified as the area
of the glitch in nV-sec. See Table TBD
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm
FSR/°C.
Digital-to-Analog Glitch Impulse
Full-Scale Error
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LSB at the major
carry transition (0x7FFF to 0x8000). See Table TBD
Full-Scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% FSR).
Negative Full-Scale Error/Zero-Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (straight binary coding) or 0x8000 (twos
complement coding) is loaded to the DAC register. Ideally, the
output voltage should be negative full-scale − 1 LSB. A plot of
zero-scale error vs. temperature can be seen in Table TBD
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Table TBD.
Zero-Scale TC
This is a measure of the change in zero-scale error with a change in
temperature. Zero-scale error TC is expressed in ppm FSR/°C.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. A plot of settling time can be seen in Table TBD
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage.
Reference TC
Rev. PrE | Page 22 of 37
Preliminary Technical Data
AD5422
Reference TC is a measure of the change in the reference output
voltage with a change in temperature. It is expressed in ppm/°C.
−40°C to +85°C and back to +25°C. This is a typical value from
a sample of parts put through such a cycle. See Table TBDfor a
histogram of thermal hysteresis.
Line Regulation
VO _ HYS = VO (25°C) −VO _TC
VO (25°C) −VO _TC
Line regulation is the change in reference output voltage due to
a specified change in supply voltage. It is expressed in ppm/V.
V
O _ HYS (ppm) =
×106
Load Regulation
VO (25°C)
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.
where:
VO(25°C) = VO at 25°C
O_TC = VO at 25°C after temperature cycle
Thermal Hysteresis
V
Thermal hysteresis is the change of reference output voltage
after the device is cycled through temperatures from +25°C to
Rev. PrE | Page 23 of 37
AD5422
Preliminary Technical Data
THEORY OF OPERATION
+VSENSE
The AD5422 is a precision digital to current loop and voltage
output converter designed to meet the requirements of
industrial process control applications. It provides a high
precision, fully integrated, low cost single-chip solution for
generating current loop and unipolar/bipolar voltage outputs.
The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to
20mA, the voltage ranges available are; 0 to 5V, 5V, 0 to 10V
and 10V, the current and voltage outputs are available on
separate pins and only one is active at any one time. The desired
output configuration is user selectable via the CONTROL
register.
R1
V
OUT
RANGE
SCALING
16-BIT
DAC
RL
-VSENSE
±3V
REFIN
Figure 59. Voltage Output
Voltage Output Amplifier
The voltage output amplifier is capable of generating both
ARCHITECTURE
The DAC core architecture of the AD5422 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 57. The 4 MSBs of the 16-bit data word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects 1
of 15 matched resistors to either ground or the reference buffer
output. The remaining 12 bits of the data-word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
unipolar and bipolar output voltages. It is capable of driving a
load of 2 kΩ in parallel with 1 µF to AGND. The source and
sink capabilities of the output amplifier can be seen in Figure
TBD. The slew rate is 1 V/µs with a full-scale settling time of 10
µs, (10V step). Figure 59 shows the voltage output drving a load,
RL on top of a common mode voltage of up to 3V.
In output module applications where a cable could possibly
become disconnected from +VSENSE resulting in the amplifier
loop being broken and most probably resulting in large
destructive voltages on VOUT, a resistor, R1, of value 2kΩ to 5kΩ
should be included as shown to ensure the amplifier loop is kept
closed.
R
R
V
OUT
2R
2R
S1
2R
S11
2R
E1
2R
E2
2R
2R
S0
E15
V
REF
Driving Large Capacitive Loads
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
The voltage output amplifier is capable of driving capacitive
loads of up to 1uF with the addition of a non-polarised 4nF
compensation capacitor between the CCOMP1 and CCOMP2 pins.
Without the compensation capacitor, up to 20nF capacitive
loads can be driven.
Figure 57. DAC Ladder Structure
The voltage output from the DAC core is either converted to a
current (see diagram, Figure 58) which is then mirrored to the
supply rail so that the application simply sees a current source
output with respect to ground or it is buffered and scaled to
output a software selectable unipolar or bipolar voltage range
(See diagram, Figure 59). The current and voltage are output on
separate pins and cannot be output simultaneously.
Reference Buffers
The AD5422 can operate with either an external or internal
reference. The reference input has an input range of 4 V to 5 V,
5 V for specified performance. This input voltage is then buffered
before it is applied to the DAC.
AVDD
SERIAL INTERFACE
R2
R3
The AD5422 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP standards.
T2
A2
16-BIT
DAC
T1
Input Shift Register
A1
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of
SCLK. The input register consists of 8 control bits and 16 data
bits as shown in Table 7. The 24 bit word is unconditionally
latched on the rising edge of LATCH. Data will continue to be
clocked in irrespective of the state of LATCH, on the rising edge
of LATCH the data that is present in the input register will be
latched, in other words the last 24 bits to be clocked in before
I
OUT
R1
Figure 58. Voltage to Current conversion circuitry
Rev. PrE | Page 24 of 37
Preliminary Technical Data
AD5422
the rising edge of LATCH will be the data that is latched. The
timing diagram for this operation is shown in Figure 2.
Rev. PrE | Page 25 of 37
AD5422
Preliminary Technical Data
Table 7. Input Shift Register Format
MSB
LSB
D22 D21 D20 D19 D1± D17 D16 D15 D14 D13 D12 D11 D10 D9 D± D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS WORD DATA WORD
D23
AD5422*
CONTROLLER
Table 8. Control Word Functions
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDIN
Address
Word
Function
SCLK
00000000
00000001
00000010
No Operation (NOP)
DATA Register
Readback register value as per Read Address
(See Table 10)
LATCH
DATA IN
SDO
01010101
01010110
CONTROL Register
RESET Register
SDIN
AD5422*
SCLK
LATCH
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The first rising edge of SCLK that clocks in the MSB of the
dataword marks the beginning ot the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24th rising
SCLK edge, the data written will be invalid. If more than 24
rising SCLK edges are applied before LATCH is brought high,
the input data will also be invalid.
SDO
SDIN
AD5422*
SCLK
LATCH
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 60. Daisy Chaining the AD5422
Rev. PrE | Page 26 of 37
Preliminary Technical Data
AD5422
Daisy-Chain Operation
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together as shown in Figure
60. This daisy-chain mode can be useful in system diagnostics
and in reducing the number of serial interface lines. Daisychain
mode is enabled by setting the DCEN bit of the CONTROL
register. The first rising edge of SCLK that clocks in the MSB of
the dataword marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than 24
clock pulses are applied, the data ripples out of the shift register
and appears on the SDO line. This data is clocked out on the
falling edge of SCLK and is valid on the next rising edge. By
connecting the SDO of the first device to the SDIN input of the
next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 × N, where N is
the total number of AD5422 devices in the chain. When the
serial transfer to all devices is complete, LATCH is taken high.
This latches the input data in each device in the daisy chain.
The serial clock can be a continuous or a gated clock.
Readback Operation
Readback mode is invoked by setting the control word and read
address as shown in Table 9 and Table 10 when writing to the
input register. The next write to the AD5422 should be a NOP
command which will clock out the data from the previously
addressed register as shown in Figure 3.
By default the SDO pin is disabled, after having addressed the
AD5422 for a read operation, a rising edge on LATCH will
enable the SDO pin in anticipation of data being clocked out,
after the data has been clocked out on SDO, a rising edge on
LATCH will disable (tri-state) the SDO pin once again.
To read back the data register for example, the following
sequence should be implemented:
1. Write 0x020001 to the AD5422 input register. This
configures the part for read mode with the data register
selected.
2. Follow this with a second write, a NOP condition, 0x000000
During this write, the data from the register is clocked out
on the SDO line.
A continuous SCLK source can only be used if LATCH is taken
high after the correct number of clock cycles. In gated clock
Table 9. Input Shift Register Contents for a read operation
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
Address
0
0
0
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 10. Read Address Decoding
Read Address
Function
00
01
10
Read Status Register
Read Data Register
Read Control Register
Rev. PrE | Page 27 of 37
AD5422
Preliminary Technical Data
V
REFIN is the reference voltage applied at the REFIN pin.
DEFAULT CONFIGURATION
Gain is an internal gain whose value depends on the output
range selected by the user as shown in Table 11.
On initial power-up of the AD5422 the power-on-reset circuit
ensures that all registers are loaded with zero-code, as such the
default output is the current output with the 4mA to 20mA
range selected, the current output until a value is programmed
is 0mA. The voltage output pin will be in three-state. An
alternative current range or a voltage output range may be
selected via the CONTROL register.
Table 11.
Output Range
Gain Value
+5 V
+10 V
±5 V
±10 V
1
2
2
4
TRANSFER FUNCTION
Voltage Output
Current Output
For the 0 to 20mA, 0 to 24mA and 4 to 20mA current output
ranges the output current expressions are respectively given by
For a unipolar voltage output range, the output voltage
expression is given by
20mA
⎡
⎤
D
2
⎡
⎤
IOUT
=
=
× D
× D
VOUT =VREFIN ×Gain
2N
⎢
⎣
⎥
⎦
N
⎢
⎣
⎥
⎦
For a bipolar voltage output range, the output voltage
expression is given by
24mA
2N
⎡
⎤
IOUT
⎢
⎣
⎥
⎦
16mA
⎡
⎤
Gain ×VREFIN
D
2
⎡
⎤
IOUT
=
× D + 4mA
VOUT =VREFIN ×Gain
−
2N
N
⎢
⎥
⎦
⎢
⎣
⎥
⎦
2
⎣
where:
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
Rev. PrE | Page 2± of 37
Preliminary Technical Data
AD5422
DATA REGISTER
The DATA register is addressed by setting the control word of the input shift register to 0x01. The data to be written to the DATA register
is entered in positions D15 to D0 as shown in Table 12,
Table 12. Programming the Data Register
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DATA WORD
CONTROL REGISTER
The CONTROL register is addressed by setting the control word of the input shift register to 0x55. The data to be written to the
CONTROL register is entered in positions D15 to D0 as shown in Table 13. The CONTROL register functions are shown in Table 14.
Table 13. Programming the CONTROL Register
MSB
LSB
D0
R0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
CLRSEL
OVRRNG
REXT
OUTEN
SR CLOCK
SR STEP
SREN
DCEN
R2
R1
Table 14. Control Register Functions
Option
Description
Table 15. Output Range Options
CLRSEL
See Table 20 for a description of the CLRSEL
operation
Setting this bit increases the voltage output
range by 10%. Further details in Features
section
Setting this bit selects the external current
setting resistor, Further details in Features
section
Output enable. This bit must be set to enable
the outputs, The range bits select which output
will be functional.
R2
R1
R0
Output Range Selected
0 to +5V Voltage Range
0 to 10V Voltage Range
±5V Voltage Range
0
0
0
0
0
1
0
1
0
OVRRNG
REXT
0
1
1
±10V Voltage Range
1
1
1
0
1
1
1
0
1
4 to 20 mA Current Range
0 to 20 mA Current Range
0 to 24 mA Current Range
OUTEN
SR CLOCK
SR STEP
SREN
See Features Section. Digital Slew Rate Control
See Features Section. Digital Slew Rate Control
Digital Slew Rate Control enable
Daisychain enable
DCEN
R2,R1,R0
Output range select. See Table 15
RESET REGISTER
The RESET register is addressed by setting the control word of the input shift register to 0x56. The data to be written to the RESET
register is entered in positions D15 to D0 as shown in Table 16. The RESET register options are shown in Table 16 and Table 17.
Table 16. Programming the RESET Register
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
RESET
Table 17. RESET register Functions
Option Description
RESET
Setting this bit performs a reset operation, restoring the AD5422 to its initial power on state
Rev. PrE | Page 29 of 37
AD5422
Preliminary Technical Data
STATUS REGISTER
The STATUS register is a read only register. The STATUS register functionality is shown in Table 18 and Table 19.
Table 18. Decoding the STATUS Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8 D7
D6 D5
D4
D3
D2
D1
D0
OVER TEMP
IOUT FAULT
SLEW ACTIVE
Table 19. STATUS Register Functions
Option
Description
IOUT FAULT
SLEW ACTIVE
OVER TEMP
This bit will be set if a fault is detected on the IOUT pin.
This bit will be set while the output value is slewing (slew rate control enabled)
This bit will be set if the AD5422 core temperature exceeds approx. 150°C.
Rev. PrE | Page 30 of 37
Preliminary Technical Data
AD5422
FEATURES
FAULT ALERT
Table 20. CLEAR SELECT Options
CLR SELECT
Output CLR Value
The AD5422 is equipped with a FAULT pin, this is an open-
drain output allowing several AD5422 devices to be connected
together to one pull-up resistor for global fault detection. The
FAULT pin is forced active by any one of the following fault
scenarios;
Unipolar Output Range Bipolar Output Range
0
1
0 V
Mid-Scale
0 V
Negative Full-Scale
1) The Voltage at IOUT attempts to rise above the
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The IOUT current is
controlled by a PMOS transistor and internal
amplifier as shown in Figure 58. The internal circuitry
that develops the fault output avoids using a
INTERNAL REFERENCE
The AD5422 contains an integrated +5V voltage reference with
initial accuracy of 2mV max and a temperature drift
coefficient of 10 ppm max. The reference voltage is buffered
and externally available for use elsewhere within the system. See
Figure 56 for a load regulation graph of the Integrated reference.
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approxiamately one volt of remaining drive
capability (when the gate of the output PMOS
transistor nearly reaches ground). Thus the FAULT
output activates slightly before the compliance limit is
reached. Since the comparison is made within the
feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain and an
output error does not occur before the FAULT output
becomes active.
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 58, R1 is an internal sense resistor as part of
the voltage to current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of R1. As a method of improving the stability of the
output current over temperature an external precision 15kΩ low
drift resistor can be connected to the RSET pin of the AD5422 to
be used instead of the internal resistor R1. The external resistor
is selected via the CONTROL register. See Table 13.
VOLTAGE OUTPUT OVER-RANGE
An over-range facility is provided on the voltage output. When
enabled via the CONTROL register, the selected output range
will be over-ranged by 10%.
2) If the core temperature of the AD5422 exceeds approx.
150°C.
DIGITAL POWER SUPPLY
The OPEN CCT and OVER TEMP bits of the STATUS register
are used in conjunction with the FAULT pin to inform the user
which one of the fault conditions caused the FAULT pin to be
asserted. See Table 18 and Table 19.
By default the DVCC pin accepts a power supply of 2.7V to 5.5V,
alternatively, via the DVCC SELECT pin an internal 4.5V power
supply may be output on the DVCC pin for use as a digital power
supply for other devices in the system or as a termination for
pull-up resistors. This facility offers the advantage of not having
to bring a digital supply across an isolation barrier. The internal
power supply is enabled by leaving the DVCC SELECT pin
unconnected. To disable the internal supply DVCC SELECT
should be tied to 0V.
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation the voltage output will sink/source
5mA and maintain specified operation. The maximum current
that the voltage output will deliver is 10mA, this is the short
circuit current.
ASYNCHRONOUS CLEAR (CLEAR)
EXTERNAL BOOST FUNCTION
CLEAR is an active high clear that allows the voltage output to
be cleared to either zero-scale code or mid-scale code, user-
selectable via the CLEAR SELECT pin or the CLRSEL bit of the
CONTROL register as described in Table 20. (The Clear select
feature is a logical OR function of the CLEAR SELECT pin and
the CLRSEL bit). The Current output will clear to the bottom of
its programmed range. It is necessary to maintain CLEAR high
for a minimum amount of time (see Figure 2) to complete the
operation. When the CLEAR signal is returned low, the output
remains at the cleared value until a new value is programmed.
The addition of an external boost transistor as shown in Figure
61 will reduce the power dissipated in the AD5422 by reducing
the current flowing in the on-chip output transistor (dividing it
by the current gain of the external circuit). A discrete NPN
transistor with a breakdown voltage, BVCEO, greater than 60V
can be used.
The external boost capability has been developed for those
users who may wish to use the AD5422 at the extremes of the
supply voltage, load current and temperature range. The boost
transistor can also be used to reduce the amount of temperature
induced drift in the part. This will minimise the temperature
induced drift of the on-chip voltage reference, which improves
drift and linearity.
Rev. PrE | Page 31 of 37
AD5422
Preliminary Technical Data
MJD31C
OR
PBSS8110Z
Table 22. Slew Rate Step Size Options
BOOST
SR STEP
Step Size (LSBs)
AD5422
000
001
1
2
I
OUT
010
4
011
100
101
110
±
1k
R
LOAD
0.022
F
16
32
64
12±
Figure 61. External Boost Configuration
111
DIGITAL SLEW RATE CONTROL
The Slew Rate Control feature of the AD5422 allows the user to
control the rate at which the output value changes. This feature
is available on both the current and voltage outputs. With the
slew rate control feature disabled the output value will change at
a rate limited by the output drive circuitry and the attached
load. If the user wishes to reduce the slew rate this can be
achieved by enabling the slew rate control feature.With the
feature enabled via the SREN bit of the CONTROL register, (See
Table 13) the output, instead of slewing directly between two
values, will step digitally at a rate defined by two parameters
accessible via the CONTROL register as shown in Table 13. The
parameters are SR CLOCK and SR STEP. SR CLOCK defines
the rate at which the digital slew will be updated, e.g. if the
selected update rate is 1MHz the output will update every 1µs,
SR STEP defines by how much the output value will change at
each update. Together both parameters define the rate of change
of the output value.Table 21 and Table 22 outline the range of
values for both the SR CLOCK and SR STEP parameters.
The following equation describes the slew rate as a function of
the step size, the update clock frequency and the LSB size.
StepSize×UpdateClockFrequency× LSBSize
SlewRate =
1×106
Where:
Slew Rate is expressed in A/µs For IOUT or V/µs for VOUT
LSBSize = Fullscale Range / 65536
When the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, i.e. if the
CLEAR pin is asserted the output will slew to the clear value at
the programmed slew rate. The output can be halted at its
current value with a write to the CONTROL register. To avoid
halting the output slew, the SLEW ACTIVE bit can be used to
check that the slew has completed before writing to the AD5422
registers. See Table 18.
Table 21. Slew Rate Update Clock Options
SR CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)
IOUT FILTERING CAPACITORS
1000000
500000
333333
250000
200000
100000
50000
33333
25000
20000
12500
10000
±333
Two capacitors may be placed between the pins CAP1, CAP2
and AVDD as shown in Figure 62. The capacitors form a filter on
the current output circuitry reducing the bandwidth and the
rate of change of the output current.
AVDD
C1
C2
AVDD
CAP1
AD5422 CAP2
I
OUT
6666
5000
3921
AGND
Figure 62. IOUT Filtering Capacitors
Rev. PrE | Page 32 of 37
Preliminary Technical Data
AD5422
APPLICATIONS INFORMATION
avoid radiating noise to other parts of the board and should
DRIVING INDUCTIVE LOADS
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because it
couples through to the DAC output.
When driving inductive or poorly defined loads connect a
0.01µF capacitor between IOUT and GND. This will ensure
stability with loads beyond 50mH. There is no maximum
capacitance limit. The capacitive component of the load may
cause slower settling, though this may be masked by the settling
time of the AD5422.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
TRANSIENT VOLTAGE PROTECTION
The AD5422 contains ESD protection diodes which prevent
damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. In order to protect the AD5422 from excessively high
voltage transients , external power diodes and a surge current
limiting resistor may be required, as shown in Figure 63. The
constraint on the resistor value is that during normal operation
the output level at IOUT must remain within its voltage
compliance limit of AVDD – 2.5V and the two protection diodes
and resistor must have appropriate power ratings.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur. The
iCoupler® family of products from Analog Devices provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5422 make it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 64 shows
a 4-channel isolated interface to the AD5422 using an
ADuM1400. For further information, visit
AV
DD
AV
DD
R
P
AD5422
I
OUT
AGND
R
LOAD
http://www.analog.com/icouplers.
Figure 63. Output Transient Voltage Protection
Controller
LAYOUT GUIDELINES
ADuM1400 *
V
V
V
V
V
OA
IA
IB
IC
ID
To SCLK
Serial Clock Out
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5422 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5422 is in a system where multiple devices
require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device.
V
V
OB
To SDIN
Serial Data Out
SYNC Out
OC
To LATCH
To CLEAR
V
OD
Control out
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 64. Isolated Interface
The AD5422 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The 10
µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5422 is via a serial bus that
uses protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a latch signal. The AD5422 require a 24-bit data-word with
data valid on the rising edge of SCLK.
For all interfaces, the DAC output update is initiated on the
rising edge of LATCH. The contents of the registers can be read
using the readback function.
The power supply lines of the AD5422 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
Rev. PrE | Page 33 of 37
AD5422
Preliminary Technical Data
At maximum ambient temperature of 85°C the 24-lead TSSOP
package can dissipate 950mW and the 40-lead LFCSP package
can dissipate 1.42W.
To ensure the junction temperature does not exceed 125°C
while driving the maximum current of 24mA directly into
ground (also adding an on-chip current of 3mA), AVDD should
be reduced from the maximum rating to ensure the package is
not required to dissipate more power than stated above. See
Table 23, Figure 65 and Figure 66.
THERMAL AND SUPPLY CONSIDERATIONS
The AD5422 is designed to operate at a maximum junction
temperature of 125°C. It is important that the device is not
operated under conditions that will cause the junction
temperature to exceed this value . Excessive junction
temperature can occur if the AD5422 is operated from the
maximum AVDD and driving the maximum current (24mA)
directly to ground. In this case the ambient temperature should
be controlled or AVDD should be reduced. The conditions will
depend on the device package.
2.5
45
TSSOP
TSSOP
LFCSP
43
LFCSP
2
41
39
37
35
33
31
29
27
25
1.5
1
0.5
0
40
45
50
55
60
65
70
75
80
85
25
35
45
55
65
75
85
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 65. Maximum Power Dissipation Vs Ambient Temperature
Figure 66. Maximum Supply Voltage Vs Ambient Temperature
Table 23. Thermal and Supply considerations for each package
TSSOP
LFCSP
Maximum allowed power dissipation
when operating at an ambient
temperature of ±5°C
T
max− T
125 − 85
T
max− T
A
125 − 85
J
A
J
=
= 950mW
=
= 1.42W
Θ
42
Θ
28
JA
JA
Maximum allowed ambient
temperature when operating from a
supply of 60V and driving 24mA
directly to ground.
T
max− P × Θ
= 125 −
40 × 0.027
)
× 42 = 79°C
T max− P × Θ = 125−
(
40× 0.027
)
× 28 > 85°C
J
D
JA
J
D
JA
Maximum allowed supply voltage
when operating at an ambient
temperature of ±5°C and driving 24mA
directly to ground.
T
max− T
125 − 85
T
max− T
A
125 − 85
J
A
J
=
= 35V
=
= 53V
AI
× Θ
0.027 × 42
AI
× Θ
JA
0.027 × 28
DD
JA
DD
Rev. PrE | Page 34 of 37
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5422
5.02
5.00
4.95
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
3.25
3.20
3.15
EXPOSED
PAD
(Pins Up)
6.40 BSC
1
BOTTOM VIEW
TOP VIEW
1.20 MAX
1.05
1.00
0.80
8°
0°
0.20
0.09
0.15
0.05
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 67. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BCS SQ
EXPOSED
PAD
(BOT TOM VIEW)
0.50
0.40
0.30
21
10
11
20
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 68. 40-Lead Lead Frame Chip Scale Package
(CP-40)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5422BREZ
AD5422BCPZ
Temperature Range
-40°C to ±5°C
-40°C to ±5°C
Package Description
24 Lead TSSOP_EP
40 Lead LFCSP
Package Option
RE-24
CP-40
Rev. PrE | Page 35 of 37
AD5422
NOTES
Preliminary Technical Data
Rev. PrE | Page 36 of 37
Preliminary Technical Data
NOTES
AD5422
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06996-0-11/07(PrE)
Rev. PrE | Page 37 of 37
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