AD5381BSTZ-3_技术文档

40-Channel, 3 V/5 V, Single-Supply,

12-Bit, denseDAC

Data Sheet

AD5381

FEATURES

INTEGRATED FUNCTIONS

Guaranteed monotonic

Channel monitor

INL error: ±± LSB max

Simultaneous output update via LDAC

Clear function to user-programmable code

Amplifier boost mode to optimize slew rate

User-programmable offset and gain adjust

Toggle mode enables square wave generation

Thermal monitors

On-chip ±.25 V/2.5 V, ±0 ppm/°C reference

Temperature range: –40°C to +85°C

Rail-to-rail output amplifier

Power-down

Package type: ±00-lead LQFP (±4 mm × ±4 mm)

User interfaces

APPLICATIONS

Parallel

Variable optical attenuators (VOAs)

Level setting (ATE)

Optical micro-electro-mechanical systems (MEMs)

Control systems

Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,

featuring data readback)

I²C®-compatible

Robust 6.5 kV HBM and 2 kV FICDM ESD rating

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

DVDD (×3)

DGND (×3)

AVDD (×5)

AGND (×5)

DAC_GND (×5)

REFGND

REFOUT/REFIN SIGNAL_GND (×5)

PD

SER/PAR

AD5381

1.25V/2.5V

REFERENCE

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

12

INPUT

REG0

DAC

REG0

DAC 0

VOUT0

DB11/(DIN/SDA)

12

m REG0

c REG0

DB10/(SCLK/SCL)

FIFO

+

STATE

MACHINE

+

2

DB9/(SPI/I C)

R

DB8

INTERFACE

CONTROL

LOGIC

12

INPUT

REG1

DAC

REG1

DAC 1

DB0

CONTROL

LOGIC

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

12

A5

A0

m REG1

c REG1

REG0

REG1

RESET

BUSY

CLR

12

INPUT

REG6

DAC

REG6

DAC 6

POWER-ON

RESET

12

m REG6

c REG6

12

INPUT

REG7

DAC

REG7

VOUT0………VOUT38

DAC 7

VOUT7

VOUT8

12

m REG7

c REG7

39-TO-1

MUX

VOUT38

×5

VOUT39/MON_OUT

LDAC

Figure 1.

Rev. E

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DESIGN RESOURCES

• AD5381 Material Declaration

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DOCUMENTATION

Application Notes

• AN-1224: 40 Channels of Programmable Voltage with

Excellent Temperature Drift Performance Using the

AD5381 DAC

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• AN-1227: AD5381 Channel Monitor Function

Data Sheet

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• AD5381: 40-Channel, 3 V/5 V, Single-Supply, 12-Bit,

denseDAC Data Sheet

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SOFTWARE AND SYSTEMS REQUIREMENTS

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REFERENCE MATERIALS

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• Software Calibration Reduces D/A Converter Offset and

Gain Errors

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AD5381

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Hardware Functions....................................................................... 26

Reset Function ............................................................................ 26

Asynchronous Clear Function.................................................. 26

Integrated Functions ........................................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Specifications..................................................................................... 5

AD5381-5 Specifications............................................................. 5

AD5381-3 Specifications............................................................. 7

AC Characteristics........................................................................ 8

Timing Characteristics..................................................................... 9

Serial Interface Timing ................................................................ 9

I²C Serial Interface Timing........................................................ 11

Parallel Interface Timing........................................................... 12

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Terminology .................................................................................... 18

Typical Performance Characteristics ........................................... 19

Functional Description.................................................................. 22

DAC Architecture—General..................................................... 22

Data Decoding ............................................................................ 22

On-Chip Special Function Registers (SFR) ............................ 23

SFR Commands.......................................................................... 23

and

Functions...................................................... 26

LDAC

BUSY

FIFO Operation in Parallel Mode............................................ 26

Power-On Reset.......................................................................... 26

Power-Down ............................................................................... 26

Interfaces.......................................................................................... 27

DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 27

I²C Serial Interface ..................................................................... 29

Parallel Interface......................................................................... 31

Microprocessor Interfacing....................................................... 32

Applications Information .............................................................. 34

Power Supply Decoupling ......................................................... 34

Power Supply Sequencing ......................................................... 34

Typical Configuration Circuit .................................................. 35

Monitor Function....................................................................... 36

Toggle Mode Function............................................................... 36

Thermal Monitor Function....................................................... 36

Optical Attenuators.................................................................... 37

Utilizing FIFO............................................................................. 37

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

Rev. E | Page 2 of 40

Data Sheet

AD5381

REVISION HISTORY

5/14—Rev. D to Rev. E

5/12—Rev. B to Rev. C

Deleted ADSP-2103 ...................................................... Throughout

Changed ADSP-2101 to ADSP-BF527....................... Throughout

Deleted Table 1; Renumbered Sequentially ...................................3

Changed 10 µA to 1 µA, Reference Input/Output, Input

Current Parameter, Table 1 ..............................................................5

Changed 10 µA to 1 µA, Reference Input/Output, Input

Current Parameter, Table 2 ..............................................................7

Changes to Table 4 ............................................................................9

Changes to Table 6 ..........................................................................12

Changes to Soft Reset Section .......................................................23

Changes to Reset Function Section ..............................................26

Changes to Figure 38 ......................................................................33

Added Power Supply Sequencing Section, Table 18, Figure 39,

and Figure 40; Renumbered Sequentially....................................34

Changed ADR280 to ADR3412, Typical Configuration Circuit

Section ..............................................................................................35

Added Figure 41 and Figure 42.....................................................35

Changes to Features ..........................................................................1

Changes to Table 3 ............................................................................4

Changes to Table 4 ............................................................................6

Changes to Output Voltage Settling Time and Slew Rate

Parameters, Table 5 ...........................................................................7

Changes to t₁₄, t₁₇, and t₁₉Parameters, Table 6...............................8

Changes to Table 9 ..........................................................................13

Changes to Figure 10, Figure 11, and Figure 14 .........................18

Changes to Figure 16 to Figure 18 and Figure 20.......................19

Updated Outline Dimensions and Changes to Ordering Guide ....37

8/05—Rev. A to Rev. B

Changes to Table 2 ............................................................................3

Changes to Specifications Section ..................................................4

Changes to Absolute Maximum Ratings Section .......................13

Changes to Figure 43 ......................................................................35

Changes to Ordering Guide...........................................................37

9/12—Rev. C to Rev. D

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Product Title..................................................................1

Changes to General Description Section and Table 1..................3

Deleted Table 2; Renumbered Sequentially ...................................3

Changes to Ordering Guide...........................................................36

5/04—Revision 0: Initial Version

Rev. E | Page 3 of 40

AD5381

Data Sheet

GENERAL DESCRIPTION

The AD5381 is a complete, single-supply, 40-channel, 12-bit

denseDAC® available in a 100-lead LQFP package. All 40 channels

have an on-chip output amplifier with rail-to-rail operation.

The AD5381 includes a programmable internal 1.25 V/2.5 V,

10 ppm/°C reference, an on-chip channel monitor function that

multiplexes the analog outputs to a common MON_OUT pin

for external monitoring, and an output amplifier boost mode,

which allows optimization of the amplifier slew rate. The AD5381

An input register followed by a DAC register provides double

buffering, allowing the DAC outputs to be updated

independently or simultaneously using the

input.

LDAC

Each channel has a programmable gain and offset adjust

register that allows the user to fully calibrate any DAC chan-

nel. Power consumption is typically 0.25 mA/channel with

boost mode disabled.

contains a double-buffered parallel interface featuring 20 ns

WR

pulse width, an SPI-/QSPI-/MICROWIRE-/DSP-compatible serial

interface with interface speeds in excess of 30 MHz, and an I²C-

compatible interface that supports a 400 kHz data transfer rate.

Rev. E | Page 4 of 40

Data Sheet

AD5381

SPECIFICATIONS

AD5381-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T_MINto T_MAX

,

unless otherwise noted.

Table 1.

Parameter

AD5381-5¹

Unit

Test Conditions/Comments

ACCURACY

Output unloaded

Resolution

12

1

Bits

Relative Accuracy²(INL)

Differential Nonlinearity (DNL)

Zero-Scale Error

Offset Error

LSB max

mV max

Guaranteed monotonic over temperature

Measured at Code 8 in the linear region

4

mV max

Offset Error TC

Gain Error

5

μV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

0.05

0.0ꢀ

2

At 25°C

T_MINto T_MAX

Gain Temperature Coefficient³

DC Crosstalk³

1

REFERENCE INPUT/OUTPUT

Reference Input³

Reference Input Voltage

2.5

V

1% for specified performance, AVDD = 2 × REFIN

+ 50 mV

DC Input Impedance

Input Current

1

MΩ min

μA max

Typically 100 MΩ

Typically 30 nA

Reference Range

Reference Output⁴

1 to AVDD/2 V min/max

Enabled via CR8 in the AD5381 control register,

CR10 selects the reference voltage

Output Voltage

Reference TC

2.495/2.505

1.22/1.28

10

15

800

V min/max

ppm/°C max

Ω typ

At ambient, optimized for 2.5 V operation. CR10 = 1

CR10 = 0

Temperature Range: +25°C to +85°C

Temperature Range: −40°C to +85°C

Output Impedance

OUTPUT CHARACTERISTICS³

Output Voltage Range²

Short-Circuit Current

Load Current

0/AVDD

40

1

V min/max

mA max

Capacitive Load Stability

R_L= ∞

R_L= 5 kΩ

DC Output Impedance

MONITOR PIN

200

1000

0.ꢀ

pF max

Ω max

Output Impedance

Three-State Leakage Current

LOGIC INPUTS (EXCEPT SDA/SCL)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

DVDD > 3.ꢀ V

DVDD ≤ 3.ꢀ V

Input Current

Pin Capacitance

1

100

kΩ typ

nA typ

DVDD = 2.7 V to 5.5 V

2

V min

0.8

0.ꢀ

10

V max

μA max

pF max

Total for all pins; T_A= T_MINto T_MAX

10

Rev. E | Page 5 of 40

AD5381

Data Sheet

Parameter

AD5381-5¹

Unit

Test Conditions/Comments

LOGIC INPUTS (SDA, SCL ONLY)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

0.7 × DVDD

0.3 × DVDD

±±

V min

V max

µA max

SMBus compatible at DVDD < 3.6 V

0.05 × DVDD V min

C_IN, Input Capacitance

8

pF typ

Glitch Rejection

50

ns max

Input filtering suppresses noise spikes of less than 50 ns

LOGIC OUTPUTS (BUSY, SDO)³

V_OL, Output Low Voltage

V_OH, Output High Voltage

V_OL, Output Low Voltage

V_OH, Output High Voltage

High Impedance Leakage Current

High Impedance Output Capacitance

LOGIC OUTPUT (SDA)³

0.4

DVDD – ±

0.4

DVDD – 0.5

±±

5

V max

V min

V max

V min

µA max

pF typ

DVDD = 5 V ± ±0%, sinking 200 µA

DVDD = 5 V ± ±0%, sourcing 200 µA

DVDD = 2.7 V to 3.6 V, sinking 200 µA

DVDD = 2.7 V to 3.6 V, sourcing 200 µA

SDO only

V_OL, Output Low Voltage

0.4

0.6

±±

8

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

AVDD

4.5/5.5

2.7/5.5

V min/max

DVDD

Power Supply Sensitivity³

∆Midscale/∆ΑV_DD

AI_DD

–85

0.375

0.475

±

dB typ

mA/channel max

mA max

Outputs unloaded, boost off; 0.25 mA/channel typ

Outputs unloaded, boost on.; 0.325 mA /channel typ

V_IH= DVDD, V_IL= DGND

DI_DD

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

80

µA max

mW max

Typically ±00 nA

Typically ± µA

Outputs unloaded, boost off, AVDD = DVDD = 5 V

^±AD538±-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

²Accuracy guaranteed from VOUT = ±0 mV to AVDD – 50 mV.

³Guaranteed by characterization, not production tested.

⁴Default on the AD538±-5 is 2.5 V. Programmable to ±.25 V via CR±0 in the AD538± control register; operating the AD538±-5 with a ±.25 V reference will lead to

degraded accuracy specifications.

Rev. E | Page 6 of 40

Data Sheet

AD5381

AD5381-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T_MINto T_MAX, unless

otherwise noted.

Table 2.

Parameter

AD5381-3¹

Unit

Test Conditions/Comments

ACCURACY

Output unloaded

Resolution

±2

±±

4

±4

±5

±0.05

±0.±

2

Bits

Relative Accuracy²(INL)

Differential Nonlinearity (DNL)

Zero-Scale Error

Offset Error

LSB max

mV max

Guaranteed monotonic over temperature

Measured at Code ±6 in the linear region

mV max

Offset Error TC

Gain Error

µV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

At 25 °C

T_MINto T_MAX

Gain Temperature Coefficient³

DC Crosstalk³

±

REFERENCE INPUT/OUTPUT

Reference Input³

Reference Input Voltage

DC Input Impedance

Input Current

Reference Range

Reference Output⁴

±.25

±

±±

V

±±% for specified performance

Typically ±00 MΩ

Typically ±30 nA

MΩ min

µA max

V min/max

± to AVDD/2

Enabled via CR8 in the AD538± control register

CR±0 selects the reference voltage.

Output Voltage

Reference TC

±.245/±.255

2.47/2.53

±±0

±±5

800

V min/max

ppm/°C max

Ω typ

At ambient; optimized for ±.25 V operation; CR±0 = 0

CR±0 = ±

Temperature Range: +25°C to +85°C

Temperature Range: –40°C to +85°C

Output Impedance

OUTPUT CHARACTERISTICS³

Output Voltage Range²

Short-Circuit Current

Load Current

0/AVDD

40

±±

V min/max

mA max

Capacitive Load Stability

R_L= ∞

R_L= 5 kΩ

DC Output Impedance

MONITOR PIN

200

±000

0.6

pF max

Ω max

Output Impedance

Three-State Leakage Current

LOGIC INPUTS (EXCEPT SDA/SCL)³

V_IH, Input High Voltage

V_IL,Input Low Voltage

DVDD > 3.6

DVDD ≤ 3.6

Input Current

Pin Capacitance

±

±00

kΩ typ

nA typ

DVDD = 2.7 V to 3.6 V

2

V min

0.8

0.6

±±

±0

V max

µA max

pF max

Total for all pins; T_A= T_MINto T_MAX

LOGIC INPUTS (SDA, SCL ONLY)³

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

C_IN, Input Capacitance

Glitch Rejection

0.7 × DVDD

0.3 × DVDD

±±

0.05 × DVDD

8

50

V min

SMBus compatible at DVDD < 3.6 V

V max

µA max

V min

pF typ

ns max

Input filtering suppresses noise spikes of less than 50 ns

Rev. E | Page 7 of 40

AD5381

Data Sheet

AD5381-3¹

Parameter

LOGIC OUTPUTS (BUSY, SDO)³

Unit

Test Conditions/Comments

V_OL, Output Low Voltage

V_OH, Output High Voltage

High Impedance Leakage Current

High Impedance Output Capacitance

LOGIC OUTPUT (SDA)³

0.4

DVDD – 0.5

±±

5

V max

V min

µA max

pF typ

Sinking 200 µA

Sourcing 200 µA

SDO only

V_OL, Output Low Voltage

0.4

0.6

±±

8

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

AVDD

2.7/3.6

2.7/5.5

V min/max

DVDD

Power Supply Sensitivity³

∆Midscale/∆ΑV_DD

AI_DD

–85

0.375

0.475

±

dB typ

mA/channel max

mA max

Outputs unloaded, boost off; 0.25 mA/channel typ

Outputs unloaded, boost on; 0.325 mA/channel typ

V_IH= DVDD, V_IL= DGND

DI_DD

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

48

µA max

mW max

Typically ±00 nA

Typically ± µA

Outputs unloaded, boost off, AVDD = DVDD = 3 V

^±AD538±-3 is calibrated using an external ±.25 V reference. Temperature range is –40°C to +85°C.

²Accuracy guaranteed from VOUT = ±0 mV to AVDD– 50 mV.

³Guaranteed by characterization, not production tested.

⁴Default on the AD538±-3 is ±.25 V. Programmable to 2.5 V via CR±0 in the AD538± control register; operating the AD538±-3 with a 2.5 V reference will lead to degraded

accuracy specifications and limited input code range.

AC CHARACTERISTICS

AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.¹

Table 3.

Parameter

All

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

±/4 scale to 3/4 scale change settling to ±± LSB

3

µs typ

8

µs max

V/µs typ

nV-s typ

mV typ

Slew Rate²

±.5

2.5

±2

±5

Boost mode off, CR9 = 0

Boost mode on, CR9 = ±

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

DAC-to-DAC Crosstalk

Digital Crosstalk

Digital Feedthrough

Output Noise 0.± Hz to ±0 Hz

±

nV-s typ

µV p-p typ

See Terminology section

0.8

0.±

±5

40

Effect of input bus activity on DAC output under test

External reference, midscale loaded to DAC

Internal reference, midscale loaded to DAC

Output Noise Spectral Density

At ± kHz

At ±0 kHz

±50

±00

nV/√Hz typ

^±Guaranteed by design and characterization, not production tested.

²Slew rate can be programmed via the current boost control bit in the AD538± control register.

Rev. E | Page 8 of 40

Data Sheet

AD5381

TIMING CHARACTERISTICS

SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Parameter^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t_±

t₂

t₃

t₄

33

±3

ns min

ns max

ns min

ns min/max

ns min

ns min/max

µs typ

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

24^thSCLK falling edge to SYNC falling edge

Minimum SYNC low time

4

t₅

±3

4

t₆

33

t₇

±0

Minimum SYNC high time

t_7A

t₈

t₉

±40

Minimum SYNC high time in Readback mode

Data setup time

Data hold time

24^thSCLK falling edge to BUSY falling edge

BUSY pulse width low (single channel update)

24th SCLK falling edge to LDAC falling edge

LDAC pulse width low

5

4.5

36

4

t_±0

t_±±

670

4

t_±2

20

t_±3

t_±4

t_±5

t_±6

t_±7

t_±8

t_±9

20

±00/2000

BUSY rising edge to DAC output response time

BUSY rising edge to LDAC falling edge

LDAC falling edge to DAC output response time

DAC output settling time; boost mode off

CLR pulse width low

0

±00/2000

3

20

40

30

5

ns min

µs max

ns max

ns min

CLR pulse activation time

5

t₂₀

t_2±

SCLK rising edge to SDO valid

SCLK falling edge to SYNC rising edge

SYNC rising edge to SCLK rising edge

SYNC rising edge to LDAC falling edge

5

t₂₂

8

t₂₃

20

^±Guaranteed by design and characterization, not production tested.

²All input signals are specified with t_r= t_f= 5 ns (±0% to 90% of V_CC) and are timed from a voltage level of ±.2 V.

³See Figure 2, Figure 3, Figure 4, and Figure 5.

⁴Standalone mode only.

⁵Daisy-chain mode only.

200µA

I

OL

V

(MIN) OR

(MAX)

OH

OL

TO OUTPUT PIN

C

L

50pF

I

200µA

OH

Figure 2. Load Circuit for Digital Output Timing

Rev. E | Page 9 of 40

AD5381

Data Sheet

t₁

24

SCLK

t₃

t₆

t₂

t₅

t₄

SYNC

DIN

t₇

t₈t₉

DB0

DB23

t₁₀

t₁₁

t₁₃

BUSY

t₁₂

t₁₇

1

LDAC

t₁₄

VOUT1

t₁₅

t₁₃

t₁₇

2

LDAC

t₁₆

VOUT2

t₁₈

CLR

t₁₉

VOUT

1

2

LDAC ACTIVE DURING BUSY.

LDAC ACTIVE AFTER BUSY.

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

SCLK

24

48

t_7A

SYNC

DIN

DB23

DB0

DB23

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB0

SDO

UNDEFINED

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t₁

SCLK

24

48

t₃

t₂

t₂₁

t₇

t₂₂

t₄

SYNC

DIN

t₈t₉

DB23

DB0 DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N + 1

t₂₀

DB23

DB0

SDO

UNDEFINED

INPUT WORD FOR DAC N

t₁₃

t₂₃

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

Rev. E | Page ±0 of 40

Data Sheet

AD5381

I²C SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T_MINto T_MAX

,

unless otherwise noted.

Table 5.

Parameter^{1, 2}

Limit at T_MIN, T_MAX

Unit

Description

f_SCL

t_±

t₂

t₃

t₄

400

2.5

0.6

±.3

0.6

±00

0.9

0

0.6

±.3

300

0

kHz max

µs min

ns min

µs max

µs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_SU,DAT, data setup time

t_HD,DAT, data hold time

t₅

t₆

3

t_HD,DAT, data hold time

t₇

t₈

t₉

t_±0

t_SU,STA, setup time for repeated start

t_SU,STO, stop condition setup time

t_BUF, bus free time between a STOP and a START condition

t_R, rise time of SCL and SDA when receiving

t_R, rise time of SCL and SDA when receiving (CMOS compatible)

t_F, fall time of SDA when transmitting

t_F, fall time of SDA when receiving (CMOS compatible)

t_F, fall time of SCL and SDA when receiving

t_F, fall time of SCL and SDA when transmitting

Capacitive load for each bus line

t_±±

300

0

300

20 + 0.± C_b

400

4

C_b

^±Guaranteed by design and characterization, not production tested.

²See Figure 6.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

⁴C_bis the total capacitance, in pF, of one bus line. t_Rand t_Fare measured between 0.3 DVDD and 0.7 DVDD.

SDA

t₉

t₃

t₁₀

t₁₁

t₄

SCL

t₄

t₆

t₂

t₁

t₈

t₅

t₇

START

CONDITION

REPEATED

START

STOP

CONDITION

Figure 6. I²C-Compatible Serial Interface Timing Diagram

Rev. E | Page ±± of 40

AD5381

Data Sheet

PARALLEL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T_MINto T_MAX

,

unless otherwise noted.

Table 6.

Parameter^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t₀

t_±

t₂

t₃

t₄

t₅

t₆

t₇

t₈

4.5

ns min

ns max

ns min

ns min/max

ns min

ns min/max

µs typ

REG0, REG±, address to WR rising edge setup time

REG0, REG±, address to WR rising edge hold time

CS pulse width low

4.5

20

WR pulse width low

0

CS to WR falling edge setup time

WR to CS rising edge hold time

0

4.5

Data to WR rising edge setup time

Data to WR rising edge hold time

WR pulse width high

4.5

20

4

t₉

700

Minimum WR cycle time (single-channel write)

WR rising edge to BUSY falling edge

BUSY pulse width low (single-channel update)

WR rising edge to LDAC falling edge

LDAC pulse width low

4

t_±0

30

4, 5

t_±±

670

t_±2

t_±3

t_±4

t_±5

t_±6

t_±7

t_±8

t_±9

t₂₀

30

20

±00/2000

BUSY rising edge to DAC output response time

LDAC rising edge to WR rising edge

BUSY rising edge to LDAC falling edge

LDAC falling edge to DAC output response time

DAC output settling time, boost mode off

CLR pulse width low

20

0

±00/2000

8

20

40

ns min

µs max

CLR pulse activation time

^±Guaranteed by design and characterization, not production tested.

²All input signals are specified with t_R= t_R= 5 ns (±0% to 90% of DVDD) and timed from a voltage level of ±.2 V.

³See Figure 7.

⁴See Figure 29.

⁵Measured with the load circuit of Figure 2.

Rev. E | Page ±2 of 40

Data Sheet

AD5381

t₀

t₁

REG0, REG1, A5...A0

t₄

t₅

t₂

CS

t₉

t₃

t₈

WR

t₁₅

t₆

t₇

DB11...DB0

BUSY

t₁₀

t₁₁

t₁₃

t₁₂

t₁₈

1

LDAC

t₁₄

t₁₆

VOUT1

2

LDAC

t₁₃

t₁₈

t₁₇

VOUT2

CLR

t₁₉

t₂₀

VOUT

1

2

LDAC ACTIVE DURING BUSY.

LDAC ACTIVE AFTER BUSY.

Figure 7. Parallel Interface Timing Diagram

Rev. E | Page ±3 of 40

AD5381

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.¹

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect device

reliability.

Table 7.

Parameter

Rating

AVDD to AGND

–0.3 V to +7 V

DVDD to DGND

–0.3 V to +7 V

Digital Inputs to DGND

SDA/SCL to DGND

–0.3 V to DVDD + 0.3 V

–0.3 V to +7 V

ESD CAUTION

Digital Outputs to DGND

REFIN/REFOUT to AGND

AGND to DGND

–0.3 V to DVDD + 0.3 V

–0.3 V to AVDD + 0.3 V

–0.3 V to +0.3 V

VOUTx to AGND

–0.3 V to AVDD + 0.3 V

Analog Inputs to AGND

Operating Temperature Range

Commercial (B Version)

Storage Temperature Range

Junction Temperature (T_{J MAX}

±00-Lead LQFP Package

θ_JAThermal Impedance

Reflow Soldering

Peak Temperature

Reflow Soldering (Pb-free)

Peak Temperature

Time at Peak Temperature

ESD

–40°C to +85°C

–65°C to +±50°C

±50°C

)

44°C/W

230°C

260 (0/−5)°C

±0 sec to 40 sec

HBM

FICDM

6.5 kV

2 kV

^±Transient currents of up to ±00 mA will not cause SCR latch-up.

Rev. E | Page ±4 of 40

Data Sheet

AD5381

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

FIFO EN

CLR

VOUT24

VOUT25

VOUT26

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RESET

DB5

DB4

DB3

DB2

DB1

DB0

NC

PIN 1

IDENTIFIER

2

3

4

5

6

VOUT27

SIGNAL_GND4

DAC_GND4

AGND4

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AVDD4

VOUT28

VOUT29

VOUT30

REG0

REG1

VOUT23

VOUT22

VOUT21

VOUT20

AVDD3

AGND3

DAC_GND3

SIGNAL_GND3

VOUT19

VOUT18

VOUT17

VOUT16

AVDD2

AGND2

AD5381

TOP VIEW

(Not to Scale)

VOUT31

REFGND

REFOUT/REFIN

SIGNAL_GND1

DAC_GND1

AVDD1

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

AGND1

NC = NO CONNECT

Figure 8. 100-Lead LQFP Pin Configuration

Table 8. Pin Function Descriptions

Mnemonic

Function

VOUTx

Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a

gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

SIGNAL_GND(±–5)

DAC_GND(±–5)

AGND(±–5)

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together

internally and should be connected to the AGND plane as close as possible to the AD538±.

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal ±2-bit DAC.

These pins should be connected to the AGND plane.

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be

connected externally to the AGND plane.

AVDD(±–5)

Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and

should be decoupled with a 0.± µF ceramic capacitor and ±0 µF tantalum capacitor. Operating range for the AD538±-5

is 4.5 V to 5.5 V; operating range for the AD538±-3 is 2.7 V to 3.6 V.

DGND

DVDD

Ground for All Digital Circuitry.

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled

with a 0.± µF ceramic and a ±0 µF tantalum capacitors to DGND.

REFGND

Ground Reference Point for the Internal Reference.

REFOUT/REFIN

The AD538± contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference

output. If the application requires an external reference, it can be applied to this pin and the internal reference can

be disabled via the control register. The default for this pin is a reference input.

Rev. E | Page ±5 of 40

AD5381

Data Sheet

Mnemonic

Function

VOUT39/MON_OUT This pin has a dual function. It acts as a buffered output for Channel 39 in default mode. However, when the monitor

function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex

one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is

intended to drive a high input impedance like that exhibited by SAR ADC inputs.

SER/PAR

Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied high,

the serial interface mode is selected and Pin 97 (SPI/I²C) is used to determine if the interface mode is SPI or I²C.

Parallel interface mode is selected when SER/PAR is low.

CS/(SYNC/AD0)

In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5381

is selected.

Serial Interface Mode. This is the frame synchronization input signal for the serial clock and data.

I²C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address

for the device on the I²C bus.

WR/(DCEN/AD1)

Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a

daisy-chain enable in SPI mode and as a hardware address pin in I²C mode.

Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low, and the

address bus inputs to write to the selected device registers.

Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction

with SER/PAR high to enable the SPI serial interface daisy-chain mode.

I²C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address

for this device on the I²C bus.

DB11–DB0

A5–A0

Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5381.

Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5381’s 40 input channels. Used in conjunction

with the REG1 and REG0 pins to determine the destination register for the input data.

REG1, REG0

SDO/(A/B)

In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1

and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and

are also used to decide the special function registers.

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a

number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of

SCLK.

When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the

AD5381’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the

LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels

contain two data registers. In normal mode, Data Register A is the default for data transfers.

BUSY

Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.

During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the

DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also

goes low during power-on reset, and when the RESET pin is low. During this time, the interface is disabled and any

events on LDAC are ignored. A CLR operation also brings BUSY low.

LDAC

CLR

Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input

registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is

active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when

BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored.

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated

with the data contained in the CLR code register. BUSY is low for a duration of 35 μs while all channels are being

updated with the CLR code.

Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-

on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m,

c, and x2 registers to their default power-on values. This sequence typically takes 270 μs. The falling edge of RESET

initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY

is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal

operation and the status of the RESET pin is ignored until the next falling edge is detected.

PD

Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog

current consumption is reduced to 2 μA and the digital current consumption is reduced to 20 μA. In power-down

mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high

impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured.

The serial interface remains active during power-down.

Rev. E | Page 16 of 40

Data Sheet

AD5381

Mnemonic

Function

FIFO EN

FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user

to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is

sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or

I²C interface modes, the FIFO EN pin should be tied low.

DB9/(SPI/I²C)

Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial

interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = ±) and

this input is low, SPI mode is selected. In SPI mode, DB±2 is the serial clock (SCLK) input and DB±± is the serial data

(DIN) input.

When serial interface mode is selected (SER/PAR = ±) and this input is high I²C Mode is selected.

In this mode, DB±2 is the serial clock (SCL) input and DB±± is the serial data (SDA) input.

DB±0/(SCLK/SCL)

DB±±/(DIN/SDA)

Multifunction Input Pin. In parallel interface mode, this pin acts as DB±0 of the parallel input data-word. In serial

interface mode, this pin acts as a serial clock input.

Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK.

This operates at clock speeds up to 50 MHz.

I²C Mode. In I²C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in

I²C mode is compatible with both ±00 kHz and 400 kHz operating modes.

Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB±± of the parallel input data-word.

Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling

edge of SCLK.

I²C Mode. In I²C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.

Rev. E | Page ±7 of 40

AD5381

Data Sheet

TERMINOLOGY

Relative Accuracy

DC Output Impedance

Relative accuracy, or endpoint linearity, is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero-scale error and full-scale error, and is

expressed in LSB.

This is the effective output source resistance. It is dominated by

package lead resistance.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to

settle to a specified level for a ¼ to ¾ full-scale input change,

and is measured from the

rising edge.

Differential Nonlinearity

BUSY

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity.

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at

the major code transition. It is specified as the area of the glitch

in nV-s. It is measured by toggling the DAC register data

between 0x7FF and 0x800.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all

0s are loaded into the DAC register. Ideally, with all 0s loaded to

the DAC and m = all 1s, c = 2^{n – 1}

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the

output of one DAC due to both the digital change and the

subsequent analog output change at another DAC. The victim

channel is loaded with midscale. DAC-to-DAC crosstalk is

specified in nV-s.

VOUT_(Zero-Scale)= 0 V

Zero-scale error is a measure of the difference between VOUT

(actual) and VOUT (ideal), expressed in mV. It is mainly due to

offsets in the output amplifier.

Digital Crosstalk

The glitch impulse transferred to the output of one converter

due to a change in the DAC register code of another converter is

defined as the digital crosstalk and is specified in nV-s.

Offset Error

Offset error is a measure of the difference between VOUT

(actual) and VOUT (ideal) in the linear region of the transfer

function, expressed in mV. Offset error is measured on the

AD5381-5 with Code 32 loaded into the DAC register, and on

the AD5381-3 with Code 64.

Digital Feedthrough

When the device is not selected, high frequency logic activity

on the device’s digital inputs can be capacitively coupled both

across and through the device to show up as noise on the

VOUT pins. It can also be coupled along the supply and ground

lines. This noise is digital feedthrough.

Gain Error

Gain Error is specified in the linear region of the output range

between VOUT = 10 mV and VOUT = AVDD – 50 mV. It is the

deviation in slope of the DAC transfer characteristic from the

ideal and is expressed in %FSR with the DAC output unloaded.

Output Noise Spectral Density

This is a measure of internally generated random noise.

Random noise is characterized as a spectral density (voltage per

√Hertz). It is measured by loading all DACs to midscale and

measuring noise at the output. It is measured in nV/√Hz in a

1 Hz bandwidth at 10 kHz.

DC Crosstalk

This is the dc change in the output level of one DAC at midscale

in response to a full-scale code (all 0s to all 1s, and vice versa)

and output change of all other DACs. It is expressed in LSB.

Rev. E | Page ±8 of 40

Data Sheet

AD5381

TYPICAL PERFORMANCE CHARACTERISTICS

1.00

0.75

0.50

0.25

0

AVDD = 5V

AVDD = 3V

REFIN = 1.25V

= 25°C

REFIN = 2.5V

= 25°C

0.75

T

A

0.50

0.25

0

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

–1.00

0

512

1024

1536

2048

2560

3072

3584

4096

0

512

1024

1536

2048

2560

3072

3584

4096

INPUT CODE

Figure 9. Typical AD5381-5 INL Plot

Figure 12. Typical AD5381-3 INL Plot

1.254

1.253

1.252

1.251

1.250

1.249

1.248

1.247

1.246

1.245

2.510

2.505

2.500

2.995

2.990

AVDD = DVDD = 3V

V

= 1.25V

REF

= 25°C

T

A

14ns/SAMPLE NUMBER

1 LSB CHANGE AROUND MIDSCALE

GLITCH IMPULSE = 5nV-s

0

50 100 150 200 250 300 350 400 450 500 550

SAMPLE NUMBER

0

2

4

6

8

10

12

TIME (µs)

Figure 10. AD5381-5 Glitch Impulse

Figure 13. AD5381-3 Glitch Impulse

LDAC

VOUT

AVDD = DVDD = 5V

= 2.5V

AVDD = DVDD = 5V

VREF = 2.5V

V

REF

T

= 25°C

T = 25°C

A

Figure 14. Slew Rate with Boost On

Figure 11. Slew Rate with Boost Off

Rev. E | Page ±9 of 40

AD5381

Data Sheet

14

12

10

8

AVDD = 5.5V

= 2.5V

V

REF

= 25°C

T

A

AVDD = DVDD = 5V

VREF = 2.5V

T

= 25°C

A

VDD

6

4

VOUT

2

8

9

10

AI (mA)

11

DD

Figure 15. AI_DDHistogram with Boost Off

Figure 18. Power-Up Transient

40

35

30

25

20

15

10

5

DVDD = 5.5V

V

= DVDD

= DGND

= 25°C

IH

IL

A

10

8

T

6

4

2

0

–5.0 –4.0 –3.0 –2.0 –1.0

0

1.0 2.0 3.0 4.0 5.0

0

–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5

REFERENCE DRIFT (ppm/°C)

0.5

0.6

0.7

DI

0.8

0.9

1.0

(mA)

DD

Figure 19. REFOUT Temperature Coefficient

Figure 16. DI_DDHistogram

PD

BUSY

VOUT

AVDD = DVDD = 5V

= 2.5V

V

= 2.5V

REF

= 25°C

V

REF

T

A

T

= 25°C

A

Figure 17. Exiting Soft Power-Down

Figure 20. Exiting Hardware Power-Down

Rev. E | Page 20 of 40

Data Sheet

AD5381

6

5

AVDD = DVDD = 3V

= 1.25V

FULL SCALE

V

REF

T

= 25°C

5

A

AVDD = DVDD = 5V

V

= 2.5V

= 25°C

3/4 SCALE

REF

4

3

T

4

A

3/4 SCALE

FULL SCALE

MIDSCALE

3

MIDSCALE

2

1/4 SCALE

1

ZERO SCALE

0

ZERO SCALE

–5

1/4 SCALE

–1

–40 –20 –10

–5

–2

0

2

5

10

20

40

–40 –20 –10

–2

0

2

5

10

20

–40

CURRENT (mA)

Figure 21. AD5381-5 Output Amplifier Source and Sink Capability

Figure 24. AD5381-3 Output Amplifier Source and Sink Capability

0.20

2.456

AVDD = 5V

AVDD = DVDD = 5V

V

= 2.5V

REF

= 25°C

V

T

= 2.5V

REF

= 25°C

0.15

0.10

0.05

0

T

A

2.455

2.454

2.453

2.452

2.451

2.450

2.449

A

14ns/SAMPLE NUMBER

ERROR AT ZERO SINKING CURRENT

–0.05

–0.10

–0.15

–0.20

(VDD–VOUT) AT FULL-SCALE SOURCING CURRENT

0

0.25

0.50

0.75

I

1.00

/I

1.25

1.50

1.75

2.00

0

50 100 150 200 250 300 350 400 450 500 550

SAMPLE NUMBER

(mA)

SOURCE SINK

Figure 22. Headroom at Rails vs. Source/Sink Current

Figure 25. Adjacent Channel DAC-to-DAC Crosstalk

600

500

400

300

200

100

0

AVDD = 5V

T

= 25°C

A

REFOUT DECOUPLED

WITH 100nF CAPACITOR

AVDD = DVDD = 5V

= 25°C

T

A

DAC LOADED WITH MIDSCALE

EXTERNAL REFERENCE

Y AXIS = 5µV/DIV

X AXIS = 100ms/DIV

REFOUT = 2.5V

AV = DV = 5V

DD DD

REFOUT = 1.25V

V

= 2.5V

REF

T

= 25°C

A

EXITS SOFT PD

TO MIDSCALE

100

1k

10k

100k

FREQUENCY (Hz)

Figure 26. 0.1 Hz to 10 Hz Noise Plot

Figure 23. REFOUT Noise Spectral Density

Rev. E | Page 2± of 40

AD5381

Data Sheet

FUNCTIONAL DESCRIPTION

The complete transfer function for these devices can be

represented as

VOUT = 2 × V_REF× x2/2ⁿ

DAC ARCHITECTURE—GENERAL

The AD5381 is a complete, single-supply, 40-channel voltage

output DAC that offers 12-bit resolution. The part is available

in a 100-lead LQFP package and features both a parallel and

a serial interface. This product includes an internal, software

selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used

to drive the buffered reference inputs; alternatively, an external

reference can be used to drive these inputs. Internal/external

reference selection is via the CR8 bit in the control register;

CR10 selects the reference magnitude if the internal reference

is selected. All channels have an on-chip output amplifier with

rail-to-rail output capable of driving 5 kΩ in parallel with a

200 pF load.

where:

x2 is the data-word loaded to the resistor string DAC. V_REF

is externally applied to the DAC REFOUT/REFIN pin. For

specified performance, an external reference voltage of 2.5 V is

recommended for the AD5381-5, and 1.25 V for the AD5381-3.

DATA DECODING

The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-

ing on the value of REG1 and REG0 (see Table 9), this data is

loaded into the addressed DAC input registers, offset I registers,

or gain (m) registers. The format data, offset I, and gain (m)

register contents are shown in Table 10 to Table 12.

VREF

AVDD

×1 INPUT

REG

Table 9. Register Selection

DAC

REG

12-BIT

DAC

REG1

REG0

Register Selected

INPUT DATA m REG ×2

c REG

VOUT

±

0

±

0

±

0

Input Data Register (x±)

Offset Register I

Gain Register (m)

R

Special Function Registers (SFRs)

Figure 27. Single-Channel Architecture

Table 10. DAC Data Format (REG1 = 1, REG0 = 1)

The architecture of a single DAC channel consists of a 12-bit

resistor-string DAC followed by an output buffer amplifier

operating at a gain of 2. This resistor-string architecture

guarantees DAC monotonicity. The 12-bit binary digital code

loaded to the DAC register determines at what node on the

string the voltage is tapped off before being fed to the output

amplifier. Each channel on these devices contains independent

offset and gain control registers that allow the user to digitally

trim offset and gain. These registers give the user the ability to

calibrate out errors in the complete signal chain, including the

DAC, using the internal m and c registers, which hold the

correction factors. All channels are double buffered, allow-

DB11 to DB0

DAC Output (V)

2 V_REF× (4095/4096)

2 V_REF× (4094/4096)

2 V_REF× (2049/4096)

2 V_REF× (2048/4096)

2 V_REF× (2047/4096)

2 V_REF× (±/4096)

0

±±±±

±000

0±±±

0000

±±±±

0000

±±±±

0000

±±±±

±±±0

000±

0000

±±±±

000±

0000

Table 11. Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0

Offset (LSB)

+2048

+2047

+±

0

–±

±±±±

±000

0±±±

0000

±±±±

0000

±±±±

0000

±±±±

±±±0

000±

0000

±±±±

000±

0000

ing synchronous updating of all channels using the

pin.

LDAC

Figure 27 shows a block diagram of a single channel on the

AD5381. The digital input transfer function for each DAC

can be represented as

–2047

–2048

x2 = [(m + 2)/ 2ⁿ× x1] + (c – 2^{n – 1}

)

where:

Table 12. Gain Data Format (REG1 = 0, REG0 = 1)

x2 = the data-word loaded to the resistor string DAC.

x1 = the 12-bit data-word written to the DAC input register.

m = the gain coefficient (default is 0xFFE). The gain coefficient

is written to the 11 most significant bits (DB11 to DB1), the LSB

(DB0) of the data-word is a 0.

DB11 to DB0

Gain Factor

±±±±

±0±±

0±±±

00±±

0000

±±±±

±±±0

0000

±

0.75

0.5

0.25

0

n = DAC resolution (n = 12 for AD5381).

c = the12-bit offset coefficient (default is 0x800).

0000

Rev. E | Page 22 of 40

Data Sheet

AD5381

Soft CLR

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

REG1 = REG0 = 0, A5 to A0 = 000010

DB11 to DB0 = Don’t Care

The AD5381 contains a number of special function registers

(SFRs), as outlined in Table 13. SFRs are addressed with

REG1 = REG0 = 0 and are decoded using Address Bits

A5 to A0.

Executing this instruction performs the CLR, which is func-

tionally the same as that provided by the external

pin. The

CLR

DAC outputs are loaded with the data in the CLR code register.

It takes 35 µs to fully execute the SOFT CLR, as indicated by

Table 13. SFR Register Functions (REG1 = 0, REG0 = 0)

R/

A5 A4 A3 A2 A1 A0 Function

W

the

low time.

BUSY

X

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

NOP (No Operation)

Write CLR Code

Soft CLR

Soft Power-Down

Soft Power-Up

Control Register Write

Control Register Read

Monitor Channel

Soft Reset

Soft Power-Down

REG1 = REG0 = 0, A5 to A0 = 001000

DB11 to DB0 = Don’t Care

Executing this instruction performs a global power-down

feature that puts all channels into a low power mode that

reduces the analog supply current to 2 µA max and the digi-

tal current to 20 µA max. In power-down mode, the output

amplifier can be configured as a high impedance output or

provide a 100 kΩ load to ground. The contents of all internal

registers are retained in power-down mode. No register can be

written to while in power-down.

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A5 to A0 = 000000

Performs no operation but is useful in serial readback mode to

Soft Power-Up

REG1 = REG0 = 0, A5 to A0 = 001001

DB11 to DB0 = Don’t Care

clock out data on D_OUTfor diagnostic purposes.

pulses

BUSY

low during a NOP operation.

This instruction is used to power up the output amplifiers and

the internal reference. The time to exit power-down is 8 µs.

The hardware power-down and software function are internally

combined in a digital OR function.

Write CLR Code

REG1 = REG0 = 0, A5 to A0 = 000001

DB11 to DB0 = Contain the CLR data

Soft RESET

Bringing the

line low or exercising the soft clear function

CLR

REG1 = REG0 = 0, A5 to A0 = 001111

DB11 to DB0 = Don’t Care

will load the contents of the DAC registers with the data con-

tained in the user configurable CLR register, and will set

VOUT0 to VOUT39 accordingly. This can be very useful for

setting up a specific output voltage in a clear condition. It is also

beneficial for calibration purposes; the user can load full scale

or zero scale to the clear code register and then issue a hard-

ware or software clear to load this code to all DACs, removing

the need for individual writes to each DAC. Default on power-

up is all zeros.

This instruction is used to implement a software reset. All

internal registers are reset to their default values, which corre-

spond to m at full scale and c at zero scale. The contents of the

DAC registers are cleared, setting all analog outputs to 0 V. The

soft reset activation time is 135 µs. Only perform a soft reset

when the AD5381 is not in power-down mode.

Rev. E | Page 23 of 40

AD5381

Data Sheet

Table 14. Control Register Contents

MSB

LSB

CR±±

CR±0

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR±

CR0

Control Register Write/Read

REG1 = REG0 = 0, A5 to A0 = 001100, R/ status determines

CR6: Thermal Monitor Function. When enabled, this function

is used to monitor the internal die temperature of the AD5381.

The thermal monitor powers down the output amplifiers when

the temperature exceeds 130°C. This function can be used to

protect the device in cases where power dissipation may be

exceeded if a number of output channels are simultaneously

short-circuited. A soft power-up will re-enable the output

amplifiers if the die temperature has dropped below 130°C.

W

if the operation is a write (R/ = 0) or a read (R/ = 1). DB11

W

to DB0 contains the control register data.

Control Register Contents

CR11: Power-Down Status. This bit is used to configure the

output amplifier state in power-down.

CR6 = 1: Thermal Monitor Enabled.

CR6 = 0: Thermal Monitor Disabled (default on power-up).

CR5: Don’t Care.

CR11 = 1. Amplifier output is high impedance (default on

power-up).

CR11 = 0. Amplifier output is 100 kΩ to ground.

CR10: REF Select. This bit selects the operating internal

reference for the AD5381. CR10 is programmed as follows:

CR4 to CR0: Toggle Function Enable. This function allows the

user to toggle the output between two codes loaded to the A

and B registers for each DAC. Control Register Bits CR4 to CR0

are used to enable individual groups of eight channels for

operation in toggle mode. A Logic 1 written to any bit enables

CR10 = 1: Internal reference is 2.5 V (AD5381-5 default), the

recommended operating reference for AD5381-5.

CR10 = 0: Internal reference is 1.25 V (AD5381-3 default),

the recommended operating reference for AD5381-3.

a group of channels; a Logic 0 disables a group.

is used

LDAC

to toggle between the two registers.

CR9: Current Boost Control. This bit is used to boost the

current in the output amplifier, thereby altering its slew rate.

This bit is configured as follows:

Table 15.

CR Bit

Group

Channels

32–39

24–3±

±6–23

8–±5

CR4

CR3

CR2

CR±

4

3

2

±

0

CR9 = 1: Boost Mode On. This maximizes the bias current

in the output amplifier, optimizing its slew rate but increasing

the power dissipation.

CR9 = 0: Boost Mode Off (default on power-up). This

reduces the bias current in the output amplifier and reduces

the overall power consumption.

CR0

0–7

Channel Monitor Function

CR8: Internal/External Reference. This bit determines if the

DAC uses its internal reference or an externally applied

reference.

REG1 = REG0 = 0, A5 to A0 = 001010

DB11–DB6 = Contain data to address the monitored channel.

A channel monitor function is provided on the AD5381. This

feature, which consists of a multiplexer addressed via the inter-

face, allows any channel output to be routed to the MON_OUT

pin for monitoring using an external ADC. In channel monitor

mode, VOUT39 becomes the MON_OUT pin, to which all

monitored pins are routed. The channel monitor function must

be enabled in the control register before any channels are routed

to MON_OUT. On the AD5381, DB11 to DB6 contain the

channel address for the monitored channel. Selecting Channel

Address 63 three-states MON_OUT.

CR8 = 1: Internal Reference Enabled. The reference output

depends on data loaded to CR10.

CR8 = 0: External Reference Selected (default on power-up).

CR7: Channel Monitor Enable (see Channel Monitor Function

section).

CR7= 1: Monitor Enabled. This enables the channel monitor

function. After a write to the monitor channel in the SFR

register, the selected channel output is routed to the

MON_OUT pin. VOUT39 operates at the MON_OUT pin.

CR7 = 0: Monitor Disabled (default on power-up). When the

monitor is disabled, the MON_OUT pin assumes its normal

DAC output function.

Rev. E | Page 24 of 40

Data Sheet

AD5381

Table 16. AD5381 Channel Monitor Decoding

REG1

0

•

REG0

0

•

A5

0

•

A4

0

•

A3

±

•

A2

0

•

A1

±

•

A0

0

•

DB11

0

±

•

DB10

0

±

0

•

DB9

0

±

0

±

0

•

DB8

0

±

0

±

0

±

0

±

0

±

•

DB8

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

•

DB6

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

0

±

•

DB5–DB0

MON_OUT

VOUT0

VOUT±

X

•

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT±0

VOUT±±

VOUT±2

VOUT±3

VOUT±4

VOUT±5

VOUT±6

VOUT±7

VOUT±8

VOUT±9

VOUT20

VOUT2±

VOUT22

VOUT23

VOUT24

VOUT25

VOUT26

VOUT27

VOUT28

VOUT29

VOUT30

VOUT3±

VOUT32

VOUT33

VOUT34

VOUT35

VOUT36

VOUT37

VOUT38

Undefined

•

0

±

0

±

0

±

0

±

X

Undefined

Three-State

REG1 REG0A5 A4 A3 A2 A1 A0

0

1

0

1

0

VOUT0

VOUT1

AD5381

CHANNEL

MONITOR

DECODING

VOUT39/MON_OUT

VOUT37

VOUT38

CHANNEL ADDRESS

DB11–DB6

Figure 28. Channel Monitor Decoding

Rev. E | Page 25 of 40

AD5381

Data Sheet

HARDWARE FUNCTIONS

RESET FUNCTION

FIFO OPERATION IN PARALLEL MODE

The AD5381 contains a FIFO to optimize operation when

operating in parallel interface mode. The FIFO Enable (level

sensitive, active high) is used to enable the internal FIFO. When

connected to DVDD, the internal FIFO is enabled, allowing the

user to write to the device at full speed. FIFO is only available in

parallel interface mode. The status of the FIFO EN pin is sam-

Bringing the

line low resets the contents of all internal

RESET

registers to their power-on reset state. Reset is a negative edge-

sensitive input. The default corresponds to m at full-scale and

to c at zero scale. The contents of the DAC registers are cleared,

setting VOUT0 to VOUT39 to 0 V. This sequence takes 270 µs.

The falling edge of

RESET

low for the duration, returning high when

initiates the reset process;

RESET

is low, all interfaces are disabled and all LDAC

goes

BUSY

is complete.

pled on power-up, and after a

or , to determine if

CLR RESET

the FIFO is enabled. In either serial or I²C interface modes,

FIFO EN should be tied low. Up to 128 successive instructions

can be written to the FIFO at maximum speed in parallel mode.

When the FIFO is full, any further writes to the device are

ignored. Figure 29 shows a comparison between FIFO mode

and non-FIFO mode in terms of channel update time. Figure 29

also outlines digital loading time.

While

BUSY

pulses are ignored. When

returns high, the part resumes

BUSY

normal operation and the status of the

pin is ignored

RESET

until the next falling edge is detected. Only perform a hardware

reset when the AD5381 is not in power-down mode.

ASYNCHRONOUS CLEAR FUNCTION

25

Bringing the

line low clears the contents of the DAC

CLR

registers to the data contained in the user configurable CLR

register and sets VOUT0 to VOUT39 accordingly. This func-

tion can be used in system calibration to load zero-scale and

full-scale to all channels. The execution time for a CLR is 35 µs.

WITHOUT FIFO

20

(CHANNEL UPDATE TIME)

15

AND

FUNCTIONS

LDAC

BUSY

10

is a digital CMOS output that indicates the status of the

BUSY

WITH FIFO

(CHANNEL UPDATE TIME)

AD5381. The value of x2, the internal data loaded to the DAC

data register, is calculated each time the user writes new data to

the corresponding x1, c, or m registers. During the calculation

5

WITH FIFO

(DIGITAL LOADING TIME)

of x2, the

output goes low. While

is low, the user

BUSY

0

1

4

7

10 13 16 19 22 25 28 31 34 37 40

NUMBER OF WRITES

can continue writing new data to the x1, m, or c registers, but

no DAC output updates can take place. The DAC outputs are

updated by taking the

Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)

input low. If

goes low

LDAC

is active, the

LDAC

event is stored and the DAC

LDAC

while

BUSY

outputs update immediately after

POWER-ON RESET

goes high. The user

BUSY

input permanently low, in which case the

The AD5381 contains a power-on reset generator and state

machine. The power-on reset resets all registers to a predefined

state and configures the analog outputs as high impedance.

may hold the

LDAC

DAC outputs update immediately after

goes high.

BUSY

also goes low during power-on reset and when a falling edge is

detected on the pin. During this time, all interfaces are

BUSY

The

pin goes low during the power-on reset sequencing,

BUSY

RESET

disabled and any events on

preventing data writes to the device.

are ignored.

LDAC

POWER-DOWN

The AD5381 contains an extra feature whereby a DAC register

is not updated unless its x2 register has been written to since

The AD5381 contains a global power-down feature that puts all

channels into a low power mode and reduces the analog power

consumption to 2 µA max and digital power consumption to

20 µA max. In power-down mode, the output amplifier can be

configured as a high impedance output or can provide a 100 kΩ

load to ground. The contents of all internal registers are retained

in power-down mode. When exiting power-down, the settling

time of the amplifier will elapse before the outputs settle to their

correct values.

the last time

was brought low. Normally, when

LDAC

is brought low, the DAC registers are filled with the contents

of the x2 registers. However, the AD5381 will only update the

DAC register if the x2 data has changed, thereby removing

unnecessary digital crosstalk.

Rev. E | Page 26 of 40

Data Sheet

AD5381

INTERFACES

The AD5381 contains both parallel and serial interfaces.

Furthermore, the serial interface can be programmed to be

either SPI-, DSP-, MICROWIRE-, or I²C-compatible. The

Figure 3 and Figure 5 show timing diagrams for a serial write

to the AD5381 in standalone and daisy-chain modes. The 24-bit

data-word format for the serial interface is shown in Table 17.

SER/

pin selects parallel and serial interface modes. In

PAR

/B This pin selects whether the data write is to the A or B

register when toggle mode is enabled. With toggle disabled, this

bit should be set to 0 to select the A data register.

A

serial mode, the

MICROWIRE-, or I²C-interface mode.

/I²C pin is used to select DSP-, SPI-,

SPI

The devices use an internal FIFO memory to allow high speed

successive writes in parallel interface mode. The user can con-

tinue writing new data to the device while write instructions are

R/ is the read or write control bit.

W

A5 to A0 are used to address the input channels.

being executed. The

signal indicates the current status of

REG1 and REG0 select the register to which data is written,

BUSY

as shown in Table 9.

the device, going low while instructions in the FIFO are being

executed. In parallel mode, up to 128 successive instructions

can be written to the FIFO at maximum speed. When the FIFO

is full, any further writes to the device are ignored.

DB11 to .DB0 contain the input data-word.

X is a don’t care condition.

Standalone Mode

To minimize both the power consumption of the device and the

on-chip digital noise, the active interface only powers up fully

when the device is being written to, that is, on the falling edge

By connecting the DCEN (daisy-chain enable) pin low, stand-

alone mode is enabled. The serial interface works with both a

continuous and a noncontinuous serial clock. The first falling

of

or the falling edge of

.

WR

SYNC

edge of

starts the write cycle and resets a counter that

SYNC

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL

INTERFACES

counts the number of serial clocks to ensure the correct number

of bits are shifted into the serial shift register. Any further edges

The serial interface can be operated with a minimum of three

wires in standalone mode or four wires in daisy-chain mode.

Daisy chaining allows many devices to be cascaded together to

on

, except for a falling edge, are ignored until 24 bits are

SYNC

clocked in. Once 24 bits are shifted in, the SCLK is ignored. In

order for another serial transfer to take place, the counter must

be reset by the falling edge of

increase system channel count. The SER/

pin must be tied

PAR

.

SYNC

high and the

/I²C pin (Pin 97) should be tied low to enable

SPI

the DSP-/SPI-/MICROWIRE-compatible serial interface. In

serial interface mode, the user does not need to drive the paral-

lel input data pins. The serial interface’s control pins are

, DIN, SCLK—Standard 3-wire interface pins.

SYNC

DCEN—Selects standalone mode or daisy-chain mode.

SDO—Data out pin for Daisy-chain mode.

Table 17. 40-Channel, 12-bit DAC Serial Input Register Configuration

MSB

LSB

X

A

W

R/

A5

A4

A3

A2

A±

A0

REG±

REG0

DB±±

DB±0

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB±

DB0

X

/B

Rev. E | Page 27 of 40

AD5381

Data Sheet

Daisy-Chain Mode

Readback Mode

Readback mode is invoked by setting the R/ bit = 1 in the

serial input register write. With R/ = 1, Bits A5 to A0, in

W

association with Bits REG1 and REG0, select the register to be

read. The remaining data bits in the write sequence are don’t

cares. During the next SPI write, the data appearing on the

SDO output will contain the data from the previously

addressed register.

For systems that contain several devices, the SDO pin can be

used to daisy-chain several devices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

number of serial interface lines.

W

By connecting the DCEN (daisy-chain enable) pin high, daisy-

chain mode is enabled. The first falling edge of

starts the

SYNC

write cycle. The SCLK is continuously applied to the input shift

register when is low. If more than 24 clock pulses are

SYNC

For a read of a single register, the NOP command can be used

in clocking out the data from the selected register on SDO.

Figure 30 shows the readback sequence. For example, to read

back the m register of Channel 0 on the AD5381, the following

sequence should be implemented. First, write 0x404XXX to the

AD5381 input register. This configures the AD5381 for read

mode with the m register of Channel 0 selected. Note that Data

Bits DB11 to DB0 are don’t cares. Follow this with a second

write, a NOP condition, 0x000000.

applied, the data ripples out of the shift register and appears

on the SDO line. This data is clocked out on the rising edge of

SCLK and is valid on the falling edge. By connecting the SDO

of the first device to the DIN input on the next device in the

chain, a multidevice interface is constructed. Twenty-four clock

pulses are required for each device in the system. Therefore, the

total number of clock cycles must equal 24N, where N is the

total number of AD538x devices in the chain.

When the serial transfer to all devices is complete,

is

During this write, the data from the m register is clocked out on

the DOUT line, that is, data clocked out will contain the data

from the m register in Bit DB11 to Bit DB0, and the top 10 bits

contain the address information as previously written. In

SYNC

taken high. This latches the input data in each device in the

daisy-chain and prevents further data from being clocked

into the input shift register.

readback mode, the

signal must frame the data. Data is

SYNC

If

is taken high before 24 clocks are clocked into the part,

SYNC

clocked out on the rising edge of SCLK and is valid on the

falling edge of the SCLK signal. If the SCLK idles high between

the write and read operations of a readback operation, the first

this is considered a bad frame and the data is discarded.

The serial clock can be either a continuous or a gated clock. A

continuous SCLK source can only be used if it can be arranged

bit of data is clocked out on the falling edge of

.

SYNC

that

is held low for the correct number of clock cycles. In

SYNC

gated clock mode, a burst clock containing the exact number of

clock cycles must be used and

must be taken high after

SYNC

the final clock to latch the data.

SCLK

SYNC

24

48

DB23

DB0

DB23

DB0

DIN

INPUT WORD SPECIFIES REGISTER TO BE READ

NOP CONDITION

DB23

DB0

DB23

DB0

SDO

UNDEFINED

SELECTED REGISTER DATA CLOCKED OUT

Figure 30. Serial Readback Operation

Rev. E | Page 28 of 40

Data Sheet

AD5381

I²C SERIAL INTERFACE

AD5381 Slave Addresses

The AD5381 features an I²C-compatible 2-wire interface

consisting of a serial data line (SDA) and a serial clock line

(SCL). SDA and SCL facilitate communication between the

AD5381 and the master at rates up to 400 kHz. Figure 6 shows

the 2-wire interface timing diagrams that incorporate three

different modes of operation. In selecting the I²C operating

A bus master initiates communication with a slave device by

issuing a START condition followed by the 7-bit slave address.

When idle, the AD5381 waits for a START condition followed

by its slave address. The LSB of the address word is the Read/

Write (R/ ) bit. The AD5381 is a receive only device; when

W

communicating with the AD5381, R/ = 0. After receiving the

W

proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK

by pulling SDA low for one clock cycle.

mode, first configure serial operating mode (SER/

= 1)

PAR

and then select I²C mode by configuring the

/I²C pin to a

SPI

Logic 1. The device is connected to the I²C bus as a slave device

(that is, no clock is generated by the AD5381). The AD5381 has

a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSB are hard-

coded and the 2 LSB are determined by the state of the AD1

and AD0 pins. The facility to hardware configure AD1 and AD0

allows four of these devices to be configured on the bus.

The AD5381 has four different user programmable addresses

determined by the AD1 and AD0 bits.

Write Operation

There are three specific modes in which data can be written to

the AD5381 DAC.

I²C Data Transfer

4-Byte Mode

When writing to the AD5381 DACs, the user must begin

One data bit is transferred during each SCL clock cycle. The

data on SDA must remain stable during the high period of the

SCL clock pulse. Changes in SDA while SCL is high are control

signals that configure START and STOP conditions. Both SDA

and SCL are pulled high by the external pull-up resistors when

the I²C bus is not busy.

with an address byte (R/ = 0) after which the DAC acknowl-

W

edges that it is prepared to receive data by pulling SDA low.

The address byte is followed by the pointer byte; this addresses

the specific channel in the DAC to be addressed and is also

acknowledged by the DAC. Two bytes of data are then written

to the DAC, as shown in Figure 31. A STOP condition follows.

This allows the user to update a single channel within the

AD5381 at any time and requires four bytes of data to be

transferred from the master.

START and STOP Conditions

A master device initiates communication by issuing a START

condition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high. A START condition

from the master signals the beginning of a transmission to

the AD5381. The STOP condition frees the bus. If a repeated

START condition (Sr) is generated instead of a STOP condition,

the bus remains active.

3-Byte Mode

In 3-byte mode, the user can update more than one channel in a

write sequence without having to write the device address byte

each time. The device address byte is only required once; sub-

sequent channel updates require the pointer byte and the data

bytes. In 3-byte mode, the user begins with an address byte

Repeated START Conditions

(R/ = 0), after which the DAC will acknowledge that it is pre-

W

A repeated START (Sr) condition may indicate a change of data

direction on the bus. Sr can be used when the bus master is

writing to several I²C devices and wants to maintain control of

the bus.

pared to receive data by pulling SDA low. The address byte is

followed by the pointer byte. This addresses the specific channel

in the DAC to be addressed and is also acknowledged by the

DAC. This is then followed by the two data bytes. REG1 and

REG0 determine the register to be updated.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any

8-bit data-word. ACK is always generated by the receiving

device. The AD5381 devices generate an ACK when receiving

an address or data by pulling SDA low during the ninth clock

period. Monitoring ACK allows for detection of unsuccess-

ful data transfers. An unsuccessful data transfer occurs if a

receiving device is busy or if a system fault has occurred.

In the event of an unsuccessful data transfer, the bus master

should reattempt communication.

If a STOP condition does not follow the data bytes, another

channel can be updated by sending a new pointer byte followed

by the data bytes. This mode only requires three bytes to be

sent to update any channel once the device has been initially

addressed, and reduces the software overhead in updating the

AD5381 channels. A STOP condition at any time exits this mode.

Figure 32 shows a typical configuration.

Rev. E | Page 29 of 40

AD5381

Data Sheet

SCL

1

0

1

0

1

AD1

AD0

R/W

0

A5

A4

A3

A2

A1

A0

SDA

START COND

BY MASTER

ACK BY

AD538x

MSB

ACK BY

AD538x

ADDRESS BYTE

POINTER BYTE

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

STOP

COND

BY

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

MASTER

Figure 31. 4-Byte AD5381, I²C Write Operation

SCL

SDA

1

0

1

0

1

AD1

AD0

R/W

0

A5

A4

A3

A2

A1

A0

START COND

BY MASTER

ACK BY

AD538x

MSB

ACK BY

AD538x

ADDRESS BYTE

POINTER BYTE FOR CHANNEL "N"

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "N"

SCL

SDA

0

A5

A4

A3

A2

A1

A0

MSB

ACK BY

AD538x

POINTER BYTE FOR CHANNEL "NEXT CHANNEL"

SCL

SDA

REG1 REG0

MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY STOP COND

AD538x BY MASTER

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "NEXT CHANNEL"

Figure 32. 3-Byte AD5381, I²C Write Operation

Rev. E | Page 30 of 40

Data Sheet

AD5381

2-Byte Mode

PARALLEL INTERFACE

The SER/

PAR

pin must be tied low to enable the parallel

Following initialization of 2-byte mode, the user can update

channels sequentially. The device address byte is only required

once and the pointer address pointer is configured for auto-

increment or burst mode.

interface and disable the serial interfaces. Figure 7 shows the

timing diagram for a parallel write. The parallel interface is

controlled by the following pins.

The user must begin with an address byte (R/ = 0), after

W

CS

Active low device select pin.

which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The address byte is followed by a

specific pointer byte (0xFF) that initiates the burst mode of

operation. The address pointer initializes to Channel 0, the data

following the pointer is loaded to Channel 0, and the address

pointer automatically increments to the next address.

WR

On the rising edge of

to Pin A0 are latched; data present on the data bus is loaded into

the selected input registers.

, with

WR

low, the addresses on Pin A5

CS

The REG0 and REG1 bits in the data byte determine which

register will be updated. In this mode, following the initializa-

tion, only the two data bytes are required to update a channel.

The channel address automatically increments from Address 0

to Channel 39 and then returns to the normal 3-byte mode of

operation. This mode allows transmission of data to all

channels in one block and reduces the software overhead in

configuring all channels. A STOP condition at any time exits

this mode. Toggle mode is not supported in 2-byte mode.

Figure 33 shows a typical configuration.

REG0, REG1 Pins

The REG0 and REG1 pins determine the destination register of

the data being written to the AD5381. See Table 9.

Pin A5 to Pin A0

Each of the 40 DAC channels can be individually addressed.

Pin DB11 to Pin DB0

The AD5381 accepts a straight 12-bit parallel word on DB11 to

DB0, where DB11 is the MSB and DB0 is the LSB.

SCL

SDA

1

0

1

0

1

AD1

AD0

R/W

A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

START COND

BY MASTER

ACK BY

CONVERTER

MSB

ACK BY

CONVERTER

ADDRESS BYTE

POINTER BYTE

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CHANNEL 0 DATA

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

CONVERTER

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CHANNEL 1 DATA

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK BY

STOP

CONVERTER

CONVERTER COND

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

BY

MASTER

CHANNEL N DATA FOLLOWED BY STOP

Figure 33. 2-Byte, 1²C Write Operation

Rev. E | Page 3± of 40

AD5381

Data Sheet

When data is being transmitted to the AD5381, the

line

SYNC

MICROPROCESSOR INTERFACING

is taken low (PC7). Data appearing on the MOSI output is valid

on the falling edge of SCK. Serial data from the MC68HC11 is

transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle.

Parallel Interface

The AD5381 can be interfaced to a variety of 16-bit microcon-

trollers or DSP processors. Figure 35 shows the AD5381 family

interfaced to a generic 16-bit microcontroller/DSP processor.

The lower address lines from the processor are connected to A0

to A5 on the AD5381. The upper address lines are decoded to

DVDD

MC68HC11

AD5381

SER/PAR

RESET

provide a

,

signal for the AD5381. The fast interface

CS LDAC

MISO

MOSI

SCK

PC7

SDO

DIN

timing of the AD5381 allows direct interface to a wide variety

of microcontrollers and DSPs, as shown in Figure 35.

SCLK

SYNC

2

AD5381 to MC68HC11

SPI/I C

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1), clock polarity bit

(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is

configured by writing to the SPI control register (SPCR)—see

the MC68HC11 user manual. SCK of the MC68HC11 drives the

SCLK of the AD5381, the MOSI output drives the serial data

line (D_IN) of the AD5381, and the MISO input is driven from

Figure 34. AD5381-to-MC68HC11 Interface

D_OUT. The SYNC signal is derived from a port line (PC7).

µCONTROLLER/

DSP PROCESSOR

AD5381

1

D15

REG1

REG0

D11

DATA

BUS

D0

CS

UPPER BITS OF

ADDRESS BUS

ADDRESS

DECODE

LDAC

A5

A4

A5

A4

A3

A2

A1

A0

WR

A3

A2

A1

A0

R/W

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5381-to-Parallel Interface

Rev. E | Page 32 of 40

Data Sheet

AD5381

DVDD

8XC51

AD5381 to PIC16C6x/7x

AD5381

SER/PAR

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the Clock Polarity Bit = 0. This is done

by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 microcontroller user manual.

RESET

RxD

SDO

DIN

TxD

P1.1

SCLK

SYNC

In this example I/O, Port RA1 is being used to pulse

SYNC

2

and enable the serial port of the AD5381. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive read/write operations

may be needed depending on the mode. Figure 36 shows the

connection diagram.

SPI/I C

Figure 37. AD5381-to-8051 Interface

AD5381 to ADSP-BF527

Figure 38 shows a serial interface between the AD5381 and the

ADSP-BF527. The ADSP-BF527 should be set up to operate in

SPORT transmit alternate framing mode. The ADSP-BF527

SPORT is programmed through the SPORT control register and

configured as follows: internal clock operation, active low

framing, and 16-bit word length. Transmission is initiated by

writing a word to the Tx register after the SPORT has been

enabled.

DVDD

PIC16C6X/7X

AD5381

SER/PAR

RESET

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

DIN

SCLK

SYNC

2

SPI/I C

Figure 36. AD5381-to-PIC16C6x/7x Interface

AD5381

AD5381 to 8051

ADSP-BF527

The AD5381 requires a clock synchronized to the serial data.

The 8051 serial interface must therefore be operated in Mode 0.

In this mode, serial data enters and exits through RxD, and a

shift clock is output on TxD. Figure 37 shows how the 8051 is

connected to the AD5381. Because the AD5381 shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted. The AD5381

requires its data to be MSB first. Since the 8051 outputs the

LSB first, the transmit routine must take this into account.

SPORT_TFS

SPORT_RFS

SPORT_TSCK

SPORT_RSCK

SPORT_DT0

SPORT_DR0

SYNC

SCLK

DIN

SDO

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. AD5381-to-ADSP-BF527 Interface

Rev. E | Page 33 of 40

AD5381

Data Sheet

APPLICATIONS INFORMATION

Alternatively, a load switch such as the ADP196 can be used to

delay the first power supply until the second power supply turns

on. Figure 41 shows a typical configuration using the ADP196.

In this case, the AVDD is applied first. This voltage does not

appear at the AVDD pin of the AD5381 until the DVDD is

applied and brings the EN pin high. The result is that the AVDD

and DVDD are both applied to the AD5381 at the same time.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit board on

which the AD5381 is mounted should be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. If the AD5381 is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only, a star ground

point established as close to the device as possible.

Table 18. Power Supply Sequencing

First

Power

Supply

Second

Power

Supply

Recommended Operation

See Figure 39

See Figure 40

For supplies with multiple pins (AVDD, DVDD), these pins

should be tied together. The AD5381 should have ample supply

bypassing of 10 µF in parallel with 0.1 µF on each supply,

located as close to the package as possible and ideally right

up against the device. The 10 µF capacitors are the tantalum

bead type. The 0.1 µF capacitor should have low effective series

resistance (ESR) and effective series inductance (ESI), like the

common ceramic types that provide a low impedance path to

ground at high frequencies, to handle transient currents due to

internal logic switching.

AVDD = 3 V DVDD ≥ 3 V

DVDD = 3 V AVDD ≥ 3 V

AVDD =

DVDD

DVDD =

AVDD

See Figure 39; this operation

assumes separate analog and

digital supplies.

DVDD =

AVDD

AVDD =

DVDD

See Figure 40; this operation

assumes separate analog and

digital supplies.

AVDD = 5 V DVDD = 3 V

DVDD = 5 V AVDD = 3 V

See Figure 4±

Hardware reset or see Figure 42

AVDD = 3V

DVDD ≥ 3V

The power supply lines of the AD5381 should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digital ground

to avoid radiating noise to other parts of the board, and should

never be run near the reference inputs. A ground line routed

between the D_INand SCLK lines will help reduce crosstalk

between them (this is not required on a multilayer board

because there will be a separate ground plane, but separat-

ing the lines will help). It is essential to minimize noise on

the REFOUT/REFIN line.

SD103C OR

EQUIVALENT

AVDD

DVDD

DGND

AD5381

DAC

GND

SIGNAL

GND

AGND

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to

each other. This reduces the effects of feedthrough through

the board. A micro-strip technique is by far the best, but is

not always possible with a double-sided board. In this tech-

nique, the component side of the board is dedicated to the

ground plane while signal traces are placed on the solder side.

Figure 39. AVDD First Followed by DVDD

AVDD ≥ 3V

DVDD = 3V

SD103C OR

EQUIVALENT

POWER SUPPLY SEQUENCING

AVDD

DVDD

DGND

For proper operation of the AD5381, apply DVDD first and

then AVDD either simultaneously or within 10 ms of DVDD.

This sequence ensures that the power-on reset circuitry sets the

registers to their default values and keeps the analog outputs at

0 V until a valid write operation takes place. When AVDD

cannot be applied within 10 ms of DVDD, issue a hardware

reset. This triggers the power-on reset circuitry and loads the

default register values. In cases where the initial power supply

has the same or a lower voltage than the second power supply, a

Schottky diode can be used to temporarily supply power until

the second power supply turns on. Table 18 lists the power

supply sequences and the recommended diode connection.

AD5381

DAC

GND

SIGNAL

AGND

GND

Figure 40. DVDD First Followed by AVDD

Rev. E | Page 34 of 40

Data Sheet

AD5381

Figure 44 shows a typical configuration when using the internal

reference. On power-up, the AD5381 defaults to an external

reference; therefore, the internal reference needs to be config-

ured and turned on via a write to the AD5381 control register.

Control Register Bit CR10 allows the user to choose the

reference value; Bit CR8 is used to select the internal reference.

It is recommended to use the 2.5 V reference when AVDD =

5 V, and the 1.25 V reference when AVDD= 3 V.

ADP196

AVDD

VIN1

VIN2

VOUT1

VOUT2

AVDD

EN AGND

DVDD

AGND DGND

AVDD

DVDD

Figure 41. AVDD Power Supply Controlled by a Load Switch

AD5381

0.1µF

ADP196

10µF

0.1µF

DVDD

AVDD

VIN1

VIN2

VOUT1

VOUT2

DVDD

EN AGND

AVDD

DVDD

VOUT0

REFOUT/REFIN

AVDD

AGND DGND

0.1µF

AD5381

REFGND

VOUT39

DGND

Figure 42. DVDD Power Supply Controlled by a Load Switch

DAC_GND SIGNAL_GND AGND

TYPICAL CONFIGURATION CIRCUIT

Figure 43 shows a typical configuration for the AD5381-5

when configured for use with an external reference. In the

circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins

are tied together to a common AGND. AGND and DGND are

connected together at the AD5381 device. On power-up, the

AD5381 defaults to external reference operation. All AVDD

lines are connected together and driven from the same 5 V

source. It is recommended to decouple close to the device with a

0.1 µF ceramic and a 10 µF tantalum capacitor. In this application,

the reference for the AD5381-5 is provided externally from

either an ADR421 or ADR431 2.5 V reference. Suitable external

references for the AD5381-3 include the ADR3412 1.2 V

reference. The reference should be decoupled at the

Figure 44. Typical Configuration with Internal Reference

Digital connections have been omitted for clarity. The AD5381

contains an internal power-on reset circuit with a 10 ms brown-

out time. If the power supply ramp rate exceeds 10 ms, the user

should reset the AD5381 as part of the initialization process to

ensure the calibration data is loaded correctly into the device.

REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

AVDD

DVDD

0.1µF

10µF

0.1µF

ADR431/

ADR421

AVDD

DVDD

VOUT0

REFOUT/REFIN

0.1µF

AD5381-5

REFGND

VOUT39

DGND

DAC_GND SIGNAL_GND AGND

Figure 43. Typical Configuration with External Reference

Rev. E | Page 35 of 40

AD5381

Data Sheet

Note that B registers can only be loaded when toggle mode is

enabled. The sequence of events when configuring the AD5381

for toggle mode is

1. Enable toggle mode for the required channels via the

control register.

MONITOR FUNCTION

The AD5381 channel monitor function consists of a multiplexer

addressed via the interface, allowing any channel output to be

routed to this pin for monitoring using an external ADC. In

channel monitor mode, VOUT39 becomes the MON_OUT pin,

to which all monitored signals are routed. The channel monitor

function must be enabled in the control register before any

channels are routed to MON_OUT. Table 16 contains the

decoding information required to route any channel to

MON_OUT. Selecting Channel Address 63 three-states

MON_OUT. Figure 45 shows a typical monitoring circuit

implemented using a 12-bit SAR ADC in a 6-lead SOT-23

package. The controller output port selects the channel to be

monitored, and the input port reads the converted data from

the ADC.

2. Load data to the A registers.

3. Load data to the B registers.

4. Apply

.

LDAC

is used to switch between the A and B registers in

LDAC

determining the analog output. The first

configures the

LDAC

output to reflect data in the A registers. This mode offers signif-

icant advantages if the user wants to generate a square wave at

the output of all 40 channels, as might be required to drive a

liquid crystal-based variable optical attenuator.

In this case, the user writes to the control register and enables

the toggle function by setting CR4 to CR2 = 0, thus enabling the

five groups of eight for toggle mode operation. The user must

AVDD

then load data to all 40 A and B registers. Toggling

sets

LDAC

DIN

VOUT0

SYNC

SCLK

OUTPUT PORT

the output values to reflect the data in the A and B registers.

The frequency of the

square wave output.

determines the frequency of the

LDAC

VDD

CS

AD5381

AD7476

VOUT39/MON_OUT

VIN

SCLK

INPUT PORT

Toggle mode is disabled via the control register. The first

following the disabling of the toggle mode will update the out-

puts with the data contained in the A registers.

LDAC

SDATA

GND

CONTROLLER

AGND

THERMAL MONITOR FUNCTION

VOUT38

DAC_GND SIGNAL_GND

The AD5381 contains a temperature shutdown function to

protect the chip if multiple outputs are shorted. The short-

circuit current of each output amplifier is typically 40 mA.

Operating the AD5381 at 5 V leads to a power dissipation of

200 mW per shorted amplifier. With five channels shorted, this

leads to an extra watt of power dissipation. For the 100-lead

L QF P, t h e θ_JAis typically 44°C/W.

Figure 45. Typical Channel Monitoring Circuit

TOGGLE MODE FUNCTION

The toggle mode function allows an output signal to be gener-

ated using the

control signal that switches between two

LDAC

DAC data registers. This function is configured using the SFR

control register as follows. A write with REG1 = REG0 = 0 and

A5 to A0 = 001100 specifies a control register write. The toggle

mode function is enabled in groups of eight channels using Bit

CR4 to Bit CR0 in the control register. See the AD5381 control

register description. Figure 46 shows a block diagram of toggle

mode implementation. Each of the 40 DAC channels on the

AD5381 contain an A and B data register.

The thermal monitor is enabled by the user via CR6 in the

control register. The output amplifiers on the AD5381 are

automatically powered down if the die temperature exceeds

approximately 130°C. After a thermal shutdown has occurred,

the user can re-enable the part by executing a soft power-up if

the temperature has dropped below 130°C or by turning off the

thermal monitor function via the control register.

DATA

REGISTER

A

DAC

REGISTER

VOUT

12-BIT DAC

DATA

REGISTER

B

INPUT

DATA REGISTER

INPUT

LDAC

CONTROL INPUT

A/B

Figure 46. Toggle Mode Function

Rev. E | Page 36 of 40

Data Sheet

AD5381

OPTICAL ATTENUATORS

UTILIZING FIFO

Based on its high channel count, high resolution, monotonic

behavior, and high level of integration, the AD5381 is ideally

targeted at optical attenuation applications used in dynamic

gain equalizers, variable optical attenuators (VOAs), and optical

add-drop multiplexers (OADMs). In these applications, each

wavelength is individually extracted using an arrayed wave

guide; its power is monitored using a photodiode, transimped-

ance amplifier and ADC in a closed-loop control system. The

AD5381 controls the optical attenuator for each wavelength,

ensuring that the power is equalized in all wavelengths before

being multiplexed onto the fiber. This prevents information loss

and saturation from occurring at amplification stages further

along the fiber.

The AD5381 FIFO mode optimizes total system update rates

in applications where a large number of channels need to be

updated. FIFO mode is only available when parallel interface

mode is selected. The FIFO EN pin is used to enable the FIFO.

The status of FIFO EN is sampled during the initialization

sequence. Therefore, the FIFO status can only be changed by

resetting the device.

In a telescope that provides for the cancellation of atmospheric

distortion, for example, a large number of channels need to be

updated in a short period of time. In such systems, as many as

400 channels need to be updated within 40 µs. Four hundred

channels require the use of 10 AD5381s. With FIFO mode enabled,

the data write cycle time is 40 ns; therefore, each group consisting

of 40 channels can be fully loaded in 1.6 µs. In FIFO mode, a

complete group of 40 channels will update in 14.4 µs. The time

taken to update all 400 channels is 14.4 µs + 9 × 1.6 µs = 28.8 µs.

Figure 48 shows the FIFO operation scheme.

ADD

DROP

PORTS

OPTICAL

SWITCH

PHOTODIODES

11

12

ATTENUATOR

DWDM

IN

DWDM

OUT

ATTENUATOR

FIBRE

AWG FIBRE

AWG

1n–1

1n

ATTENUATOR

TIA/LOG AMP

(AD8304/AD8305)

ADG731

(40:1 MUX)

N:1 MULTIPLEXER

AD5381,

40-CHANNEL,

12-BIT DAC

AD7671

(0V TO 5V, 1MSPS)

CONTROLLER

16-BIT ADC

Figure 47. OADM Using the AD5381 as Part of an Optical Attenuator

GROUP A

CHNLS 0–39 CHNLS 40–79

GROUP B

GROUP C

CHNLS

80–119

GROUP D

CHNLS

120–159

GROUP E

CHNLS

160–199

GROUP F

CHNLS

200–239

GROUP G

CHNLS

240–279

GROUP H

CHNLS

280–319

GROUP I

CHNLS

320–359

GROUP J

CHNLS

360–399

FIFO DATA LOAD

GROUP A

FIFO DATA LOAD

GROUP B

FIFO DATA LOAD

GROUP J

1.6µs

OUTPUT UPDATE

TIME FOR GROUP A

OUTPUT UPDATE

TIME FOR GROUP J

14.4µs

OUTPUT UPDATE

TIME FOR GROUP B

14.4µs

TIME TO UPDATE 400 CHANNELS = 28.8µs

Figure 48. Using FIFO Mode 400 Channels Updated in Under 30 µs

Rev. E | Page 37 of 40

AD5381

Data Sheet

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

1.60 MAX

0.75

0.60

0.45

100

1

76

75

PIN 1

14.20

14.00 SQ

13.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

25

51

50

0.15

0.05

26

SEATING

PLANE

0.08

0.27

0.22

0.17

COPLANARITY

VIEW A

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BED

Figure 49. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Output

Channels

Linearity

Error (LSB)

Package

Description

Package

Option

Model¹

Resolution

±2 Bits

AVDD Range

2.7 V to 3.6 V

4.5 V to 5.5 V

AD538±BSTZ-3

AD538±BSTZ-3-REEL

AD538±BSTZ-5

AD538±BSTZ-5-REEL

EVAL-AD5380EBZ

–40°C to +85°C

40

±±

±00-Lead LQFP

Evaluation Kit

ST-±00-±

^±Z = RoHS Compliant Part.

Rev. E | Page 38 of 40

Data Sheet

NOTES

AD5381

Rev. E | Page 39 of 40

AD5381

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D03732-0-5/14(E)

Rev. E | Page 40 of 40


型号：	AD5381BSTZ-3
厂家：	ADI
描述：	40-Channel 3 V/5 V Single-Supply 12-Bit Voltage-Output DAC 转换器
文件：	总41页 (文件大小：845K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5381BSTZ-3 [ADI]

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AD5381BSTZ-5-REEL

AD5382

AD5382BST-3

AD5382BST-3-REEL

AD5382BST-5

AD5382BST-5-REEL

AD5382BST-REEL

AD5382BSTZ-3

AD5382BSTZ-5

AD5383