AD5290YRMZ100-R7 [ADI]
Compact 30 V / 15,-15 V 256-Position Digital Potentiometer; 紧凑型30 V / 15 ， -15 V 256位数字电位计
| 型号： | AD5290YRMZ100-R7 |
| 厂家： | 
ADI |
| 描述： | Compact 30 V / 15,-15 V 256-Position Digital Potentiometer |
| 文件： | 总20页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Compact +30 V / ± ±1 V ꢀ156-oꢁstsoꢂ
Dsgstal -oteꢂtsometer
Data Sheet
AD1ꢀ90
FEATURES
FUNCTIONAL BLOCK DIAGRAM
256 position
10 kΩ, 50 kΩ, 100 kΩ
V
AD5290
DD
SDO
SDI
Q
+20 V to +30 V single-supply operation
10 V to 15 V dual-supply operation
3-wire SPI®-compatible serial interface
Low temperature coefficient 35 ppm/°C typical
THD 0.006% typical
A
8-BIT
8
8
8-BIT
SERIAL
LATCH
REGISTER
W
B
D
CK
Midscale preset
RS
Compact MSOP-10 package
Automotive temperature range: −40°C to +125°C
iCMOS™1 process technology
CLK
CS
POR
V
SS
DGND
APPLICATIONS
High voltage DAC
Figure 1.
Programmable power supply
Programmable gain and offset adjustment
Programmable filters and delays
Actuator control
Audio volume control
Mechanical potentiometer replacement
GENERAL DESCRIPTION
The AD5290 is one of the few high voltage, high performance,
and compact digital potentiometers2, 3 in the market at present.
This device can be used as a programmable resistor or resistor
divider. The AD5290 performs the same electronic adjustment
function as mechanical potentiometers, variable resistors, and
trimmers, with enhanced resolution, solid-state reliability, and
superior temperature stability.
With digital rather than manual control, the AD5290 provides
layout flexibility and allows closed-loop dynamic controllability.
The AD5290 is available in MSOP-10 package and has 10 kΩ,
50 kΩ, and 100 kΩ options. All parts are guaranteed to operate
over the −40°C to +125°C extended automotive temperature range.
1 iCMOS™ Process Technology. For analog systems designers who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the
development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, and
increased ac and dc performance.
2 The terms digital potentiometer and RDAC are used interchangeably.
3 The RDAC segmentation is protected by U.S. Patent Number 5,495,245.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
rights of third parties that may result from its use. Specifications subject to change without notice. No
Tel: 781.329.4700
www.analog.com
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
Fax: 781.461.3113 ©2005-2011 Analog Devices, Inc. All rights reserved.
AD5290
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Programming the Variable Resistor......................................... 15
Programming the Potentiometer Divider............................... 16
3-Wire Serial Bus Digital Interface.......................................... 16
Daisy Chain Operation.............................................................. 16
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range ......................................... 17
Power-Up and Power-Down Sequences.................................. 17
Layout and Power Supply Biasing............................................ 17
Applications..................................................................................... 18
High Voltage DAC...................................................................... 18
Programmable Power Supply ................................................... 18
Audio Volume Control .............................................................. 18
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—10 kΩ Version................................ 3
Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 5
Interface Timing Characteristics................................................ 7
3-Wire Digital Interface................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Descriptions............................................ 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 15
REVISION HISTORY
11/11—Rev. B to Rev. C
7/09—Rev. 0 to Rev. A
Change to Figure 33 ....................................................................... 18
4/10—Rev. A to Rev. B
Changes to Figure 29...................................................................... 16
Updated Outline Dimensions ....................................................... 20
Changes to Features Section ............................................................1
Changes to Ordering Guide.......................................................... 20
12/05—Revision 0: Initial Version
Rev. C | Page 2 of 20
Data Sheet
AD5290
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 kΩ VERSION
VDD/VSS = 15 V 10%, VA = VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
R-INL
∆RAB
RWB, VA = NC
RWB, VA = NC
TA = +25°C
−1
−1.5
−30
0.3
0.7
+1
+1.5
+30
LSB
LSB
%
ppm/°C
Ω
(∆RAB/RAB)/∆T×106 VAB = VDD, wiper = no connect
35
50
RW
100
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
INL
DNL
−1
−1
0.3
0.3
5
−4
+3
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
(∆VW/VW)/∆T×106 Code = 0x80
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−6
0
0
+5
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
VSS
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
45
60
1
Capacitance6
CW
ICM
pF
Common-Mode Leakage
VA = VB = VW
nA
DIGITAL INPUTS AND OUTPUTS
CS
Input Logic High ( , CLK, SDI)
VIH
VIL
VOH
VOL
IIL
2.4
4.9
V
CS
0.8
V
Input Logic Low ( , CLK, SDI)
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current
RPull-up = 2.2 kΩ to 5 V
IOL = 1.6 mA
VIN = 0 V or 5 V
V
V
µA
pF
0.4
1
Input Capacitance6
CIL
5
POWER SUPPLIES
Positive Supply Current
IDD
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
ΔVDD/ΔVSS = 15 V 10%
15
50
μA
μA
μW
Negative Supply Current
Power Dissipation7
ISS
−0.01 −1
765
PDISS
PSRR
Power Supply Rejection Ratio
−0.15
0.08 +0.15 %/%
Rev. C | Page 3 of 20
AD5290
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS6, 8, 9
Symbol
Conditions
Min
Typ1
Max
Unit
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
BW
THDW
tS
Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 10 V, VB = 0 V, 1 LSB error
band
470
0.006
4
kHz
%
µs
Resistor Noise Voltage
eN_WB
RWB = 5 kΩ, f = 1 kHz
9
nV/√Hz
1 Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 All parts have a 35 ppm/°C temperature coefficient.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic-level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = +15 V and VSS = −15 V.
Rev. C | Page 4 of 20
Data Sheet
AD5290
ELECTRICAL CHARACTERISTICS—50 KΩ, 100 KΩ VERSIONS
VDD/VSS = 15 V 10%, VA = +VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
R-INL
∆RAB
RWB, VA = NC
RWB, VA = NC
TA = +25°C
−0.5
−1
−30
0.1
0.5
+0.5
+1
+30
LSB
LSB
%
ppm/°C
Ω
(∆RAB/RAB)/∆T×106 VAB = VDD, wiper = no connect
35
50
RW
100
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
INL
DNL
−1
−1
0.5
0.5
5
+1
+1
LSB
LSB
ppm/°C
Differential Nonlinearity4
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T×106 Code = 0x80
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−2.5
0
−1.6
+0.6
0
+1.5
LSB
LSB
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
VSS
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND,
code = 0x80
f = 1 MHz, measured to GND,
code = 0x80
45
60
1
Capacitance6
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (CS, CLK, SDI)
Input Logic Low (CS, CLK, SDI)
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current
VA = VB = VW
nA
VIH
VIL
VOH
VOL
IIL
2.4
4.9
V
0.8
V
RPull-up = 2.2 kΩ to 5 V
IOL = 1.6 mA
VIN = 0 V or 5 V
V
V
µA
pF
0.4
1
Input Capacitance6
CIL
5
POWER SUPPLIES
Positive Supply Current
IDD
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
15
50
μA
Negative Supply Current
Power Dissipation7
ISS
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
VIH = +5 V or VIL = 0 V,
VDD/VSS = 15 V
−0.01 −1
765
0.01 +0.05
μA
PDISS
PSRR
μW
%/%
Power Supply Rejection Ratio
ΔVDD/ΔVSS = 15 V 10%
−0.05
Rev. C | Page 5 of 20
AD5290
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS6, 8, 9
Symbol
Conditions
Min
Typ1
Max
Unit
Bandwidth −3 dB
BW
RAB = 50 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 10 V, VB = 0 V,
1 LSB error band
90
50
0.002
4
kHz
kHz
%
Total Harmonic Distortion
VW Settling Time
THDW
tS
µs
Resistor Noise Voltage
eN_WB
RWB = 25 kΩ, f = 1 kHz
20
nV√Hz
1 Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3 All parts have a 35 ppm/°C temperature coefficient.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification
limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = +15 V and VSS = −15 V.
Rev. C | Page 6 of 20
Data Sheet
AD5290
INTERFACE TIMING CHARACTERISTICS
Table 3.
Parameter
1, 2
Symbol
Conditions
Min
Typ
Max
Unit
MHz
ns
Clock Frequency
Input Clock Pulse Width
Data Setup Time
fCLK
tCH, tCL
tDS
4
Clock level high or low
120
30
ns
Data Hold Time
CLK to SDO Propagation Delay3
tDH
tPD
20
10
ns
ns
RPull-up = 2.2 kΩ, CL < 20 pF
100
CS Setup Time
tCSS
120
150
10
ns
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCSW
tCSH0
tCSH
tCS1
ns
ns
120
120
ns
ns
1 See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. Switching characteristics are measured using VDD = +15 V and VSS = −15 V.
2 Guaranteed by design and not subject to production test.
3 Propagation delay depends on the value of VDD, RPull-up, and CL.
Rev. C | Page 7 of 20
AD5290
Data Sheet
3-WIRE DIGITAL INTERFACE
Data is loaded MSB first.
1
0
SDI
(DATA IN)
D
D
X
X
Table 4. AD5290 Serial Data-Word Format
tDS
tDH
B7
D7
MSB
27
B6
B5
B4
B3
B2
B1
B0
D0
LSB
20
1
0
SDO
D'
D'
X
X
D6
D5
D4
D3
D2
D1
(DATA OUT)
tPD_MAX
tCH
1
0
tCS1
CLK
tCSH0
tCL
1
0
1
0
1
0
1
0
SDI
CLK
CS
D7 D6 D5 D4 D3 D2 D1
D0
tCSH
tCSS
1
tCSW
tS
CS
0
V
RDAC REGISTER LOAD
DD
V
OUT
±1 LSB ERROR BAND
0V
V
OUT
±1 LSB
Figure 2. AD5290 3-Wire Digital Interface Timing Diagram
(VA = VDD, VB = 0 V, VW = VOUT
Figure 3. Detail Timing Diagram
)
Rev. C | Page 8 of 20
Data Sheet
AD5290
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
−0.3 V, +35 V
+0.3 V, −16.5 V
−0.3 V, +35 V
VSS, VDD
Maximum Current
IWB, IWA Pulsed
ESD CAUTION
20 mA
5 mA
IWB Continuous (RWB ≤ 6 kΩ, A Open,
VDD/VSS = 30 V/0 V)1
IWA Continuous (RWA ≤ 6 kΩ, B Open,
VDD/VSS = 30 V/0 V)1
Digital Input and Output Voltages to GND
5 mA
0 V, +7 V
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
−40°C to +125°C
+150°C
−65°C to +150°C
245°C
2
)
Lead Temperature
(Soldering, 10 sec to 30 sec)
Thermal Resistance2 θJA: MSOP-10
230°C/W
1 The maximum terminal current is bound by the maximum current handling
of the switches, maximum power dissipation of the package, and the
maximum applied voltage across any two of the following at a given
resistance: A terminal, B terminal, and W terminal.
2 Package power dissipation = (TJMAX – TA)/θJA
.
Rev. C | Page 9 of 20
AD5290
Data Sheet
PIN CONFIGURATION AND DESCRIPTIONS
A
B
1
2
3
4
5
10
9
W
V
DD
AD5290
TOP VIEW
(Not to Scale)
V
8
SDO
SDI
SS
GND
CS
7
6
CLK
Figure 4. AD5290 Pin Configuration
Table 6. AD5290 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
A
B
VSS
GND
CS
A Terminal. VSS ≤ VA ≤ VDD.
B Terminal. VSS ≤ VB ≤ VDD.
Negative Supply. Connect to 0 V for single-supply applications.
Digital Ground.
CS
Chip Select Input; Active Low. When returns high, data is loaded into the wiper register.
Serial Clock Input. Positive edge triggered.
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor.
It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages.
CLK
SDI
SDO
9
10
VDD
W
Positive Power Supply.
W Terminal. VSS ≤ VW ≤ VDD.
Rev. C | Page 10 of 20
Data Sheet
AD5290
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
V
= 16.5V
V
= 16.5V
DD
DD
0.8
0.6
–40°C
+25°C
+125°C
–40°C
+25°C
+125°C
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 5. Resistance Step Position Nonlinearity Error vs. Code
Figure 8. Potentiometer Divider Differential Nonlinearity Error vs. Code
20
1.0
V
= 16.5V
DD
0.8
0.6
I
@ V /V = 30V/0V
DD DD SS
–40°C
+25°C
+125°C
16
12
8
I
@ V /V = ±15V
DD SS
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
4
I
@ V /V = 30V/0V
DD SS
SS
0
I
@ V /V = ±15V
DD SS
SS
–4
–40
–20
0
20
40
60
80
100
120
0
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 6. Resistance Step Change Differential Nonlinearity Error vs. Code
Figure 9. Supply Current IDD vs. Temperature
1.0
V
= 16.5V
120
100
80
60
40
20
0
V
/V = ±15V
DD SS
DD
0.8
0.6
100kΩ
–40°C
+25°C
+125°C
0.4
0.2
0
50kΩ
–0.2
–0.4
–0.6
–0.8
–1.0
10kΩ
–40
–20
0
20
40
60
80
100
120
0
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 7. Potentiometer Divider Nonlinearity Error vs. Code
Figure 10. Total Resistance vs. Temperature
Rev. C | Page 11 of 20
AD5290
Data Sheet
0
–6
100
80
0x80
0x40
0x20
0x10
0x08
0x04
10k
–12
–18
–24
–30
–36
–42
–48
–54
–60
50k
60
100k
40
20
0
–20
–40
–60
–80
–100
0x02
0x01
1k
10k
100k
1M
0
32
64
96
128
160
192
224
256
(Hz)
CODE (Decimal)
Figure 14. 50 kΩ Gain vs. Frequency vs. Code
Figure 11. (ΔRWB/RWB)/ΔT Rheostat Mode Tempco
0
–6
100
80
0x80
0x40
0x20
0x10
0x08
10k
–12
–18
–24
–30
–36
–42
–48
–54
–60
60
50k
100k
40
20
0
0x04
0x02
0x01
–20
–40
–60
–80
–100
1k
10k
100k
1M
0
32
64
96
128
160
192
224
256
(Hz)
CODE (Decimal)
Figure 15. 100 kΩ Gain vs. Frequency vs. Code
Figure 12. (ΔVWB/VWB)/ΔT Potentiometer Mode Tempco
0
0x80
–6
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x08
0x04
0x02
0x01
1k
10k
100k
1M
(Hz)
Figure 16. Midscale Transition Glitch
Figure 13. 10 kΩ Gain vs. Frequency vs. Code
Rev. C | Page 12 of 20
Data Sheet
AD5290
6
5
4
3
2
1
0
–60
CODE = 80 , V /V = ±15V, V /V = ±10V
DD SS
V
V
V
/V = 30V/0V
= V
DD
= 0V
H
A
B
DD SS
A
B
R
= 10kΩ
–40
AB
+PSRR @ V /V = ±15V DC ± 10% p-p AC
DD SS
R
= 50kΩ
AB
–20
–PSRR @ V /V = ±15V DC ± 10% p-p AC
DD SS
R
= 100kΩ
AB
0
100
0
64
128
CODE (Decimal)
192
256
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 17. Power Supply Rejection vs. Frequency
Figure 20. Theoretical Maximum Current vs. Code
1
140
120
100
80
V
/V = ±15V
DD SS
V
V
V
= +15V
= –15V
DD
SS
CODE = MIDSCALE
= 1V
V
IN
RMS
= +5V
DIG
10kΩ
0.01
CODE = AA
100kΩ
60
50kΩ
0.001
0.0001
40
CODE = FF
20
0
10k
10
100
1k
FREQUENCY (Hz)
10k
100k
100k
FREQUENCY (Hz)
1M
10M
Figure 18. Total Harmonic Distortion Plus Noise vs. Frequency
Figure 21. Supply Current IDD vs. Frequency
10
1
V
V
V
= +15V
= –15V
= +5V
V
/V = ±15V
DD SS
DD
CODE = MIDSCALE
= 1kHz
SS
DIG
f
IN
8
6
4
2
0
0.1
0.01
CODE = AA
50kΩ
10kΩ
CODE = FF
100kΩ
0.001
10k
100k
FREQUENCY (Hz)
1M
10M
0.001
0.01
0.1
1
10
AMPLITUDE (V)
Figure 19. Total Harmonic Distortion Plus Noise vs. Amplitude
Figure 22. Supply Current ISS vs. Frequency
Rev. C | Page 13 of 20
AD5290
Data Sheet
1000
100
V
/V = ±16.5V
DD SS
10
0
1
2
3
4
5
DIGITAL INPUT VOLTAGE V (V)
IH
Figure 23. Supply Current vs. Digital Input Voltage
Figure 25. Large Signal Settling Time, Code = 0x00 to 0xFF
Figure 24. Digital Feedthrough
Rev. C | Page 14 of 20
Data Sheet
AD5290
THEORY OF OPERATION
PROGRAMMING THE VARIABLE RESISTOR
where:
D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register from 0 to 255.
Rheostat Operation
The part operates in the rheostat mode when only two termi-
nals are used as a variable resistor. The unused terminal can
be floating or tied to the W terminal as shown in Figure 26.
R
AB is the end-to-end resistance.
RW is one of the wiper resistances contributed by the on
resistance of an internal switch.
A
A
A
The AD5290 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
VDD. The wiper resistance, RW, is a function of VDD and
temperature. Contrary to the temperature coefficient of the RAB,
which is only 35 ppm/°C, the temperature coefficient of the wiper
resistance is significantly higher because the wiper resistance
doubles from 25°C to 125°C. As a result, the user must take into
consideration the contribution of RW on the desirable
W
W
W
B
B
B
Figure 26. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 10 kΩ, 50 kΩ, and 100 kΩ with 30% toler-
ance and has 256 tap points accessed by the wiper terminal. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Figure 27 shows a simplified RDAC structure.
resistance. On the other hand, the wiper resistance is insensitive
to the tap point potential. As a result, RW remains relatively flat
at a given VDD and temperature at various codes.
A
Assuming that an ideal 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for the programming code
of 0x00 where SWB is closed. The minimum resistance between
Terminal W and Terminal B is, therefore, generally 150 Ω. The
second connection is the first tap point, which corresponds to
189 Ω (RWB = 1/256 × RAB + 3RW = 39 Ω + 150 Ω) for code 0x01,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 10,110 Ω.
4R
4R
S
S
2R
2R
4R
S
S
S
R
W
R
R
S
In the zero-scale condition, a finite total wiper resistance of
150 Ω is present. Regardless of which setting the part is oper-
ating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum dc current of 5 mA
or pulse current of 20 mA. Otherwise, degradation, or possible
destruction of the internal switch contact, can occur.
W
R
W
S
8-BIT ADDRESS
DECODER
2R
2R
S
S
R
W
4R
4R
S
S
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA.
RWA starts at the maximum resistance value and decreases as
the data loaded into the latch increases. The general equation
for this operation is
B
Figure 27. AD5290 Simplified RDAC Circuit.
(RS = Step Resistor, RW = Wiper Resistor)
256 − D
256
RWA (D) =
×RAB + 3×RW
(2)
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5290 employs a
3-stage segmentation approach as shown in Figure 27. As
a result, the general equation determining the digitally
programmed output resistance between the W terminal
and B terminal is
D
256
RWB (D) =
× RAB + 3× RW
(1)
Rev. C | Page 15 of 20
AD5290
Data Sheet
PROGRAMMING THE POTENTIOMETER DIVIDER
3-WIRE SERIAL BUS DIGITAL INTERFACE
Voltage Output Operation
CS
The AD5290 contains a 3-wire digital interface ( , CLK,
and SDI). The 8-bit serial word must be loaded MSB first.
The format of the word is shown in Table 4. The positive edge
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic fami-
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
CS
lies work well. When
is low, the clock loads data into the
serial register on each positive clock edge.
V
I
A
The data setup and data hold times in the Specifications section
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
W
V
O
B
CS
internal RDAC register when the
Extra MSB bits are ignored.
line returns to logic high.
Figure 28. Potentiometer Mode Configuration
DAISY CHAIN OPERATION
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256 positions of the potentiometer divider. The
general equation defining the output voltage at VW with respect
to ground for any valid input voltage applied to Terminal A and
Terminal B is
SDO shifts out the SDI content in the previous frame; thus it
can be used for daisy-chaining multiple devices. The SDO pin
contains an open drain N-Ch MOSFET and requires a pull-
up resistor if the SDO function is used. Users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO to SDI interface
can induce time delay to the subsequent devices.
D
256
256 − D
256
For example, in Figure 29, if two AD5290s are daisy-chained, a
total of 16 bits of data are required for each operation. The first
set of eight bits goes to U2, and the second set of eight bits goes
VW (D) =
×VA +
×VB
(3)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
CS
to U1. The
should be kept low until all 16 bits are clocked
into their respective serial registers. The
is then pulled high
CS
to complete the operation.
+5V
AD5290
AD5290
U2
R
PU
2.2kΩ
U1
µC
MOSI
SDO
SDI
SDO
CLK
SDI
SCLK SS
CS
CS
CLK
Figure 29. Daisy Chain Configuration
Rev. C | Page 16 of 20
Data Sheet
AD5290
ESD PROTECTION
POWER-UP AND POWER-DOWN SEQUENCES
All digital inputs are protected with a series input resistor and
a Zener ESD structure, as shown in Figure 30. These structures
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W
(Figure 31), it is important to power VDD/VSS before applying
any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that VDD/VSS
are powered unintentionally and affect the system. Similarly,
VDD/VSS should be powered down last. The ideal power-up
sequence is as follows: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA, VB, VW, and the digital
inputs is not important, as long as they are powered after
VDD/VSS.
CS
apply to digital input pins, Pin , Pin CLK, Pin SDI, and
Pin SDO.
340Ω
LOGIC
GND
Figure 30. Equivalent ESD Protection Circuit
All analog terminals are also protected by Zener ESD protection
diodes, as shown in Figure 31.
LAYOUT AND POWER SUPPLY BIASING
V
DD
It is good practice to use a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
A
W
B
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR),
1 µF to 10 µF tantalum or electrolytic capacitors, should be
applied at the supplies to minimize any transient disturbance
and to filter low frequency ripple. Figure 32 illustrates the basic
supply-bypassing configuration for the AD5290.
V
SS
Figure 31. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The ground pin of the AD5290 is a digital ground reference.
To minimize the digital ground bounce, the AD5290 digital
ground terminal should be joined remotely to the analog
ground (Figure 32).
The AD5290 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. The AD5290 can operate in single supply from +4.5 V to
+33 V or dual supply from 4.5 V to 16.5 V. T h e AD5290 is
functional at low supply voltages such as 4.5 V, but the
performance parameters are not guaranteed.
V
DD
V
DD
+
C1
C3
C4
10µF
0.1µF
0.1µF
AD5290
The voltages present on Terminal A, Terminal B, and Terminal W
that are more positive than VDD or more negative than VSS are
clamped by the internal forward-biased diodes (Figure 31).
+
C2
10µF
V
SS
V
SS
GND
Figure 32. Power Supply Bypassing
Rev. C | Page 17 of 20
AD5290
Data Sheet
APPLICATIONS
HIGH VOLTAGE DAC
AUDIO VOLUME CONTROL
AD5290 can be configured as a high voltage DAC, with out-
put voltage as high as 30 V. The circuit is shown in Figure 33.
The output is
Because of its good THD performance and high voltage
capability, AD5290 can be used as a digital volume control.
If AD5290 is used directly as an audio attenuator or gain
amplifier, a large step change in the volume level at any arbi-
trary time can lead to an abrupt discontinuity of the audio
signal causing an audible zipper noise. To prevent this, a zero-
D
R
[1.2 V (1 2 )]
(4)
VO(D)
256
R1
CS
where D is the decimal code from 0 to 255.
crossing window detector can be inserted to the
line to
delay the device update until the audio signal crosses the
window. Since the input signal can operate on top of any
dc level rather than absolute zero volt level, zero-crossing in
this case means the signal is ac-coupled, and the dc offset
level is the signal zero reference point.
V
DD
V
DD
R
BIAS
U2
U1A
V+
OP284
V–
AD5290
D1
U1B
100kΩ
ADR512
The configuration to reduce zipper noise (Figure 35) and the
results of using this configuration are shown in Figure 36. The
input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B
(Figure 35). U6 is used to establish the signal zero reference.
The upper limit of the comparator is set above its offset and,
therefore, the output pulses high whenever the input falls
between 2.502 V and 2.497 V (or 0.005 V window) in this
example. This output is AND’ed with the chip select signal
such that the AD5290 updates whenever the signal crosses
the window. To avoid a constant update of the device, the
chip select signal should be programmed as two pulses, rather
than as one shown in Figure 36.
V
OUT
B
OP284
R2
R1
Figure 33. High Voltage DAC
PROGRAMMABLE POWER SUPPLY
With a boost regulator, such as ADP1611, AD5290 can be used
as the variable resistor at the regulator’s FB pin to provide the
programmable power supply (Figure 34). The output is
D
(
256) RAB
R2
(5)
VO 1.23 V [1
]
In Figure 35, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
AD5290’s VDD is derived from the output. Initially, L1 acts as
a short, and VDD is one diode voltage drop below +5 V. The
output slowly establishes the final value.
U1
5V
AD5290
V
C
10F
IN
ADP1611
DD
IN
U2
A
C1
0.1F
L1
4.7H
W
R1
100k
V
OUT
SW
RT
B
D1
1.23V
C
C
OUT
10F
FB
SS
COMP
R2
8.5k
R
C
SS
GND
220k
22nF
C
C
150pF
Figure 34. Programmable Power Supply
Rev. C | Page 18 of 20
Data Sheet
AD5290
V
C1
IN
5V
1µF
U1
V
+15V
R1
+5V
100kΩ
DD
C3
0.1µF
A
AD5290
U2
V+
C2
0.1µF
R2
200Ω
ADCM371
V–
+15V
R4
V
SS
W
90kΩ
–15V
U4A
U5
V+
U4B
V
4
5
100kΩ
OUT
6
1
2
+5V
7408
CS
7408
R5
10kΩ
V–
U3
V+
ADCM371
V–
5V
CLK
SDI
CLK
SDI
B
–15V
U6
V+
CS
GND
R3
100kΩ
AD8541
V–
Figure 35. Audio Volume Control with Zipper Noise Reduction
1
2
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
Figure 36. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35
(The Command of Volume Change May Occur at Any Time, but the Level Change Occurs Only Near the Zero-Crossing Window)
Rev. C | Page 19 of 20
AD5290
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 37. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
RAB (kΩ)
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
Package Option
RM-10
RM-10
RM-10
RM-10
Branding
D4U
D4U
D4T
D4T
AD5290YRMZ10
AD5290YRMZ10-R7
AD5290YRMZ50
AD5290YRMZ50-R7
AD5290YRMZ100
AD5290YRMZ100-R7
EVAL-AD5290EBZ
10
10
50
50
100
100
10
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
RM-10
RM-10
D4V
D4V
1 Z = RoHS Compliant Part.
©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04716-0-11/11(C)
Rev. C | Page 20 of 20
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