AD5290YRMZ50-RL7 [ADI]

Compact +30V/【15V 256-Position Digital Potentiometer; 小巧+ 30V / 15V 【 256位数字电位计


型号：	AD5290YRMZ50-RL7
厂家：	ADI
描述：	Compact +30V/【15V 256-Position Digital Potentiometer 小巧+ 30V / 15V 【 256位数字电位计数字电位计
文件：	总11页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Compact +30V/± ±1V ꢀ156-oꢁstsoꢂ ꢃsistaꢄ

-oteꢂtsometer

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

MSOP-±0 package. AD5290 can be operated from a single

supply +2.7 V to +30 V or dual supply ±2.7 V to ±±5 V. All

parts are guaranteed to operate over the automotive

temperature range of -40°C to +±05°C.

FEATURES

256-position

+2.7V to +30V Single Supply Operation

2.7V to 15V Dual Supply Operation

End-to-end resistance 10 kΩ, 50 kΩ, 100 kΩ

Low temperature coefficient 35 ppm/°C

Power-on preset to midscale

SPI compatible interface

Automotive temperature range –40°C to +105°C

Compact MSOP-10 (3 mm × 4.9 mm) package

FUNCTIONAL BLOCK DIAGRAM

AD5290

APPLICATIONS

Programmable Gain and Offset

Programmable Power Supply

Industrial Actuator Control

LED Array Driver

Audio Volume Control

General Purpose DAC Replacement

Mechanical Potentiometer Replacement

SDO

8-Bit

SERIAL

REG

LATCH

SDI

CLK

POR

GENERAL OVERVIEW

The AD5290 is a low cost, compact 2.9 mm × 3 mm

+30V/±±5V, 256-position digital potentiometer. This device

performs the same electronic adjustment function as

mechanical potentiometers or variable resistors, with enhanced

resolution, solid-state reliability, and superior low temperature

coefficient performance.

DGND

Figure 1.

The wiper settings are controllable through an SPI compatible

digital interface. The resistance between the wiper and either

end point of the fixed resistor varies linearly with respect to the

digital code transferred into the RDAC latch.

Note:

The terms digital potentiometer and RDAC are used interchangeably.

The AD5290 is available in ±0k, 50k, and ±00kΩ in compact

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

ELECTRICAL CHARACTERISTICS—±0 kΩ, 10 kΩ, ±00 kΩ VERSIONS

(V_DD/V_SS= ±1ꢀV±1±ꢁ or ±ꢀV±1±ꢁꢂ V_A= +V_DDꢂ V_B= V_SS/±Vꢂ -4±°C < T_A< +1±ꢀ°C unless otherwise noted)

Table 1.

Parameter

Symbol

Conditions

Min Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R-DNL

R-INL

∆R_AB

R_WBꢂ V_A= no connect

T_A= 2ꢀ°C

–1

–2

–3±

±±.1

±±.2ꢀ

+3±

LSB

ꢁ

(∆R_AB/R_AB)/∆T*1±⁶V_AB= V_DDꢂ

Wiper = no connect

V_DD= 3± V

3ꢀ

ppm/°C

Wiper Resistance

R_W

ꢀ±

2±±

12±

4±±

Ω

V_DD= ꢀ V

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE

Resolution

Bits

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(∆V_W/V_W)/∆T*1±⁶

V_WFSE

–1

±±.1

±±.3

ꢀ

–1

LSB

ppm/°C

LSB

Code = ±x8±

Code = ±xFF

Code = ±x±±

–3

Zero-Scale Error

V_WZSE

RESISTOR TERMINALS

Voltage Range^ꢀ

V_AꢂBꢂW

C_AꢂB

V_SS

V_DD

Capacitance⁶Aꢂ B

f = 1 MHzꢂ measured to

GNDꢂ Code = ±x8±

f = 1 MHzꢂ measured to

GNDꢂ Code = ±x8±

4ꢀ

6±

Capacitance⁶W

C_W

I_CM

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

V_A= V_B= V_W

V_IH

V_IL

2.4

4.9

_DD= +5V or +15V

Input Logic Low

Output Logic High

Output Logic Low

±.8

V_OH

V_OL

R_L= 2.2 kΩ to +5 V

±.4

±1

I_OL= 1.6mA, V_LOGIC= +5V,

V_DD= +15V

Input Current

I_I

C_I

V_IN= ± V or +1ꢀ V

µA

Input Capacitance

POWER SUPPLIES

Power Supply Range

ꢀ

Dual Supply Range

±2.ꢃ

±16.ꢀ

+3±

V_DD/V_SS

Power Supply Range

V_DD

Single Supply Rangeꢂ V_SS= +2.ꢃ

± V

Supply Current6

I_DD

I_SS

V_IH= ꢀ V or V_IL= ± Vꢂ V_DD

+ꢀ V

V_IH= ꢀ V or V_IL= ± Vꢂ V_DD

+1ꢀ V

V_IH= ꢀ V or V_IL= ± Vꢂ V_SS= -

ꢀ V or –1ꢀ V

±.1

1±

µA

Supply Current

±.ꢃꢀ

±.±2

±.1

3±

Power Dissipation^ꢃ

P_DISS

PSS

V_IH= ꢀ V or V_IL= ± Vꢂ V_DD

+1ꢀ Vꢂ V_SS= -1ꢀ V

Power Supply Sensitivity

±±.±1

±±.±2 ꢁ/ꢁ

∆V_DD= +1ꢀV ±1±ꢁꢂ or

∆V_SS= -1ꢀV ±1±ꢁꢂ Code =

Midscale

DYNAMIC CHARACTERISTICS^{6ꢂ 8}

Bandwidth –3dB

R_AB= 1± kΩ/ꢀ± kΩ/1±± kΩꢂ

Code = ±x8±

ꢀ2ꢀ/12ꢀ/6±

kHz

Rev. Pr C | Page 2 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

Total Harmonic Distortion

THD_W

t_S

V_A=1 V rmsꢂ V_B= ± Vꢂ

f = 1 kHzꢂ R_AB= 1± kΩ

V_A= ꢀ Vꢂ V_B= ± Vꢂ

±1 LSB error band

±.±ꢀ

ꢁ

V_WSettling Time (1± kΩ/ꢀ± kΩ/1±± kΩ)

Resistor Noise Voltage Density

µs

e_{N_WB}

R_WB= 2ꢀ kΩ

nV/√Hz

Rev. Pr C | Page 3 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

TIMING CHARACTERISTICS— ±0 kΩ, 10 kΩ, ±00 kΩ VERSIONS

(V_DD/V_SS= ±1ꢀV±1±ꢁ or ±ꢀV±1±ꢁꢂ V_A= +V_DDꢂ V_B= ±Vꢂ -4±°C < T_A< +1±ꢀ°C unless otherwise noted.)

Table 2.

Parameter

Symbol

Conditions

Min Typ¹Max Unit

SPI INTERFACE TIMING CHARACTERISTICS^{6ꢂ 8ꢂ9}(Specifications Apply to All Parts)

Clock Frequency

Input Clock Pulsewidth

Data Setup Time

f_CLK

t_CHꢂ t_CL

t_DS

MHz

Clock level high or low

12±

3±

Data Hold Time

t_DH

2±

CLK to SDO Propagation Delay

t_PD

1±

1±±

_PU= 1KΩꢂ C_L< 2±pF

t_CSS

12±

1ꢀ±

TBD

12±

Setup Time

t_CSW

t_CSH±

t_CSH1

t_CS1

High Pulsewidth

CLK Fall to

Fall Hold Time

Rise Hold Time

Rise to Clock Rise Setup

NOTES

Typical specifications represent average readings at +2ꢀ°C and V_DD= ꢀ V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

ꢀ.

ꢃ.

V_AB= V_DDꢂ Wiper (V_W) = no connect.

INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A=V_DDand V_B=± V.

Resistor terminals Aꢂ Bꢂ W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

_DISSis calculated from (I_DD× V_DD+ I_SS× V_SS) CMOS logic level inputs result in minimum power dissipation.

All dynamic characteristics use V_DD/ V_SS= ±ꢀ V.

See timing diagram for location of measured values. All input control voltages are specified with t_R= t_F= 2 ns (1±ꢁ to 9±ꢁ of 3 V) and timed from a voltage level

of 1.ꢀ V.

Rev. Pr C | Page 4 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

ABSOLUTE MAXIMUM RATINGS^±

(T_A= +25°C, unless otherwise noted.)

Table 3.

Storage Temperature

–6ꢀ°C to +1ꢀ±°C

Lead Temperature (Solderingꢂ 1± – 3± sec) 24ꢀ°C

Thermal Resistance²θ_JA: MSOP-1±

23±°C/W

Parameter

Value

NOTES

¹Maximum terminal current is bounded by the maximum current handling

of the switchesꢂ maximum power dissipation of the packageꢂ and maximum

applied voltage across any two of the Aꢂ Bꢂ and W terminals at a given

resistance.

V_DDto VSS

–±.3 V to +33 V

+±.3 V to –16.ꢀ V

V_SSꢂ V_DD

V_DDto GND

V_SSto GND

²Package power dissipation = (T_JMAX– T_A)/θ_JA

V_Aꢂ V_Bꢂ V_Wto GND

Maximum Current

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods

may affect device reliability.

_WBꢂ I_WAPulsed

_WBContinuous (R_WB≤ 1 kΩꢂ A open)¹

±2± mA

±ꢀ mA

I_WAContinuous (R_WA≤ 1 kΩꢂ B open)¹

Digital Inputs Voltage to GND

Digital Output Voltage to GND

Operating Temperature Range

±ꢀ mA

V_DD+ ±.3 V

± Vꢂ +3± V

–4±°C to +1±ꢀ°C

1ꢀ±°C

Maximum Junction Temperature (T_JMAX

)

Rev. Pr C | Page ꢀ of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

-IN CONFIGURATION ANꢃ FUNCTION ꢃESCRI-TIONS

VDD

AD5290

TOP VIEW

VSS

SDO

SDI

GND

CLK

Figure 2. AD5290 Pin Configuration

Table 7. AD5290 Pin Function Descriptions

Menmonic

Description

^{A Terminal. V}_SS≤ V_A≤ V_DD

^{B Terminal. V}_SS≤ V_B≤ V_DD

ꢀ

V_SS

Negative Supply. Connect to zero volts for single supply applications.

GND

Digital Ground.

Chip Select Inputꢂ Active Low. When returns highꢂ data will be loaded into the Wiper

ꢃ

CLK

SDI

Serial Clock Input. Positive edge triggered

Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.

SDO

Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-

up resistor. It shifts out the previous 8 SDI bits that allows daisy-chain operation of multiple

packages

V_DD

Positive Power Supply

1±

^{W Terminal. V}_SS≤ V_W≤ V_DD

Rev. Pr C | Page 6 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

S-I Iꢂterface

SDI

CLK

Table 4. AD5290 Serial Data-Word Format

Dꢃ

MSB

2^ꢃ

B6 B5 B4 B3 B2 B1 B0

RDAC REGISTER LOAD

D6 Dꢀ D4 D3 D2 D1 D±

LSB

2^±

VOUT

Figure 3. AD5290 SPI Interface Timing Diagram

(V_A= VDD, V_B= 0 V, V_W= V_OUT

)

SDI

(DATA IN)

t_DS

t_CH

t_CS1

t_CH

CLK

t_CSH1

t_CL

t_CSHO

t_CSS

t_CSW

t_S

V_DD

VOUT

±1LSB

Figure 2. SPI Interface Detailed Timing Diagram (V_A= VDD, V_B= 0 V, V_W= V_OUT

)

Rev. Pr C | Page ꢃ of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

O-ERATION

Aꢃ1ꢀ90

The AD5290 is a 256-position digitally controlled variable

resistor device that can be controlled digitally through SPI

interface.

Since a finite wiper resistance of 60 Ω is present in the zero-

scale condition, care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of

no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

An internal power-on preset places the wiper at midscale

during power-on, which simplifies the fault condition recovery

at power-up.

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper W and terminal A also produces a

complementary resistance R_WA. When these terminals are used,

the B terminal can be opened or shorted to W. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

DETERMINING THE VARIABLE RESISTANCE

AND VOLTAGE

Rheostat Mode Operation

If only the W-to-B or W-to-A terminals are used as variable

resistors, the unused terminal can be opened or shorted with W.

This operation is called rheostat mode (Figure 3).

256 − D

256

(2)

R_WA(D) =

×R_AB+ R_W

Table 2. R_WAvs. Codes; R_AB=10 kΩ and

B Terminal Is Opened

D (Dec)

R_WA(Ω)

Output State

Full-Scale

Midscale

1 LSB

Figure 3. Rheostat Mode Configuration

2ꢀꢀ

128

6±

ꢀ±6±

1±±2±

1±±6±

The nominal resistance (R_AB) of the RDAC has 256 contact

points accessed by the wiper terminal, plus the B terminal

contact if R_WBis considered. The 8-bit data in the RDAC latch is

decoded to select one of the 256 settings. Assuming that a ±0

kΩ part is used, the wiper’s first connection starts at the B

terminal for data 0x00. Such connection yields a minimum of

60 Ω resistance between terminals W and B because of the 60 Ω

wiper contact resistance. The second connection is the first tap

point, which corresponds to 99 Ω (R_WB= (±) × R_AB/256 + R_W)

for data 0x0±, and so on. Each LSB data value increase moves

the wiper up the resistor ladder until the last tap point is reached

at ±0020 Ω ((255) × R_AB/256 + R_W). Figure 6 shows a simplified

diagram of the equivalent RDAC circuit. The general equation

determining R_WBis

Zero-Scale

The typical distribution of the resistance tolerance from device

to device is process lot dependent, and it is possible to have

±30ꢀ tolerance.

R_S

R_WB(D) =

× R_AB+ R_W

(±)

256

RDAC

R_W

where:

LATCH

R_S

AND

D is the decimal equivalent of the 8-bit binary code.

DECODER

_ABis the end-to-end resistance.

_Wis the wiper resistance contributed by the on-resistance of

Figure 6. AD5290 Equivalent RDAC Circuit

the internal switch.

Table 1. R_WBvs. Codes; R_AB= 10 kΩ and

the A Terminal Is Opened

Potentiometer Mode Operation

If all three terminals are used, the operation is called the

potentiometer mode. The most common configuration is the

voltage divider operation (Figure 7).

D (Dec)

R_WB(Ω)

1±±2±

ꢀ±6±

Output State

2ꢀꢀ

128

Full-Scale (R_AB+ R_W)

Midscale

1 LSB

6±

Zero-Scale (Wiper Contact Resistance)

Rev. Pr C | Page 8 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

The data setup and data hold times in the specification table

determine the valid timing requirements. The AD5290 uses an

8-bit serial input data register word that is transferred to the

internal RDAC register when the

returns to logic high. If

dataword contains more than 8-bit, the extra MSB bits will be

ignored.

Figure 7. Potentiometer Mode Configuration

Ignoring the effect of the wiper resistance, the transfer function

is simply

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures shown in 8 and Figure 9. This

applies to the digital input pins SDI, CLK, and

V_W(D) =

V_A

(3)

256

340Ω

LOGIC

A more accurate calculation, which includes the wiper

resistance effect, yields

Figure 8. ESD Protection of Digital Pins

R_AB+ R_W

256

R_AB+ 2R_W

(4)

V_W(D) =

V_A

A,B,W

If there is an applied voltage at the B terminal, then the transfer

function becomes

Figure 9. ESD Protection of Resistor Terminals

256

256 − D

256

V_W(D) =

V_A

V_B

(5)

TERMINAL VOLTAGE OPERATING RANGE

Unlike in rheostat mode operation where the absolute tolerance

is high, potentiometer mode operation yields an almost ratio-

metric function of D/256 with a relatively small error contributed

by the RW terms, and therefore the tolerance effect is almost

cancelled. Although the thin film step resistor R_Sand CMOS

switches resistance R_Whave very different temperature coeffi-

cients, the ratiometric adjustment also reduces the overall

temperature coefficient effect to 5 ppm/°C, except at low value

codes where R_Wdominates.

The AD5290 V_DDand GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on terminals A, B, and W that

exceed V_DDor GND will be clamped by the internal forward

biased diodes (see Figure ±0).

Potentiometer mode operations include others such as op amp

input, feedback resistor networks, and other voltage scaling

applications. A, W, and B terminals can in fact be input or

output terminals provided that |V_A|, |V_W|, and |V_B| do not

exceed |V_DD| and |V_SS|.

Figure 10. Maximum Terminal Voltages Set by V_DDand V_SS

SPI COMPATIBLE 3-WIRE SERIAL BUS

The AD5290 contains a 3-wire SPI compatible digital interface

POWER-UP SEQUENCE

(SDI, , and CLK). The 8-bit serial word must be loaded MSB

Since the ESD protection diodes limit the voltage compliance at

terminals A, B, and W (see Figure ±0), it is important to power

V_DD–to-GND and V_SS-to-GND before applying any voltage to

terminals A, B, and W; otherwise, the diode will be forward

biased such that V_DDwill be powered unintentionally and may

affect the rest of the user’s circuit. The ideal power-up sequence

is in the following order: GND, V_SS,V_DD, digital inputs, and then

first. The format of the word is shown in Table .

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well.

should start high, when it

goes low, the clock loads data into the serial register on each

positive clock edge (see Figure 3).

Rev. Pr C | Page 9 of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

Aꢃ1ꢀ90

V_A/B/W. The relative order of powering V_A, V_B, V_W, and the

digital inputs is not important as long as they are powered after

V_DDand V_SSwith respect to GND.

AD5290

SDO

LAYOUT AND POWER SUPPLY BYPASSING

2.2K

Ω

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

MOSI

SDI

SDO

SDI

SCLK SS

CLK

Similarly, it is also a good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to

the device should be bypassed with disc or chip ceramic

capacitors of 0.0± µF to 0.± µF. Low ESR ± µF to ±0 µF tantalum

or electrolytic capacitors should also be applied at the supplies

to minimize any transient disturbance and low frequency ripple

(see Figure 4). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

Figure 12. Daisy Chain Configuration

AD5290

Figure 4. Power Supply Bypassing

DAISY CHAIN OPERATION

The serial data output pin (SDO) can be used to daisy chain

multiple devices for simultaneous operations, see Figure ±2. The

SDO pin contains an open drain N-Ch FET and requires a pull-

up resistor. Users need to tie the SDO pin of one package to the

SDI pin of the next package. If many devices are daisy-chained,

users may need to increase the clock period to accommodate

the time delay introduced by the pull-up resistors and the

capacitive loading at the SDO-SDI interface, see Figure ±2.

If two AD5290 are daisy chained, this requires total ±6 bits of

data. The first 8 bits goes to U2 and the second 8 bits goes to

U±. The

should be kept low until all ±6 bits are clocked into

their respective serial registers. The

complete the operation.

is then pulled high to

Rev. Pr C | Page 1± of 11

-reꢄsmsꢂary Techꢂscaꢄ ꢃata

OUTLINE ꢃIMENSIONS

Aꢃ1ꢀ90

3.00 BSC

4.90 BSC

3.00 BSC

PIN 1

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.00

0.27

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 5. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Ordering Guide

Model¹

R_AB(kΩ)

1±

ꢀ±

Temperature Range

–4±°C to +1±ꢀ°C

Package Description

MSOP-1±

Package Option

RM-1±

Branding

D4U

D4T

ADꢀ29±YRMZ1±

ADꢀ29±YRMZ1±-RLꢃ

ADꢀ29±YRMZꢀ±

ADꢀ29±YRMZꢀ±-RLꢃ

ADꢀ29±YRMZ1±±

ADꢀ29±YRMZ1±±-RLꢃ

1±±

MSOP-1±

RM-1±

D4V

ADꢀ29±EVAL

Evaluation Board

NOTES:

1. Z in Model Number denotes Lead Free Package

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C systemꢂ provided that the system conforms to the I²C Standard Specification as defined by Philips.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitryꢂ permanent damage may occur on devices subjected to high energy

electrostatic discharges. Thereforeꢂ proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. Pr C | Page 11 of 11

AD5290YRMZ50-RL7 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E