AD1938YSTZRL [ADI]
4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC; 4 ADC / DAC 8与PLL ， 192千赫， 24位编解码器
| 型号： | AD1938YSTZRL |
| 厂家： | 
ADI |
| 描述： | 4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC |
| 文件： | 总32页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 ADC/8 DAC with PLL,
192 kHz, 24-Bit CODEC
AD1938
FEATURES
GENERAL DESCRIPTION
PLL generated or direct master clock
Low EMI design
108 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Single-ended DAC output
Log volume control with autoramp function
SPI® controllable for flexibility
Software controllable clickless mute
Software power-down
Right justified, left justified, I2S and TDM modes
Master and slave modes up to 16-channel in/out
48-lead LQFP package
The AD1938 is a high performance, single-chip codec that
provides four analog-to-digital converters (ADCs) with
differential input and eight digital-to-analog converters
(DACs) with single-ended output using the Analog Devices,
Inc. patented multibit sigma-delta (Σ-Δ) architecture. An SPI
port is included, allowing a microcontroller to adjust volume
and many other parameters. The AD1938 operates from 3.3 V
digital and analog supplies. The AD1938 is available in a
48-lead (single-ended output) LQFP package. Other members
of this family include a differential DAC output and I2C® control
port version.
The AD1938 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1938 eliminates the
need for a separate high frequency master clock and can also be
used with a suppressed bit clock. The digital-to-analog and
analog-to-digital converters are designed using the latest ADI
continuous time architectures to further minimize EMI. By
using 3.3 V supplies, power consumption is minimized, further
reducing emissions.
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1938
SERIAL DATA PORT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
SDATA
OUT
SDATA
IN
ADC
ADC
ADC
ADC
DIGITAL
FILTER
AND
VOLUME
CONTROL
ANALOG
AUDIO
INPUTS
CLOCKS
ANALOG
AUDIO
OUTPUTS
DIGITAL
FILTER
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
CONTROL PORT
2
PRECISION
VOLTAGE
REFERENCE
SPI/I C
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD1938
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog-to-Digital Converters (ADCs).................................... 13
Digital-to-Analog Converters (DACs).................................... 13
Clock Signals............................................................................... 13
Reset and Power-Down ............................................................. 14
Serial Control Port ..................................................................... 14
Power Supply and Voltage Reference....................................... 15
Serial Data Ports—Data Format............................................... 15
Time-Division Multiplexed (TDM) Modes............................ 15
Daisy-Chain Mode..................................................................... 19
Control Registers............................................................................ 24
Definitions................................................................................... 24
PLL and Clock Control Registers............................................. 24
DAC Control Registers.............................................................. 25
ADC Control Registers.............................................................. 27
Additional Modes....................................................................... 29
Application Circuits ....................................................................... 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Test Conditions............................................................................. 3
Analog Performance Specifications........................................... 3
Crystal Oscillator Specifications................................................. 4
Digital Input/Output Specifications........................................... 5
Power Supply Specifications........................................................ 5
Digital Filters................................................................................. 6
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 13
REVISION HISTORY
5/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD1938
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply voltages (AVDD, DVDD)
Temperature range1
Master clock
3.3 V
As specified in Table 1 and Table 2
12.288 MHz (48 kHz fS, 256 × fS mode)
Input sample rate
48 kHz
Measurement bandwidth
Word width
20 Hz to 20 kHz
24 bits
Load capacitance (digital output)
Load current (digital output)
Input voltage HI
20 pF
1 mA or 1.5 kꢀ to ½ DVDD supply
2.0 V
0.8 V
Input voltage LO
1 Functionally guaranteed at −40°C to +125°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
All ADCs
24
Bits
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
98
100
102
105
−96
dB
dB
dB
%
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Gain Error
−1 dBFS
−87
+10
−10
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
−0.25
−10
+0.25
+10
dB
0
mV
ppm/°C
dB
dB
dB
100
−110
55
100 mV rms, 1 kHz
100 mV rms, 20 kHz
55
Input Resistance
Input Capacitance
14
10
kꢀ
pF
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
1.5
V
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
98
100
104
106
108
dB
dB
dB
With A-Weighted Filter (RMS)
With A-Weighted Filter (Avg)
Total Harmonic Distortion + Noise
Single-Ended Version
Single-Ended Version
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
0 dBFS
Two channels running
Eight channels running
−92
−86
0.88 (2.48)
dB
dB
−75
V rms (V p-p)
%
dB
mV
ppm/°C
dB
−10
−0.2
−16
−30
+10
+0.2
+16
+30
−4
Interchannel Isolation
100
Rev. 0 | Page 3 of 32
AD1938
Parameter
Conditions
Min
Typ
0
0.375
95
Max
0.6
Unit
Degrees
dB
dB
dB
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
100
ꢀ
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
FILTR pin
FILTR pin
CM pin
1.50
1.50
1.50
V
V
V
1.32
1.68
Specifications measured at 130°C (case).
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
All ADCs
24
Bits
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
95
97
102
105
−96
dB
dB
dB
%
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Gain Error
−1 dBFS
−87
+10
−10
Interchannel Gain Mismatch
Offset Error
−0.25
−10
+0.25
+10
dB
mV
0
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
98
100
104
106
108
dB
dB
dB
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Single-Ended Version
Single-Ended Version
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
0 dBFS
Two channels running
Eight channels running
−92
−86
0.8775 (2.482)
dB
dB
−70
V rms (V p-p)
%
dB
mV
−10
−0.2
−16
−30
+10
+0.2
16
−4
30
ppm/°C
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
FILTR pin
FILTR pin
CM pin
1.50
1.50
1.50
V
V
V
1.32
1.68
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
TRANSCONDUCTANCE
3.5
mmhos
Rev. 0 | Page 4 of 32
AD1938
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V 10ꢀ.
Table 4.
Parameter
Conditions/Comments
Min
2.0
2.2
Typ
Max
Unit
V
V
Input Voltage HI (VIH)
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage
MCLK_I pin
0.8
10
10
V
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
IOH = 1 mA
μA
μA
V
V
pF
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
DVDD − 0.60
IOL = 1 mA
0.4
5
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Conditions/Comments
Min
Typ
Max
Unit
DVDD
AVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Digital Current
Normal Operation
MCLK = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
56
65
95
2.0
mA
mA
mA
mA
Power-Down
Analog Current
Normal Operation
Power-Down
74
23
mA
mA
DISSIPATION
Operation
MCLK = 256 fS, 48 kHz
All Supplies
Digital Supply
Analog Supply
429
185
244
83
mW
mW
mW
mW
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
50
50
dB
dB
Rev. 0 | Page 5 of 32
AD1938
DIGITAL FILTERS
Table 6.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
All modes, typ @ 48 kHz
0.4375 fS
21
0.015
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
0.5 fS
0.5625 fS
24
27
kHz
kHz
dB
79
35
22.9844/fS
479
22
μs
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
0.4535 fS
0.3646 fS
0.3646 fS
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
70
Pass-Band Ripple
Transition Band
Stop Band
0.01
0.05
0.1
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
24
48
96
26
61
122
Stop-Band Attenuation
Group Delay
70
70
70
dB
dB
μs
μs
25/fS
11/fS
8/fS
521
115
42
μs
TIMING SPECIFICATIONS
−40°C < TA < +130°C, DVDD = 3.3 V 10ꢀ.
Table 7.
Parameter
Condition
Comments
Min
Max Unit
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH
MCLK duty cycle
MCLK frequency
DAC/ADC clock source = PLL clock @ 256 fS, 384 fS,
512 fS, 768 fS
DAC/ADC clock source = direct MCLK @ 512 fS (bypass
on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
40
6.9
60
60
%
%
tMH
fMCLK
fMCLK
tPDR
13.8 MHz
27.6 MHz
ns
RST low
15
tPDRR
RST recovery
Reset to active output
4096
tMCLK
PLL
Lock time
MCLK and LRCLK
input
10
60
ms
%
256 fS VCO Clock
Output Duty Cycle
MCLK_O pin
40
Rev. 0 | Page 6 of 32
AD1938
Parameter
Condition
Comments
Min
Max Unit
SPI PORT
See Figure 11
tCCH
tCCL
CCLK high
CCLK low
35
35
ns
ns
fCCLK
tCDS
tCDH
tCLS
CCLK frequency
CDATA setup
CDATA hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
10
MHz
ns
ns
To CCLK rising
From CCLK rising
To CCLK rising
10
10
10
10
10
ns
tCLH
From CCLK falling
ns
tCLH
ns
tCOE
tCOD
tCOH
From CCLK falling
From CCLK falling
From CCLK falling
30
30
ns
ns
ns
30
tCOTS
COUT tri-state
From CCLK falling
30
ns
DAC SERIAL PORT
See Figure 24
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
DBCLK high
DBCLK low
Slave mode
Slave mode
10
10
10
5
−8
10
5
ns
ns
ns
ns
ns
ns
ns
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
To DBCLK rising, slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
+8
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tABDD
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
10
10
10
5
ns
ns
ns
ns
ns
ns
−8
+8
18
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
10
5
ns
ns
ns
ns
ns
ns
ns
18
10
10
10
5
AUXLRCLK setup
AUXLRCLK hold
To AUXBCLK rising
From AUXBCLK rising
tDLH
Rev. 0 | Page 7 of 32
AD1938
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Rating
THERMAL RESISTANCE
Analog (AVDD)
Digital (DVDD)
−0.3 V to +3.6 V
−0.3 to +3.6 V
20 mA
–0.3 V to AVDD + 0.3 V
−0.3 to DVDD + 0.3 V
θJA represents thermal resistance, junction-to-ambient; θJC
represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Table 9. Thermal Resistance
Package Type
θJA
θJC
Unit
48-Lead LQFP
50.1
17
°C/W
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 32
AD1938
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AGND
MCLKI/XI
MCLKO/XO
AGND
AGND
FILTR
AGND
AVDD
3
4
5
AVDD
AGND
OR2
AD1938
6
OL3
TOP VIEW
(Not to Scale)
7
OR3
OL2
SINGLE-ENDED
OUTPUT
8
OL4
OR1
9
OR4
OL1
10
11
12
PD/RST
DSDATA4
DGND
CLATCH/ADR1
CCLK/SCL
DGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pin Configuration, 48-Lead LQFP
Table 10. 48-Lead LQFP Package for AD1938
Pin No. In/Out Mnemonic Description
Analog Ground.
1
I
AGND
2
3
4
I
O
I
MCLKI/XI
MCLKO/XO
AGND
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
5
6
7
8
I
AVDD
OL3
OR3
OL4
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
DAC 3 Right Output.
DAC 4 Left Output.
DAC 4 Right Output.
O
O
O
O
I
9
OR4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD/RST
DSDATA4
DGND
Power-Down Reset (Active Low).
I/O
I
I
DAC Input 4 (Input to DAC 4 L and R)/DAC TDM Data Out 2/AUX ADC 1 Data In.
Digital Ground.
DVDD
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC 3 L and R)/DAC TDM Data In 2/Aux DAC 2 Data Output.
DAC Input 2 (Input to DAC 2 L and R)/DAC TDM Data Out/AUX ADC 1 Data In.
DAC Input 1 (Input to DAC 1 L and R)/DAC TDM Data In/AUX ADC 2 Data In.
Bit Clock for DACs.
I/O
I/O
I
I/O
I/O
I/O
O
I/O
I/O
I
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN/ADR0
COUT/SDA
DGND
CCLK/SCL
CLATCH/ADR1
OL1
LR Clock for DACs.
ADC Serial Data Output 2 (ADC 2 L and R)/ADC TDM Data Input/Aux DAC 1 Data Output.
ADC Serial Data Output 1 (ADC 1 L and R)/ADC TDM Data Output.
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
O
I
I
I
O
DAC 1 Left Output.
Rev. 0 | Page 9 of 32
AD1938
Pin No. In/Out Mnemonic
Description
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
O
O
I
I
I
O
I
I
O
I
I
I
I
I
I
I
I
O
I
OR1
OL2
OR2
DAC 1 Right Output.
DAC 2 Left Output.
DAC 2 Right Output.
Analog Ground.
AGND
AVDD
AGND
FILTR
AGND
AVDD
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
AVDD
Rev. 0 | Page 10 of 32
AD1938
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0
0.08
0.06
0.04
0.02
0
–50
–0.02
–0.04
–0.06
–0.08
–0.10
–100
–150
0
12
24
36
48
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 3. ADC Pass-Band Filter Response, 48 kHz
Figure 6. DAC Stop-Band Filter Response, 48 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.10
0.05
0
–0.05
–0.10
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (Hz)
0
24
48
72
96
FREQUENCY (kHz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
Figure 7. DAC Pass-Band Filter Response, 96 kHz
0.06
0.04
0.02
0
0
–50
–0.02
–0.04
–0.06
–100
–150
0
24
48
72
96
0
8
16
FREQUENCY (kHz)
24
FREQUENCY (kHz)
Figure 5. DAC Pass-Band Filter Response, 48 kHz
Figure 8. DAC Stop-Band Filter Response, 96 kHz
Rev. 0 | Page 11 of 32
AD1938
0.5
0.4
0
–2
0.3
0.2
0.1
–4
0
–0.1
–0.2
–0.3
–0.4
–6
–8
–10
48
–0.5
0
64
80
96
8
16
32
64
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 10. DAC Stop-Band Filter Response, 192 kHz
Figure 9. DAC Pass-Band Filter Response, 192 kHz
Rev. 0 | Page 12 of 32
AD1938
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
high frequency noise and tones to fold down into the audio
band; therefore, exercise care in selecting these components.
There are four analog-to-digital converter (ADC) channels in
the AD1938 configured as two stereo pairs with differential
inputs. The ADCs can operate at a nominal sample rate of
48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board
digital antialiasing filters with 79 dB stop-band attenuation and
linear phase response, operating at an oversampling ratio of 128
(48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each
stereo pair) and a common frame (ALRCLK) and bit (ABCLK)
clock. Alternatively, one of the TDM modes can be used to
access up to 16 channels on a single TDM data line.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI pin. The default at power-up is
256 × fS from MCLKI. In 96 kHz mode, the master clock fre-
quency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD193x family is programmed in 256 × fS mode, the
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD193x is then switched to 96 kHz operation (by writing
to the SPI or I2C port), the frequency of the master clock should
remain at 12.288 MHz, which is now 128 × fS. In 192 kHz mode,
this becomes 64 × fS.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to inter-
nal switched capacitors. To isolate the external driving op amp
from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for example, ceramic NPO or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs if
selected in PLL and Clock Control Register 1.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a
1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The
cutoff frequency scales directly with sample frequency.
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The PLL can be powered down in PLL and Clock Control
Register 0. To ensure reliable locking when changing PLL
modes, or if the reference clock is unstable at power-on, power
down the PLL and then power it back up when the reference
clock has stabilized.
The AD1938 digital-to-analog converter (DAC) channels are
arranged as single-ended, four stereo pairs giving eight analog
outputs for minimum external components. The DACs include
on-board digital reconstruction filters with 70 dB stop band
attenuation and linear phase response, operating at an oversam-
pling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode).
Each channel has its own independently programmable
attenuator, adjustable in 255 steps in increments of 0.375 dB.
Digital inputs are supplied through four serial data input pins
(one for each stereo pair) and a common frame (DLRCLK) and
bit (DBCLK) clock. Alternatively, one of the TDM modes can
be used to access up to 16 channels on a single TDM data line.
The internal master clock (MCLK) can be disabled in PLL and
Clock Control Register 0 to reduce power dissipation when the
AD1938 is idle. The clock should be stable before it is enabled.
Unless a standalone mode is selected (see the Serial Control
Port section), the clock is disabled by reset and must be enabled
by writing to the SPI or I2C port for normal operation.
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms TIE (time interval error). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
Each output pin has a nominal common-mode dc level of 1.5 V
and swings 1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins. The
use of op amps with low slew rate or low bandwidth can cause
Rev. 0 | Page 13 of 32
AD1938
especially important that the clock signal should not be passed
through an FPGA, CPLD, or other large digital chip (such as a
DSP) before being applied to the AD1938. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
SERIAL CONTROL PORT
The AD1938 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal MCLK enable is set to 1 and ADC
BCLK and LRCLK master/slave is set by COUT/SDA. Refer to
Table 11 for details. It is recommended to use a weak pull-up
RESET AND POWER-DOWN
Reset sets all the control registers to their default settings. To
avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires lock condition,
an initialization routine runs inside the AD1938. This initializa-
tion lasts for approximately 256 MCLKs.
CLATCH
resistor on
in applications that have a microcontroller.
This pull-up resistor ensures that the AD1938 recognizes the
presence of a microcontroller.
The SPI control port of the AD1938 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. The
reset pin should be pulled low by an external resistor to
guarantee proper startup.
W
AD1938 the address is 0x04, shifted left 1 bit due to the R/
bit. The second byte is the AD1938 register address and the
third byte is the data.
Table 11. Stand Alone Mode Selection
CLATCH/ADR1
ADC Clocks
Slave
Master
CIN/ADR0
COUT/SDA
CCLK/SCL
0
0
0
1
0
0
0
0
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
tCOTS
CCLK
tCDS tCDH
CIN
D23
D22
D9
D8
D8
D0
D0
tCOE
COUT
D9
tCOD
Figure 11. Format of SPI Signal
Rev. 0 | Page 14 of 32
AD1938
to become the bus masters according to DAC Control Register 1
and ADC Control Register 2. By default, both ADC and DAC
serial ports are in the slave mode.
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1938 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 μF
should also be provided on the same PC board as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with
each supply. It is important that the analog supply be as clean as
possible.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1938 serial ports also have several different TDM serial
data modes. The first and most commonly used configurations
are shown in Figure 12 and Figure 13. In Figure 12, the ADC
serial port outputs one data stream consisting of four on-chip
ADCs followed by four unused slots. In Figure 13, the eight
on-chip DAC data slots are packed into one TDM stream. In
this mode, both DBCLK and ABCLK are 256 fS.
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and Aux Modes, see Table 12.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The AD1938 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 14. In this mode,
the AUX channels are the last four slots of the TDM data stream.
These slots are extracted and output to the AUX serial port. It
should be noted that due to the high DBCLK frequency, this mode
is available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
The ADC and DAC internal voltage reference (VREF) is
brought out on FILTR and should be bypassed as close as
possible to the chip, with a parallel combination of 10 μF and
100 nF. Any external current drawn should be limited to less
than 50 μA.
The internal reference can be disabled in PLL and Clock
Control Register 1 and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. The total gain
from ADC input to DAC output remains constant.
The AD1938 also allows system configurations with more than
four ADC channels as shown in Figure 15 and Figure 16 that
show using 8 ADCs and 16 ADCs, respectively. Again, due to
the high ABCLK frequency, this mode is available only in the
48 kHz/44.1 kHz/32 kHz sample rate.
Combining the AUX ADC and DAC modes results in a system
configuration of 8 ADCs and 12 DACs. The system, then, con-
sists of two external stereo ADCs, two external stereo DACs,
and one AD1938. This mode is shown in Figure 17 (combined
AUX ADC and DAC modes).
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
LRCLK
256 BCLKs
BCLK
SERIAL DATA PORTS—DATA FORMAT
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 23.
SLOT 5 SLOT 6 SLOT 7 SLOT 8
DATA
LEFT 1 RIGHT 1 LEFT 2 RIGHT 2
LRCLK
BCLK
MSB
MSB–1
MSB–2
DATA
Figure 12. ADC TDM (8-Channel I2S Mode)
LRCLK
BCLK
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left-justified, right-justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to DAC Control Register 0. The
polarity of the DBCLK and DLRCLK is programmable according
to DAC Control Register 1. The ADC serial formats and serial
clock polarity are programmable according to ADC Control
Register 1. Both DAC and ADC serial ports are programmable
256 BCLKs
32 BCLK
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 RIGHT 1 LEFT 2 RIGHT 2 LEFT 3 RIGHT 3 LEFT 4 RIGHT 4
DATA
LRCLK
BCLK
MSB
MSB–1
MSB–2
DATA
Figure 13. DAC TDM (8-Channel I2S Mode)
Rev. 0 | Page 15 of 32
AD1938
Table 12. Pin Function Changes in TDM and AUX Modes
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
TDM Modes
AUX Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/Out
ADC TDM BCLK In/Out
DAC TDM Frame Sync In/Out
DAC TDM BCLK In/Out
TDM Data Out
AUX Data Out 1 (to Ext. DAC 1)
TDM Data In
AUX Data In 1 (from Ext. ADC 1)
AUX Data In 2 (from Ext. ADC 2)
AUX Data Out 2 (to Ext. DAC 2)
TDM Frame Sync In/Out
TDM BCLK In/Out
DAC4 Data In
ADC LRCLK In/Out
ADC BCLK In/Out
DAC LRCLK In/Out
DAC BCLK In/Out
ABCLK
DLRCLK
DBCLK
AUX LRCLK In/Out
AUX BCLK In/Out
ALRCLK
ABCLK
AUXILIARY DAC CHANNELS
WILL APPEAR AT
AUX DAC PORTS
UNUSED SLOTS
8-ON-CHIP DAC CHANNELS
DSDATA1
(TDM_IN)
EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
ASDATA2
MSB
MSB
MSB
(AUX1_OUT)
DSDATA4
(AUX2_OUT)
MSB
Figure 14. 16-Channel AUX DAC Mode
Rev. 0 | Page 16 of 32
AD1938
ALRCLK
ABCLK
8-ON-CHIP DAC CHANNELS
DSDATA1
(TDM_IN)
DAC L1
ADC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
AUX R2
4-ON-CHIP ADC CHANNELS
ADC R1 ADC L2
4-AUX ADC CHANNELS
AUX R1 AUX L2
ASDATA1
(TDM_OUT)
ADC R2
AUX L1
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
DSDATA2
(AUX1_IN)
MSB
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
Figure 15. 8-Channel AUX ADC Mode
ALRCLK
ABCLK
4-ON-CHIP ADC CHANNELS
AUXILIARY ADC CHANNELS
UNUSED SLOTS
ASDATA1
(TDM_OUT)
ADC L1 ADC R1 ADC L2 ADC R2 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
DSDATA2
(AUX1_IN)
MSB
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
Figure 16. 16-Channel AUX ADC Mode
Rev. 0 | Page 17 of 32
AD1938
ALRCLK
ABCLK
AUXILIARY DAC CHANNELS
WILL APPEAR AT
UNUSED SLOTS
8-ON-CHIP DAC CHANNELS
AUX DAC PORTS
DSDATA1
(TDM_IN)
EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2
4-ON-CHIP ADC CHANNELS
AUXILIARY ADC CHANNELS
UNUSED SLOTS
ASDATA1
(TDM_OUT)
ADC L1 ADC R1 ADC L2 ADC R2 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
DLRCLK
(AUX PORT)
LEFT
RIGHT
DBCLK
(AUX PORT)
DSDATA2
(AUX1_IN)
MSB
MSB
MSB
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
MSB
ASDATA2
(AUX1_OUT)
DSDATA4
(AUX2_OUT)
Figure 17. Combined AUX DAC and ADC Mode
Rev. 0 | Page 18 of 32
AD1938
There are two configurations for the ADC port to work in
DAISY-CHAIN MODE
daisy-chain mode. The first one is with an ABCLK at 256 fS
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1938 must be grounded in
all modes of operation.
The AD1938 also allows a daisy-chain configuration to expand
the system to 8 ADCs and 16 DACs (see Figure 18). In this
mode, the DBCLK frequency is 512 fS. The first eight slots of the
DAC TDM data stream belong to the first AD1938 in the chain
and the last eight slots belong to the second AD1938. The second
AD1938 is the device attached to the DSP TDM port.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 26 for a typical AD1938
configuration with two external stereo DACs and two external
stereo ADCs.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1938 can be configured into a dual-line, TDM mode as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1938 in the chain and the last four channels belong to
the second AD1938.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1938 as shown in Figure 20.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1 (TDM_IN)
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
OF THE SECOND AD193x
DSDATA2 (TDM_OUT)
OF THE SECOND AD193x
THIS IS THE TDM
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
TO THE FIRST AD193x
8 UNUSED SLOTS
32 BITS
FIRST
AD193x
SECOND
AD193x
DSP
MSB
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1938 Daisy Chain)
Rev. 0 | Page 19 of 32
AD1938
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DSDATA1
(IN)
DAC L1
DAC R1
DAC L2
DAC R2
DAC L1
DAC L1
DAC L3
DAC L3
DAC R1
DAC R1
DAC R3
DAC R3
DAC L2
DAC L2
DAC L4
DAC L4
DAC R2
DAC R2
DAC R4
DAC R4
DSDATA2
(OUT)
DSDATA3
(IN)
DAC L3
DAC R3
DAC L4
DAC R4
DSDATA4
(OUT)
32 BITS
MSB
FIRST
AD193x
SECOND
AD193x
DSP
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1938 Daisy Chain); DSDATA3 and DSDATA4 are the Daisy Chain
DLRCLK
DBCLK
DSDATA1
DSDATA2
DAC L1
DAC L3
DAC R1
DAC R3
DAC L2
DAC L4
DAC R2
DAC R4
32 BITS
MSB
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
4 ADC CHANNELS OF SECOND IC IN THE CHAIN
4 ADC CHANNELS OF FIRST IC IN THE CHAIN
ADC L1 ADC R1 ADC L2 ADC R2
ASDATA1 (TDM_OUT
OF THE SECOND AD193x
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
ASDATA2 (TDM_IN
OF THE SECOND AD193x
IN THE CHAIN)
ADC L1
ADC R1
ADC L2
ADC R2
32 BITS
FIRST
AD193x
SECOND
AD193x
DSP
MSB
Figure 21. ADC TDM Daisy-Chain Mode (256 fS BCLK, Two AD193x Daisy Chain)
Rev. 0 | Page 20 of 32
AD1938
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND AD193x
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2
ASDATA2 (TDM_IN
OF THE SECOND AD193x
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2
32 BITS
FIRST
AD193x
SECOND
DSP
AD193x
MSB
Figure 22. ADC TDM Daisy-Chain Mode (512 fS BCLK, Two AD193x Daisy Chain)
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
MSB
I S MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
SDATA
MSB
LSB
2
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 × fS
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 23. Stereo Serial Modes
Rev. 0 | Page 21 of 32
AD1938
tDBH
tDBP
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
MSB–1
tDDH
tDDS
MSB
DSDATA
I C-JUSTIFIED
2
MODE
tDDH
tDDS
MSB
tDDS
LSB
tDDH
DSDATA
RIGHT-JUSTIFIED
MODE
tDDH
Figure 24. DAC Serial Timing
tABH
tABP
ABCLK
tABL
tALS
tALH
ALRCLK
tABDD
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB–1
MSB
tABDD
ASDATA
I C-JUSTIFIED
2
MODE
tABDD
ASDATA
RIGHT-JUSTIFIED
MODE
MSB
LSB
Figure 25. ADC Serial Timing
Rev. 0 | Page 22 of 32
AD1938
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Mnemonic
ASDATA1
ASDATA2
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
Stereo Modes
ADC1 Data Out
ADC2 Data Out
DAC1 Data In
DAC2 Data In
DAC3 Data In
TDM Modes
AUX Modes
ADC TDM Data Out
ADC TDM Data In
DAC TDM Data In
DAC TDM Data Out
DAC TDM Data In 2 (Dual-Line Mode)
DAC TDM Data Out 2 (Dual-Line Mode)
ADC TDM Frame Sync In/Out
ADC TDM BCLK In/Out
DAC TDM Frame Sync In/Out
DAC TDM BCLK In/Out
TDM Data Out
AUX Data Out 1 (to Ext. DAC 1)
TDM Data In
AUX Data In 1 (from Ext. ADC 1)
AUX Data In 2 (from Ext. ADC 2)
AUX Data Out 2 (to Ext. DAC 2)
TDM Frame Sync In/Out
TDM BCLK In/Out
DAC4 Data In
ADC LRCLK In/Out
ADC BCLK In/Out
DAC LRCLK In/Out
DAC BCLK In/Out
ABCLK
DLRCLK
DBCLK
AUX LRCLK In/Out
AUX BCLK In/Out
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
SHARC
12.288MHz
LRCLK
BCLK
LRCLK
BCLK
AUX
ADC 1
AUX
ADC 1
DATA
MCLK
DATA
MCLK
ASDATA1 ALRCLK ABCLK DSDATA1
DBCLK
DLRCLK
AD1938
LRCLK
BCLK
LRCLK
BCLK
ASDATA2
DSDATA4
DSDATA2
DSDATA3
MCLK
TDM MASTER
AUX MASTER
AUX
ADC 2
AUX
DATA ADC 2
DATA
MCLK
MCLK
Figure 26. Example of AUX Mode Connection to SHARC (AD1938 as TDM Master/AUX Master Shown)
Rev. 0 | Page 23 of 32
AD1938
CONTROL REGISTERS
DEFINITIONS
2
W
The format is the same for I C and SPI ports. The global address for the AD1938 is 0x04, shifted left 1 bit due to the R/ bit. However, in
I2C, ADR0 and ADR1 are OR’ed into Bit 17 and Bit 8 to provide multiple chip addressing. All registers are reset to 0, except for the DAC
volume registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
Bit
Table 15. Register Addresses and Functions
Address
Function
0
1
2
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
3
DAC Control 1
4
DAC Control 2
5
6
7
8
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
ADC Control 0
9
10
11
12
13
14
15
16
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit
Value
Function
Description
0
0
1
Normal operation
Power-down
PLL power-down
2:1
4:3
6:5
7
00
01
10
11
00
01
10
11
00
01
10
11
0
INPUT 256 (×44.1 kHz or 48 kHz)
INPUT 384 (×44.1 kHz or 48 kHz)
INPUT 512 (×44.1 kHz or 48 kHz)
INPUT 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLK pin functionality (PLL active)
MCLK_O pin
MCLK
DLRCLK
ALRCLK
Reserved
PLL input
Disable: ADC and DAC idle
Enable: ADC and DAC active
Internal MCLK enable
1
Rev. 0 | Page 24 of 32
AD1938
Table 17. PLL and Clock Control 1
Bit
Value
Function
PLL clock
MCLK
Description
0
0
1
DAC clock source select
1
0
1
PLL clock
MCLK
ADC clock source select
2
0
1
Enabled
Disabled
Not locked
Locked
On-chip voltage reference
PLL lock indicator (read only)
3
0
1
7:4
0000
Reserved
DAC CONTROL REGISTERS
Table 18. DAC Control 0
Bit
Value
Function
Description
0
0
Normal
Power-down
1
Power-down
2:1
5:3
00
01
10
11
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Sample rate
000
001
010
011
100
101
110
111
00
1
0
8
12
16
Reserved
Reserved
Reserved
SDATA delay (BCLK periods)
7:6
Stereo (normal)
Serial format
01
10
11
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Table 19. DAC Control 1
Bit
Value
Function
Description
0
0
1
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
BCLK active edge (TDM in)
2:1
00
01
10
11
0
BCLKs per frame
3
4
5
6
7
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
1
Left high
0
1
Slave
Master
0
1
Slave
Master
0
1
DBCLK pin
Internally generated
Normal
0
BCLK polarity
1
Inverted
Rev. 0 | Page 25 of 32
AD1938
Table 20. DAC Control 2
Bit
Value
Function
Unmute
Mute
Description
0
0
1
Master Mute
2:1
4:3
00
01
10
11
00
01
10
11
0
Flat
Deemphasis (32 kHz/44.1 kHz/48 kHz mode only)
48 kHz curve
44.1 kHz curve
32 kHz curve
24
20
Reserved
16
Word width
5
Noninverted
Inverted
Reserved
DAC output polarity
1
7:6
00
Table 21. DAC Individual Channel Mutes
Bit
Value
Function
Unmute
Mute
Description
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC 1 left mute
1
2
3
4
5
6
7
Unmute
Mute
DAC 1 right mute
DAC 2 left mute
DAC 2 right mute
DAC 3 left mute
DAC 3 right mute
DAC 4 left mute
DAC 4 right mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Table 22. DAC Volume Controls
Bit
Value
Function
Description
7:0
0
No attenuation
DAC volume control
1 to 254 −3/8 dB per step
255 Full attenuation
Rev. 0 | Page 26 of 32
AD1938
ADC CONTROL REGISTERS
Table 23. ADC Control 0
Bit
Value
Function
Description
0
0
Normal
Power-down
1
Power down
1
0
1
Off
On
High-pass filter
ADC 1L mute
2
0
Unmute
1
Mute
3
0
1
Unmute
Mute
ADC 1R mute
ADC 2L mute
4
0
Unmute
1
Mute
5
0
1
Unmute
Mute
ADC 2R mute
Output sample rate
7:6
00
01
10
11
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Table 24. ADC Control 1
Bit
Value
Function
Description
1:0
00
24
Word width
01
20
10
Reserved
11
16
4:2
000
001
010
011
100
101
110
111
00
1
0
8
12
16
Reserved
Reserved
Reserved
SDATA delay (BCLK periods)
6:5
7
Stereo
Serial format
01
10
11
TDM (daisy chain)
ADC Aux mode (ADC-, DAC, TDM-coupled)
Reserved
0
1
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
BCLK active edge (TDM in)
Rev. 0 | Page 27 of 32
AD1938
Table 25. ADC Control 2
Bit
Value
Function
Description
0
0
50/50 (allows 32-/24-/20-/16-BCLK/channel)
LRCLK format
1
Pulse (32-BCLK/channel)
1
0
Drive out on falling edge (DEF)
BCLK polarity
1
Drive out on rising edge
2
0
1
Left low
Left high
Slave
Master
64
128
256
512
LRCLK polarity
LRCLK master/slave
BCLKs per frame
3
0
1
5:4
00
01
10
11
0
6
7
Slave
BCLK master/slave
BCLK source
1
Master
ABCLK pin
Internally generated
0
1
Rev. 0 | Page 28 of 32
AD1938
To relax the requirement for the setup time of the AD1938 in
ADDITIONAL MODES
cases of high speed TDM data transmission, the AD1938 can
latch in the data using the falling of DBCLK. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 28 shows this pipeline mode of data
transmission.
The AD1938 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This
configuration is applicable when the AD1938 master clock is
generated by the PLL with the DLRCLK as the PLL reference
frequency.
Both the BLCK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATA
DLRCLK
INTERNAL
DBCLK
TDM-DSDATA
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK. This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
DSDATA
Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM Useful for High Frequency TDM Transmission
This Model Is Also Available in the ADC Serial Data Port.)
Rev. 0 | Page 29 of 32
AD1938
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended
loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in
Figure 31 and Figure 32 for the noninverting and inverting cases.
120pF
600Z
5.76kΩ
5.76kΩ
AUDIO
INPUT
2
3
240pF
NPO
–
100pF
1
OP275
+
3
2
+
DAC OUT
4.7µF
+
604Ω
1
AUDIO
4.75kΩ 4.75kΩ
OP275
–
OUTPUT
4.7µF
+
5.76kΩ
237Ω
3.3nF
NPO
ADCxN
4.99kΩ
49.9kΩ
1nF
120pF
NPO
270pF
NPO
4.99kΩ
100pF
5.76kΩ
1nF
6
5
NPO
237Ω
–
4.7µF
+
7
OP275
+
ADCxP
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
Figure 29. Typical ADC Input Filter Circuit
LRCLK
39nF
MCLK
5.6nF
LF
LF
68pF
11kΩ
NPO
+
2
3
DAC
OUT
2.2nF
390nF
–
4.7µF
+
2.2nF
NPO
604Ω
1
AUDIO
OUTPUT
11kΩ
3.01kΩ
CM
OP275
+
3.32kΩ
562Ω
49.9kΩ
AVDD2
AVDD2
270pF
NPO
0.1µF
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
Figure 30. Recommended Loop Filters for LRCLK and MCLK PLL Reference
Rev. 0 | Page 30 of 32
AD1938
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 33. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1938YSTZ1, 2
AD1938YSTZRL1, 2
EVAL-AD1938EB
Temperature Range
Package Description
48-Lead LQFP
48-Lead LQFP, 13”Reel
Evaluation Board
Package Option
–40°C to +105°C
–40°C to +105°C
ST-48
ST-48
1 Z = Pb-free part.
2 Single-ended output; SPI control port.
Rev. 0 | Page 31 of 32
AD1938
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05582-0-5/06(0)
Rev. 0 | Page 32 of 32
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