AD1940 [ADI]
SigmaDSP-TM Multichannel 28-Bit Audio Processor; 的SigmaDSP -TM多通道28位音频处理器型号: | AD1940 |
厂家: | ADI |
描述: | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
文件: | 总57页 (文件大小:4227K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
4
AD1940
VOLTAGE
REGULATOR
28 28
2
DSP CORE
2
2
SERIAL DATA/
TDM INPUTS
DATA FORMAT:
SERIAL
DATA/
TDM
5.23 (SINGLE
PRECISION)
MASTER
CLOCK
INPUT
PLL
OUTPUTS
10.46 (DOUBLE
PRECISION)
SERIAL
CONTROL
INTERFACE
4
SPI I/O
RAM
ROM
tLIH
tBIH
BCLK_IN
tBIL
tLIS
LRCLK_IN
tSIS
SDATA_INX
LEFT-JUSTIFIED
MODE
MSB
MSB-1
tSIH
tSIS
SDATA_INX
2
I S-JUSTIFIED
MSB
tSIH
MODE
tSIS
tSIS
SDATA_INX
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tLCH
tBIH
tTS
BCLK_OUTX
tBIL
tLOS
LRCLK_OUTX
tSDDS
tSDDM
SDATA_OUTX
LEFT-JUSTIFIED
MODE
MSB
MSB-1
tSDDS
tSDDM
SDATA_OUTX
I S-JUSTIFIED
2
MSB
MODE
tSDDS
tSDDM
SDATA_OUTX
RIGHT-JUSTIFIED
MODE
LSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
tCOD
tMP
MCLK
RESETB
tRLPW
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
VDD
MCLK
36
GND
PIN 1
INDICATOR
35
34
33
32
31
30
29
28
27
26
25
BCLK_OUT1
LRCLK_OUT1
ODVDD
RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
PLL_VDD
NC
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
SDATA_OUT0
ODVDD
AD1940
TOP VIEW
7
8
(Not to Scale)
9
10
11
LRCLK_IN
BCLK_IN
GND
BCLK_OUT0
LRCLK_OUT0
VDD
12
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
2
2
DATA MEMORY
6k 28
TARGET/SLEW
RAM
28 28
DSP CORE
64 28
2
2
SERIAL
DATA/TDM
INPUT
SERIAL DATA/
TDM OUTPUT
GROUP
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
GROUP
PLL MODE
SELECT
MCLK
PLL
MASTER
CLOCK
INPUT
CONTROL
REGISITER
PROGRAM
PARAMETER
RAM
COEFFICIENT
ROM
RAM
SERIAL
CONTROL
PORT
4
TRAP REG.
SPI I/O
GROUP
1536 40
1024 28
512 28
SAFELOAD
REGISTER
RESETB
4
REGULATOR
GROUP
MEMORY CONTROLLERS
VOLTAGE REGULATOR
4-BIT SIGN EXTENSION
DIGITAL
CLIPPER
SIGNAL PROCESSING
(5.23 FORMAT)
DATA IN
SERIAL PORT
1.23 5.23
5.23
1.23
CLATCH
CCLK
BYTE 0
BYTE 1
BYTE 2
BYTE 3
CDATA
CLATCH
CCLK
BYTE 1
BYTE 0
CDATA
COUT
HI-Z
HI-Z
DATA
DATA
DATA
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
10
20
30
TIME (ms)
1
0.8
0.6
1
0.8
0.6
0.4
0.2
0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1
–0.8
–1
0
5
10
15
20
25
30
35
0
10
20
30
TIME (ms)
TIME (ms)
1
0.8
0.6
1
0.8
0.6
0.4
0.2
0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1
–0.8
–1
0
10
20
30
0
10
20
30
TIME (ms)
TIME (ms)
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
LSB
MSB
SDATA
MSB
LSB
1 /F
S
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
1 /F
S
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
1 /F
MSB
LSB
S
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
LRCLK
BCLK
MSB TDM
MSB TDM
CH
0
SDATA
8TH
CH
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
32
BCLKs
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_IN3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
DVDD
FZT953
+
+
10 F
10 F
1k
100nF
1nF
100nF
AD1940
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
1
36
PIN 1
SEATING
PLANE
10°
6°
2°
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
VIEW A
7°
3.5
0°
25
°
12
13
24
0.15
0.05
SEATING
PLANE
0.27
0.22
0.17
0.08 MAX
COPLANARITY
0.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
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RDAC
V
DD
A
RDAC
EEPROM
V
RDAC
REGISTER
LOGIC
W
GND
B
DATA
CONTROL
8
8
SCL
SDA
2
I C
SERIAL
INTERFACE
AD0
AD1
COMMAND
DECODE LOGIC
AD5259
ADDRESS
DECODE LOGIC
POWER-
ON RESET
CONTROL LOGIC
V
V
DD
LOGIC
A
EEPROM
SCL
RDAC
REGISTER
AND
2
I
C
SDA
AD0
AD1
SERIAL
INTERFACE
LEVEL
SHIFTER
W
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
9
A
B
V
AD5259
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
t2
t8
t6
t9
SCL
SDA
t10
t4
t7
t5
t2
t3
t9
t8
t1
S
P
P
S
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
9
A
B
V
AD5259
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
1.5
1.3
0.25
0.20
0.15
0.10
0.05
0
2.7V
1.1
0.9
0.7
0.5
0.3
–0.05
–0.10
–0.15
–0.20
–0.25
0.1
–40 C
+25 C
–0.1
–0.3
–0.5
+85 C
5.5V
0
32
32
32
64
64
64
96
128
160
192
192
192
224
256
0
0
0
32
64
64
64
96
128
160
192
224
224
224
256
256
256
CODE (Decimal)
CODE (Decimal)
0.5
0.4
0.25
0.20
0.15
0.10
0.05
0
2.7V
0.3
0.2
2.7V
5.5V
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
–0.10
–0.15
–0.20
–0.25
5.5V
0
96
128
160
224
256
32
96
128
160
192
CODE (Decimal)
CODE (Decimal)
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
2.7V
5.5V
T
= +85 C
A
–0.05
–0.10
–0.15
–0.20
–0.25
–0.05
–0.10
–0.15
–0.20
–0.25
T
= +25 C
T
= –40 C
A
A
0
96
128
160
224
256
32
96
128
160
192
CODE (Decimal)
CODE (Decimal)
0.5
0.4
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.3
ZSE @ V = 2.7V
DD
0.2
0.1
+25 C
–40 C
0
ZSE @ V = 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
+85 C
160 192
–40
–20
0
20
40
60
80
0
32
64
96
128
224
256
TEMPERATURE ( C)
CODE (Decimal)
1
0.5
0.4
0.3
T
= –40 C
A
0.2
T
= +85 C
A
0.1
0
V
= 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
T
= +25 C
A
0.1
–40
–20
0
20
40
60
80
0
32
64
96
128
160
192
224
256
TEMPERATURE ( C)
CODE (Decimal)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
6
5
4
V
DD
= 5.5V
3
FSE @ V = 5.5V
DD
2
1
FSE @ V = 2.7V
DD
V
= 2.7V
DD
0
–1
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE ( C)
TEMPERATURE ( C)
400
300
100k
50k
120
100
80
60
40
20
0
100k Rt @ V = 5.5V
DD
200
10k
100
0
50k Rt @ V = 5.5V
DD
–100
–200
–300
–400
–500
–600
10k Rt @ V = 5.5V
DD
5k Rt @ V = 5.5V
DD
5k
–40
–20
0
20
40
60
80
0
32
64
96
128
160
192
224
256
TEMPERATURE ( C)
CODE (Decimal)
0
–6
70
60
80
H
40
H
50
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
H
40
10
H
30
10k
08
H
20
100k
04
H
10
02
H
0
01
H
–10
–20
–30
–40
5k
50k
1k
10k
100k
1M
10M
0
32
64
96
128
160
192
224
256
CODE (Decimal)
FREQUENCY (Hz)
0
–6
350
300
250
200
150
100
50
80
H
40
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
H
10
H
R
WB
@ V = 2.7V
DD
08
H
04
H
02
H
01
H
R
@ V = 5.5V
DD
WB
0
–40
1k
10k
100k
1M
10M
–20
0
20
40
60
80
FREQUENCY (Hz)
TEMPERATURE ( C)
0
–6
10k
1k
80
40
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20
10
08
H
H
H
V
= V
= 5V
LOGIC
DD
04
H
V
= V
= 3V
LOGIC
DD
02
01
H
H
100
10
1k
10k
100k
1M
0
1
2
3
4
5
V
(V)
FREQUENCY (Hz)
IH
0
–6
80
60
40
20
0
80
40
20
H
H
CODE = MIDSCALE, V = V
, V = 0V
A
LOGIC B
–12
–18
–24
–30
–36
–42
–48
–54
–60
PSRR @ V
LOGIC
= 5V DC 10% p-p AC
H
H
H
10
08
PSRR @ V
LOGIC
= 3V DC 10% p-p AC
04
02
01
H
H
H
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
100k
80kHz
50k
160kHz
V
W
10k
800kHz
1
5k
2MHz
SCL
2
1k
10k
100k
1M
10M
FREQUENCY (Hz)
400ns/DIV
V
V
W
W
1
1
SCL
2
1
s/DIV
200ns/DIV
V
A
V+ = V
10%
PSRR (dB) = 20 LOG
DD
V
V
MS
V+ = V
DD
1LSB = V+/2
DUT
W
DUT
W
(
)
N
DD
V
%
A
B
A
MS
DD
V
PSS (%/%) =
DD
V
%
V+
V+
B
V
V
MS
MS
NO CONNECT
DUT
DUT
W
+5V
A
B
I
W
A
V
W
IN
AD8610
V
OUT
OFFSET
GND
B
V
MS
–5V
+2.5V
0.1V
=
R
SW
I
SW
DUT
CODE = 0x00
DUT
W
I
= V /R
DD NOMINAL
W
A
V
W
W
I
SW
0.1V
V
MS2
B
B
R
W
= [V
MS1
– V ]/I
MS2 W
V
MS1
GND TO V
DD
A
B
A
B
A
B
W
W
W
V
I
A
B
W
V
O
A
R
S
R
R
D7
S
S
D6
D5
D4
D3
D2
D1
D0
W
R
RDAC
S
LATCH
AND
DECODER
B
A
A
A
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
2
SIGN
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
V
DD
A
W
B
V
V
DD
DD
+
GND
C2
F
C1
0.1
10
F
AD5259
V
LOGIC
GND
SCL
SDA
GND
VCC (~3.3V)
14.4V
R1
SUPPLIES POWER
TO BOTH THE
MICRO AND THE
LOGIC SUPPLY OF
THE DIGITAL POT
70k
C1
AD5259
1
F
R6
10k
R5
10k
–
V
V
DD
VCC (~3.3V)
5V
14.4V
U1
AD8565
LOGIC
R2
A
B
10k
R1
70k
3.5V < V
< 4.5V
COM
SCL
SDA
GND
+
MCU
W
C1
F
AD5259
1
R6
10k
R5
10k
–
V
V
DD
R3
25k
U1
AD8565
LOGIC
R2
A
B
10k
3.5V < V
COM
< 4.5V
SCL
SDA
GND
+
MCU
W
R3
25k
INDEX
AREA
3.00 BSC
PIN
1
3.00
BSC SQ
INDICATOR
6
10
10
1
1.50
BCS SQ
4.90 BSC
3.00 BSC
PIN 1
0.50
BSC
2.48
2.38
2.23
EXPOSED
1
5
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50 BSC
0.95
0.85
0.75
0.50
0.40
0.30
1.74
1.64
1.49
1.10 MAX
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
0.05 MAX
0.02 NOM
SEATING
PLANE
SIDE VIEW
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-187-BA
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