5962-8971001XA [ADI]
CMOS Latched 8-/16-Channel Analog Multiplexers; 锁存CMOS 8位/ 16通道模拟多路复用器
| 型号： | 5962-8971001XA |
| 厂家： | 
ADI |
| 描述： | CMOS Latched 8-/16-Channel Analog Multiplexers |
| 文件： | 总20页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Latched
8-/16-Channel Analog Multiplexers
ADG526A/ADG527A
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
44 V supply maximum rating
ADG526A
VSS to VDD analog signal range
S1
Single- or dual-supply specifications
Wide supply ranges (10.8 V to 16.5 V)
D
WR
Microprocessor compatible (100 ns
pulse)
S16
Extended plastic temperature range (−40°C to +85°C)
Low leakage (20 pA typical)
Low power dissipation (28 mW maximum)
Available in PDIP, CERDIP, SOIC, and PLCC packages
Superior alternative to DG526 and DG527
DECODER/
LATCHES
WR
A0 A1 A2 A3 EN RS
Figure 1. ADG526A
APPLICATIONS
ADG527A
Data acquisition systems
Communication systems
S1A
DA
Automatic test equipment
Microprocessor controlled systems
S8A
S1B
DB
S8B
GENERAL DESCRIPTION
DECODER/
WR
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 single channels and dual 8 channels,
respectively. On-chip latches facilitate microprocessor interfacing.
LATCHES
A0 A1 A2 EN RS
Figure 2. ADG527A
The ADG526A switches one of 16 inputs to a common output,
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs to
a common differential output, depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
PRODUCT HIGHLIGHTS
1.
Single- or Dual-Supply Specifications with a Wide
Tolerance. The devices are specified in the 10.8 V to
16.5 V range for both single and dual supplies.
2.
Easily Interfaced. The ADG526A and ADG527A can be
The ADG526A and ADG527A are designed on an enhanced
LC2MOS process that gives an increased signal capability of VSS
to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These multiplexers
WR
easily interfaced with microprocessors. The
latches the state of the address control lines and the enable
RS
signal
line. The
signal clears both the address and enable data
RS
in the latches, resulting in no output (all switches off).
can be tied to the microprocessor reset pin.
also feature high switching speeds and low RON
.
3.
4.
5.
Extended Signal Range. The enhanced LC2MOS
processing results in a high breakdown and an increased
analog signal range from VSS to VDD
.
Break-Before-Make Switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
Low Leakage. Leakage currents in the range of 20 pA
make these multiplexers suitable for high precision circuits.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADG526A/ADG527A
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions............................8
Typical Performance Characteristics ........................................... 11
Terminology.................................................................................... 12
Timing.............................................................................................. 13
Test Circuits..................................................................................... 14
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings............................................................ 7
REVISION HISTORY
6/08—Rev. B to Rev. C.
2/02—Rev. A to Rev. B.
Updated Format..................................................................Universal
ADG526A LCCC Package Removed ...............................Universal
Changes to Features.......................................................................... 1
Added Applications Section............................................................ 1
Changes to Absolute Maximum Ratings....................................... 7
Added Table 4, Renumbered Sequentially .................................... 8
Added Table 5.................................................................................... 9
Changes to Figure 7 and Figure 8................................................. 11
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 19
Edits to Specifications Table, Dual Supply.....................................2
Edits to Specifications Table, Single Supply...................................3
Edits to Ordering Guide ...................................................................4
Removal of one Pin Configuration and Diagram.........................6
Rev. C | Page 2 of 20
ADG526A/ADG527A
SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.
Table 1.
ADG526A/ADG527A
ADG526A
T Version
K Version
B Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C Unit
Comments
ANALOG SWITCH
Analog Signal Range
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
V min
V max
Ω typ
RON
−10 V ≤ VS ≤ +10 V, IDS = 1 mA;
see Figure 15
450
300
600
400
450 600
300 400
450 600
Ω max
Ω max
VDD = +15 V ( 10ꢀ%,
VSS = −15 V ( 10ꢀ%
300 400
Ω max
VDD = +15 V ( 5ꢀ%,
VSS = −15 V ( 5ꢀ%
RON Drift
RON Match
0.6
5
0.6
5
0.6
5
ꢀ/°C typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
ꢀ typ
−10 V ≤ VS ≤ +10 V, IDS = 1 mA
IS (Off%, Off Input Leakage 0.02
0.02
0.02
nA typ
V1 = 10 V, V2 = 10 V;
see Figure 16
1
0.04
50
1
0.04
50
1
0.04
50
nA max
nA typ
ID (Off%, Off Output
Leakage
V1 = 10 V, V2 = 10 V;
see Figure 17
ADG526A
ADG527A
ID (On%, On Channel
Leakage
ADG526A
ADG527A
IDIFF, Differential Off
Output Leakage
1
1
0.04
200
100
1
1
0.04
200
100
1
200
nA max
nA max
nA typ
0.04
1
V1 = 10 V, V2 = 10 V;
see Figure 18
1
1
200
100
25
1
1
200
100
25
200
nA max
nA max
nA max
V1 = 10 V, V2 = 10 V;
see Figure 19
(ADG527A Only%
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
μA max
pF max
VIN = 0 to VDD
CIN, Digital Input
Capacitance
8
8
8
DYNAMIC
CHARACTERISTICS1
tTRANSITION
200
200
200
ns typ
V1 = 10 V, V2 = 10 V;
see Figure 20
300
50
25
200
300
200
300
100
400
10
300 400
50
300 400
50
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
ns min
tOPEN
See Figure 21
25
10
25
10
WR
200
200
See Figure 22 and Figure 23
See Figure 22 and Figure 24
tON (EN,
tOFF (EN,
%
400
300 400
200
300 400
200
RS
%
400
120
100
300 400
100 120
100
300 400
100 130
100
tW , Write Pulse Width
tS, Address Enable Setup
Time
See Figure 13
See Figure 13
tH, Address Enable Hold
Time
tRS, Reset Pulse Width
10
10
10
ns min
ns min
See Figure 13
See Figure 14
100
100
100
Rev. C | Page 3 of 20
ADG526A/ADG527A
ADG526A/ADG527A
K Version B Version
ADG526A
T Version
Parameter
Off Isolation
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C Unit
Comments
68
68
68
dB typ
VEN = 0.8 V, RL = 1 kΩ, CL =
15 pF,VS = 7 V rms, f = 100 kHz
50
5
50
5
50
5
dB min
pF typ
VS = 7 V rms, f = 100 kHz
VEN = 0.8 V
CS (Off%
CD (Off%
ADG526A
ADG527A
QINJ, Charge Injection
44
22
4
44
22
4
44
4
pF typ
pF typ
pC typ
VEN = 0.8 V
RS = 0 Ω, VS = 0 V;
see Figure 25
POWER SUPPLY
IDD
0.6
20
10
0.6
1.5
20
0.2
10
0.6
20
10
mA typ
mA max
μA typ
mA max
mW typ
mW max
VIN = VINL or VINH
VIN = VINL or VINH
1.5
0.2
28
1.5
0.2
28
ISS
Power Dissipation
28
1 Sample tested at 25°C to ensure compliance.
Rev. C | Page 4 of 20
ADG526A/ADG527A
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND to 0 V, unless otherwise noted.
Table 2.
ADG526A/ADG527A
ADG526A
T Version
K Version
B Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C Unit
Comments
ANALOG SWITCH
Analog Signal Range
VSS
VSS
VSS
VSS
VSS
VSS
V min
VDD
500
VDD
VDD
500
VDD
VDD
500
VDD
V max
Ω typ
RON
0 V ≤ VS ≤ 10 V, IDS
=
0.5 mA; see Figure 15
700
0.6
1000
700
0.6
1000
700
0.6
1000
Ω max
ꢀ/°C typ
RON Drift
0 V ≤ VS ≤ 10 V, IDS
0.5 mA
=
=
RON Match
5
5
5
ꢀ typ
0 V ≤ VS ≤ 10 V, IDS
0.5 mA
IS (Off%, Off Input
Leakage
0.02
0.02
0.02
nA typ
V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 16
1
0.04
50
1
0.04
50
1
0.04
50
nA max
nA typ
ID (Off%, Off Output
Leakage
V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 17
ADG526A
ADG527A
ID (On%, On Channel
Leakage
ADG526A
ADG527A
IDIFF, Differential Off
Output Leakage
(ADG527A Only%
1
1
0.04
200
100
1
1
0.04
200
100
1
200
nA max
nA max
nA typ
0.04
1
V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 18
1
1
200
100
25
1
1
200
100
25
200
nA max
nA max
nA max
V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 19
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
CIN, Digital Input
Capacitance
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
μA max
pF max
VIN = 0 to VDD
8
8
8
DYNAMIC
CHARACTERISTICS1
tTRANSITION
300
300
300
ns typ
V1 = 10 V/0 V, V2 = 0 V/
10 V; see Figure 20
450
50
25
250
450
250
450
100
600
10
450
50
25
250
450
250
450
100
600
10
450
50
25
250
450
250
450
100
600
10
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns min
ns min
tOPEN
See Figure 21
WR
See Figure 22 and Figure 23
See Figure 22 and Figure 24
tON (EN,
tOFF (EN,
%
600
600
600
RS
%
600
120
100
600
120
100
600
130
100
tW Write Pulse Width
tS Address Enable
Setup Time
See Figure 13
See Figure 13
tH Address Enable Hold
Time
10
10
10
ns min
See Figure 13
tRS Reset Pulse Width
Off Isolation
100
100
100
ns min
dB typ
See Figure 14
VEN = 0.8 V, RL = 1 kΩ, CL =
15 pF
68
50
68
50
68
50
dB min
VS = 3.5 V rms, f = 100 kHz
Rev. C | Page 5 of 20
ADG526A/ADG527A
ADG526A/ADG527A
K Version B Version
ADG526A
T Version
Parameter
CS (Off%
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C Unit
Comments
5
5
5
pF typ
VEN = 0.8 V
CD (Off%
ADG526A
ADG527A
QINJ, Charge Injection
44
22
4
44
22
4
44
4
pF typ
pF typ
pC typ
VEN = 0.8 V
RS = 0 Ω, VS = 0 V; see
Figure 25
POWER SUPPLY
IDD
0.6
11
0.6
11
0.6
11
mA typ
mA max
mW typ
mW max
VIN = VINL or VINH
1.5
25
1.5
25
1.5
25
Power Dissipation
1 Sample tested at 25°C to ensure compliance.
Rev. C | Page 6 of 20
ADG526A/ADG527A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
44 V
VDD to VSS
VDD to GND
25 V
VSS to GND
Analog Inputs1
−25 V
Voltage at Sx or Dx Pins
VSS − 2 V to VDD + 2 V
or 20 mA, whichever
occurs first
ESD CAUTION
Continuous Current, Sx or Dx Pins
Pulsed Current, Sx or Dx Pins
1 ms Duration, 10ꢀ Duty Cycle
Digital Inputs1
20 mA
40 mA
Voltage at A, EN, WR, RS
VSS − 4 V to VDD + 4 V
or 20 mA, whichever
occurs first
Power Dissipation (Any Package%
Up to 75°C
Derates Above 75°C
470 mW
6 mW/°C
Operating Temperature Range
Commercial (K Version%
Industrial (B Version%
−40°C to +85°C
−40°C to +85°C
−65°C to +150°C
300°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec%
1
WR RS
Overvoltage at A, EN,
,
, Sx, or Dx pins are clamped by diodes. Limit
current to the maximum rating in Table 3.
Rev. C | Page 7 of 20
ADG526A/ADG527A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
9
28
D
DD
4
3
2
1
28 27 26
NC
RS
27
V
SS
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
PIN 1
IDENTFIER
5
6
25
S7
S15
S14
S13
S12
S11
S10
S16
S15
S14
S13
S12
S11
24 S6
ADG526A
TOP VIEW
(Not to Scale)
23
7
S5
ADG526A
22
8
S4
TOP VIEW
(Not to Scale)
21
20
9
S3
S2
10
S09 11
19 S1
S10 10
S9 11
12 13 14 15 16 17 18
NC = NO CONNECT
GND 12
WR 13
A3 14
NC = NO CONNECT
Figure 4. ADG526A PLCC Pin Configuration
Figure 3. ADG526A PDIP, SOIC, and CERDIP Pin Configuration
Table 4. ADG526A Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VDD
NC
RS
Most Positive Power Supply Potential.
No Connect.
Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
4
5
6
7
8
9
S16
S15
S14
S13
S12
S11
S10
S9
GND
WR
A3
A2
A1
A0
EN
S1
S2
S3
S4
S5
S6
S7
S8
VSS
D
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Source Terminal. This pin can be an input or output.
Ground (0 V) Reference.
Write. The WR signal latches the state of the address control lines and the enable line.
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Logic control inputs. Selects which source terminal is connected to the drain (D).
Enable. Active high logic control input.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Most Negative Power Supply Potential.
Drain Terminal. This pin can be an input or output.
Rev. C | Page 8 of 20
ADG526A/ADG527A
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DA
V
DD
DB
RS
SS
4
3
2
1
28 27 26
3
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
PIN 1
5
6
25
S7A
S7B
S6B
S5B
S4B
S3B
S2B
4
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
WR
IDENTFIER
5
24 S6A
ADG527A
6
23
7
S5A
TOP VIEW
ADG527A
TOP VIEW
7
(Not to Scale)
22
8
S4A
8
(Not to Scale)
21
20
9
S3A
S2A
9
10
10
11
12
13
14
S1B 11
19 S1A
A0
12 13 14 15 16 17 18
NC = NO CONNECT
A1
NC
A2
NC = NO CONNECT
Figure 5. ADG527A PDIP, SOIC Pin Configuration
Figure 6. ADG527A PLCC Pin Configuration
Table 5. ADG527A Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
VDD
DB
Most Positive Power Supply Potential.
Drain Terminal. This pin can be an input or output.
3
RS
Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Ground (0 V) Reference.
Write. The WR signal latches the state of the address control lines and the enable line.
No Connect.
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Logic Control Inputs. Selects which source terminal is connected to the drain (D).
Enable. Active high logic control input.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Most Negative Power Supply Potential.
4
5
6
7
8
9
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
WR
NC
A2
A1
A0
EN
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DA
Drain Terminal. This pin can be an input or output.
Rev. C | Page 9 of 20
ADG526A/ADG527A
Table 6. ADG526A Truth Table1
WR
RS
A3
A2
A1
A0
EN
ON SWITCH
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Retains previous switch condition
None (address and enable latches cleared)
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 X = don’t care.
Table 7. ADG527A Truth Table1
A2
A1
A0
EN
WR
RS
ON SWITCH PAIR
X
X
X
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
X
X
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
Retains previous switch condition
None (address and enable latches cleared)
None
X
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
1 X = don’t care.
Rev. C | Page 10 of 20
ADG526A/ADG527A
TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700
600
500
400
300
200
100
0
1.9
1.8
1.7
1.6
1.5
V
V
= 10.8V
= 0V
DD
SS
V
V
= 15V
= 0V
DD
SS
–20
–15
–10
–5
0
5
10
15
20
5
6
7
8
9
10
11
12
13
14
15
V
(V ) (V)
S
SUPPLY VOLTAGE (V)
D
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply,
TA = 25°C
Figure 7. RON as a Function of VD (VS): Single-Supply Voltage, TA = 25°C
700
600
800
700
600
V
V
= +5V
= –5V
DD
SS
500
400
300
200
100
0
500
SINGLE
SUPPLY
400
V
V
= +10.8V
DD
= –10.8V
SS
300
DUAL
SUPPLY
V
V
= +15V
= –15V
DD
SS
200
100
–20
–15
–10
–5
0
5
10
15
20
5
6
7
8
9
10
11
12
13
14
15
V
(V ) (V)
S
D
SUPPLY VOLTAGE (V)
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
Figure 11. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C
(Note: For VDD and VSS <10 V; V1 = VDD/VSS, V2 = VSS/VDD; See Figure 20)
100
1.0
0.8
0.6
0.4
0.2
0
V
V
= +16.5V
= –16.5V
DD
SS
10
1
I
I
(ON)
(OFF)
D
D
I
(OFF)
S
0.1
0.01
25
35
45
55
65
75
85
95 105 115 125
5
6
7
8
9
10 11 12 13 14 15 16 17
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 12. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C
Figure 9. Leakage Current as a Function of Temperature (Leakage Currents
Reduce as the Supply Voltages Reduce)
Rev. C | Page 11 of 20
ADG526A/ADG527A
TERMINOLOGY
t
OFF (EN)
RON
Delay time between the 50% and 10% points of the digital input
and switch off condition.
Ohmic resistance between Terminal D and Terminal S.
RON Match
tTRANSITION
Difference between the RON of any two channels.
Delay time between the 50% and 90% points of the digital
inputs and switch on condition when switching from one
address state to another.
RON Drift
Change in RON vs. temperature.
IS (Off)
tOPEN
Source terminal leakage current when the switch is off.
Off time measured between 50% points of both switches when
switching from one address state to another.
ID (Off)
Drain terminal leakage current when the switch is off.
VINL
ID (On)
Maximum input voltage for Logic 0.
Leakage current that flows from the closed switch into the body.
VINH
VS (VD)
Minimum input voltage for Logic 1.
Analog voltage on Terminal S or Terminal D.
I
INL (IINH)
CS (Off)
Input current of the digital input.
Channel input capacitance for off condition.
VDD
CD (Off)
Most positive voltage supply.
Channel output capacitance for off condition.
VSS
CIN
Most negative voltage supply.
Digital input capacitance.
IDD
t
ON (EN)
Positive supply current.
Delay time between the 50% and 90% points of the digital input
and switch on condition.
ISS
Negative supply current.
Rev. C | Page 12 of 20
ADG526A/ADG527A
TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
Figure 14 shows the reset pulse width, tRS, and reset turn-off
RS
time, tOFF
(
).
WR
therefore, while
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of
is held low, the latches are transparent and
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, tR = tF = 20 ns.
WR
.
3V
3V
RS
0V
1.5V
WR
0V
1.5V
tRS
tOFF (RS)
tW
tS
tH
V
O
3V
EN, A0, A1,
A2, (A3)
0V
0.8V
2.0V
SWITCH
OUTPUT
0V
0.8V
Figure 13. Timing Sequence
Figure 14. Reset Pulse
Rev. C | Page 13 of 20
ADG526A/ADG527A
TEST CIRCUITS
I
DS
V
V
V
V
DD
DD
SS
SS
V1
D
S
D
I
(ON)
A
D
2.4V
EN
GND
V
S
V1
V2
V1
R
=
ON
I
DS
Figure 15. RON
Figure 18. ID (On)
V
V
V
DD
DD
SS
V
SS
ADG527A
V
V
V
V
DD
DD
SS
EN
0.8V
DA
DB
A
SS
A
D
V2
A
I
(OFF)
S
GND
0.8V
V1
EN
GND
V1
V2
I
= I (OFF) – I (OFF)
DA DB
DIFF
Figure 16. IS (Off)
Figure 19. IDIFF
V
V
DD
DD
SS
V
V
SS
D
0.8V
I
(OFF)
A
D
EN
GND
V1
V2
Figure 17. ID (Off)
Rev. C | Page 14 of 20
ADG526A/ADG527A
V
V
V
V
DD
DD
SS
SS
ADG526A*
A3
A2
ADDRESS
3V
0V
V1
V2
DRIVE (V
)
S1
IN
50%
S2 TO S15
A1
A0
V
50Ω
IN
S16
D
90%
OUTPUT
2.4V
EN
RS
OUTPUT
90%
1MΩ
GND
WR
35pF
tTRANSITION
tTRANSITION
*SIMILAR CONNECTION FOR ADG527A.
Figure 20. Switching Time of Multiplexer, tTRANSITION
V
V
V
V
DD
SS
DD
SS
ADG526A*
A3
A2
5V
S1
3V
0V
ADDRESS
S2 TO S15
A1
A0
V
DRIVE (V
)
50Ω
IN
IN
S16
D
OUTPUT
OUTPUT
50%
2.4V
EN
RS
1kΩ
GND
WR
35pF
tOPEN
*SIMILAR CONNECTION FOR ADG527A.
Figure 21. Break-Before-Make Delay, tOPEN
V
V
V
V
DD
SS
3V
0V
DD
SS
2.4V
RS
ADG526A*
ENABLE
DRIVE (V
A3
A2
50%
90%
5V
S1
)
IN
S2 TO S16
A1
A0
EN
OUTPUT
10%
OUTPUT
D
WR
V
50Ω
IN
1kΩ
GND
tON
(EN)
tOFF
(EN)
35pF
*SIMILAR CONNECTION FOR ADG527A.
Figure 22. Enable Delay, tON (EN) tOFF (EN)
Rev. C | Page 15 of 20
ADG526A/ADG527A
V
V
V
V
DD
SS
SS
DD
EN ADG526A*
2.4V
5V
S1
A3
A2
A1
3V
0V
S2 TO S16
(WR)
DRIVE (V
50%
A0
)
IN
RS
OUTPUT
D
WR
OUTPUT
20%
V
50Ω
IN
1kΩ
GND
35pF
tON (WR)
NOTE:
DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE.
*SIMILAR CONNECTION FOR ADG527A.
WR
)
Figure 23. Write Turn-On Time, tON
(
V
V
V
V
DD
SS
SS
DD
2.4V
EN
ADG526A*
3V
0V
5V
S1
A3
A2
A1
A0
50%
RS DRIVE (V
)
IN
S2 TO S16
WR
80%
OUTPUT
OUTPUT
tOFF (RS)
D
RS
V
50Ω
IN
1kΩ
GND
35pF
NOTE:
DEVICE WR MUST PULSE LOW PRIOR TO APPLYING RS PULSE.
*SIMILAR CONNECTION FOR ADG527A.
RS
Figure 24. Reset Turn-Off, tOFF
(
)
V
V
V
V
DD
DD
SS
SS
ADG526A*
A3
A2
A1
A0
2.4V
RS
D
3V
V
IN
R
S
S1
C
1nF
V
L
V
S
O
EN
0V
V
50Ω
IN
V
O
ΔV
O
GND WR
Q
= C × ΔV
L O
INJ
*SIMILAR CONNECTION FOR ADG527A.
Figure 25. Charge Injection
Rev. C | Page 16 of 20
ADG526A/ADG527A
OUTLINE DIMENSIONS
0.100 (2.54)
MAX
0.005 (0.13)
MIN
28
15
14
0.610 (15.49)
0.500 (12.70)
1
PIN 1
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.018 (0.46)
0.008 (0.20)
15°
0°
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.026 (0.66)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
1.565 (39.75)
1.380 (35.05)
28
1
15
0.580 (14.73)
0.485 (12.31)
14
0.625 (15.88)
0.600 (15.24)
0.100 (2.54)
BSC
0.195 (4.95)
0.125 (3.17)
0.250 (6.35)
MAX
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.700 (17.78)
MAX
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
COMPLIANT TO JEDEC STANDARDS MS-011
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
Figure 27. 28-Lead Plastic Dual In-Line Package [PDIP]
(N-28)
Dimensions shown in inches and (millimeters)
Rev. C | Page 17 of 20
ADG526A/ADG527A
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.020 (0.51)
MIN
4
5
26
25
0.048 (1.22)
0.042 (1.07)
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
12
19
18
0.045 (1.14)
0.025 (0.64)
R
0.456 (11.582)
0.450 (11.430)
SQ
0.120 (3.04)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28A)
Dimensions shown in inches and (millimeters)
18.10 (0.7126)
17.70 (0.6969)
28
15
14
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0
.25 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
BSC
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 29. 28-Lead Standard Small Outline Package [SOIC] Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
ADG526A/ADG527A
ORDERING GUIDE
Model
ADG526AKN
ADG526AKNZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−40°C to +85°C
Package Description
28-Lead PDIP
28-Lead PDIP
28-Lead SOIC
28-Lead SOIC
28-Lead SOIC
28-Lead SOIC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead CERDIP
28-Lead CERDIP
Package Option
N-28
N-28
ADG526AKR
RW-28
RW-28
RW-28
RW-28
P-28A
P-28A
P-28A
P-28A
Q-28
ADG526AKR-REEL
ADG526AKRZ1
ADG526AKRZ-REEL1
ADG526AKP
ADG526AKP-REEL
ADG526AKPZ1
ADG526AKPZ-REEL1
ADG526ATQ
ADG526ABQ
Q-28
ADG526ATCHIPS
DIE
ADG527AKN
ADG527AKNZ1
ADG527AKR
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
28-Lead PDIP
28-Lead PDIP
28-Lead SOIC
28-Lead SOIC
28-Lead SOIC
28-Lead PLCC
28-Lead PLCC
N-28
N-28
RW-28
RW-28
RW-28
P-28A
P-28A
ADG527AKR-REEL
ADG527AKRZ1
ADG527AKP
ADG527AKPZ1
1 Z = RoHS Compliant Part, # denotes RoHS complaint product, may be top or bottom marked.
Rev. C | Page 19 of 20
ADG526A/ADG527A
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01532-0-6/08(C)
Rev. C | Page 20 of 20
相关型号：
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IC 8-CHANNEL, DIFFERENTIAL MULTIPLEXER, CQCC28, CERAMIC, LCC-28, Multiplexer or Switch
ADI
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