5962-8971101LA [FAIRCHILD]
Correlator, 1-Bit, CMOS, CDIP24, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24;
| 型号： | 5962-8971101LA |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Correlator, 1-Bit, CMOS, CDIP24, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24 CD |
| 文件： | 总16页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC2 0 2 3
CMOS Dig it a l Ou t p u t Co rre la t o r
6 4 -Bit , 2 5 , 3 0 , 3 5 , a n d 5 0 MHz
Description
Features
The TMC2023 is a monolithic 64-bit correlator with a 7-bit
three-state buffered digital output. This device consists of
three 64-bit independently clocked shift registers, one 64-bit
reference holding latch, and a 64-bit independently clocked
digital summing network. The device is available in versions
capable of 25, 30, 35, and 50 MHz parallel correlation rates.
• 25, 30, 35, and 50 MHz correlation rates
• All inputs and outputs TTL compatible
• Serial data input, parallel correlation output
• Programmable word length
• Independently clocked registers
• Programmable threshold detection and flag output
• Available in 24 pin Ceramic and Plastic DIP, 28-lead
Plastic and Ceramic chip carrier and 28-contact chip
carrier
The 7-bit threshold register allows the user to preload a
binary number from 0 to 64. Whenever the correlation is
equal to or greater than the number in the threshold register,
the threshold flag goes HIGH.
• Available to Standard Military Drawing (SMD)
• Pin-Compatible with TDC1023
• Output format flexibility
The 64-bit shift mask register (M register) allows the user to
mask or selectively to choose “no compare” bit positions,
thereby accomodating any desired word length.
• Three-state outputs
• Low-power CMOS
Applications
• Check sorting equipment
• High density recording
• Bar code identification
The reference word is serially shifted into the B register.
Bringing LDR HIGH parallel loads the data into the R refer-
ence latch. This allows the user to serially preload a new ref-
erence word into the B register while correlation is taking
Block Diagram
CLK S
INV
A
IN
A
A
A
A
OUT
1
2
64
CLK A
PIPELINED
DIGITAL
SUMMER
(3 STAGES)
7
1
LATCH
TFLG
7
TS
R
R
R
64
T REG
LDR
1
2
7
CLK T
CLK B
B
B
B
B
OUT
1
2
64
B
IN
IN
M
M
M
M
M
OUT
1
2
64
CLK M
65-2023-01
IO
0-6
Rev. 1.0.0
TMC2023
PRODUCT SPECIFICATION
Applications (cont.)
Description (cont.)
place between the A register and the R latch. The two words
are continually compared bit-by-bit by exclusive-OR cir-
cuits. Each exclusive-OR provides one bit to the digital sum-
mer. The output is a 7-bit word representing the number of
positions which agree at any one time between the A register
and R latch. A control provides either true or inverted binary
output formats.
• Radar signature recognition
• Video frame synchronization
• Electro-optical navigation
• Pattern and character recognition
• Cross-correlation control systems
• Error correction coding
• Asynchronous communication
• Matched filtering
Built with Fairchild Semiconductor’s one-micron double
level metal OMICRONC™ low power CMOS process, the
TMC2023 is available in a 24-pin ceramic side brazed pack-
age, 24-pin Plastic Dual-In-Line Package, 28-contact plastic
leadless chip carrier and 28-contact chip carrier. The CMOS
TMC2023 is pin compatible with the bipolar TDC1023.
Cross-Correlation
When LDR goes HIGH, the B register contents are copied
into the reference latch (R latch). This useful feature allows
correlation to take place between data in the R latch and the
A register while a new reference is being serially clocked
into the B register. If the new reference is n bits long, it
requires n rising edges of CLK to load this data into the B
register. For the timing diagram, n = 64. LDR is set HIGH
during the final (nth) CLK B cycle, so that the new reference
word is copied into the R latch. The minimum LOW and
Functional Description
General Information
The TMC2023 consists of an input section and an output
section. The input section contains the A, B, and M registers,
an R latch, XOR/AND logic and a pipelined summer net-
work. The output section consists of threshold, inversion and
three-state logic.
HIGH level pulse widths for LDR are shown as t
PWL
and
t , respectively.
PWH
Continuous Correlation
The TMC2023 contains three 1 x 64 serial shift registers (A,
B, and M). The operation of these registers is identical and
each has its own input, output, and clock. As shown in the
Timing Diagrams, valid data is loaded into register A (B, M)
on the rising edge of CLK A (CLK B, CLK M). Data is valid
After the new reference is loaded, the data to be correlated is
clocked through the A register. Typically, CLK A and CLK S
can be tied together. This allows a new correlation score to
be computed for each shift of the A register data relative to
the fixed reference word in the R latch. The digital summer is
internally partitioned into three pipelined stages. Therefore,
a correlation score for a particular alignment of the A register
data and the R latch reference appears at the summer output
three CLK S cycles later. After an additional output delay of
if present at the input for a setup time of at least t
SSR
before
and a hold time of t after the rising clock edge.
H
The summing process is initiated when the comparison result
between the A register and R latch is clocked into the sum-
ming network by a rising edge of CLK S. Typically, CLK A
and CLK S are tied together so that a new correlation score is
computed for each new alignment of the A register and R
latch. When LDR goes HIGH, the contents of register B are
copied into the R latch. With LDR LOW, a new template
may be entered serially into register B, while parallel corre-
lation takes place between register A and the R latch. In the
case of continuous correlation, LDR is held HIGH so that the
R latch contents continuously track those of the B register.
t , the correlation data is valid at the output pins (IO
DCOR 0-
). If this correlation result is equal to or exceeds the value in
6
the threshold register, then TFLG goes HIGH. TFLG is valid
after the third rising edge of CLK S.
t
DF
Threshold Register Load
The timing sequence for loading the threshold (T) register is
shown in the Timing Diagrams. The T register holds the 7-bit
threshold value to be compared with each correlation result.
The rising edge of CLK T loads the data present on the IO
pins into the T register. T flag logic is pipelined 3 stages,
0-6
The summing network consists of three pipelined stages.
Therefore, the total correlation score for a given set of A and
B register contents appears at the summer output three CLK
with the summer. The new value loaded into the threshold
register will affect the TFLG on the third CLK S (plus an
output delay t ) following the T register load.
DF
S cycles later. Data on the output pins IO is available after
0-6
an additional propagation delay, denoted t
Timing Diagrams.
on the
DCOR
The output buffers must be in a high-impedance state
(disabled) when the T register is programmed from an
external source. After a delay of t
DIS
HIGH, the output buffers are disabled. The data pins IO
0-6
may then be driven externally with the new threshold data.
The data must be present for a setup time of t before
from the time TS goes
The correlation result is compared with the contents of the
threshold register. TFLG goes HIGH if the correlation equals
or exceeds the threshold value. TFLG is valid after a delay of
SCOR
t
from the third CLK S rising edge.
DF
2
PRODUCT SPECIFICATION
TMC2023
and t after the rising edge of CLK T for correct operation.
H
The minimum LOW and HIGH level pulse widths for
register, except that its parallel outputs are ANDed with the
exclusive-ORed outputs from the A register and R latch.
CLK T are shown below as t
PWL
and t respectively.
PWH
Many uses of the TMC2023 digital correlator require dis-
After TS is set LOW, there is an enable delay of t
ENA
before
abling the correlation between certain bit positions (A and
i
the internal correlation data is available at pins IO
.
R ) of input words A and R. While correlation data is being
i
0-6
clocked into the A and/or B register, a mask word may be
entered into the M register. Where no comparison is to be
made, zeroes are entered in those M register positions. The
exclusive-OR result between each bit position is ANDed
with a bit from the M register. Thus, if a particular mask bit
Invert Control Timing
Most applications will tie the INVERT control HIGH or
LOW depending on system requirements. In the few situa-
tions in which the control is used dynamically, the user must
observe special timing constraints.
(M ) is zero, the output correlation between A and B for that
i
bit position will be disabled. Consequently, a zero correla-
tion is presented to the digital summer for each masked bit
position.
Because INVERT governs logic located between the master
and slave latches of the data output register, its setup and
hold requirements differ from those of the data and other
controls. The device will respond to changes on INV when-
ever CLOCK is HIGH and will ignore it when CLOCK is
LOW. To minimize the data output delay and to avoid induc-
ing errors, the user should observe the following timing con-
straints:
The Mask register is useful for changing correlation word
length and location within the registers. Where a word is
undefined or no correlation is to take place, the M register
should contain a zero. Conversely, it must be loaded with a
one in each position where correlation is desired
The M register is useful for building logic functions. Note
1. Set INVERT to the desired state for the next output on
or before the rising edge of CLOCK. If INVERT is
asserted a few nanoseconds after the rising edge, the
data output may be similarly delayed.
that for each bit A and R , the correlation logic is:
i
i
Ai + Ri = A R + A R (A exclusive-OR R )
i
i
i
i
i
i
This result is complemented at the input of the AND gates
and ANDed with the mask bit (M ) resulting in:
2. More importantly, keep INVERT in the desired state
until after the falling edge of CLOCK, to avoid corrupt-
ing the output data. If INVERT is changed several nano-
seconds before the falling edge of CLOCK, the data will
likewise change. If it is changed just before the falling
edge, an indeterminate output may result.
i
[A R + A R ] * M
i
i
i
i
i
The last step, performed in the digital summer, is to sum the
above result over all bit positions simultaneously for a corre-
lation at time n:
Mask Register
n
In addition to the A and B shift references, the TMC2023 has
another independently clocked register: the M, or mask
register. The M register functions identically to the A and B
C(n + 3)=
[(Ai XNOR Bi)AND Mi]
å
i = n – 63
where i = 1, 2, 3... and n = correlation word length
Pin Assignments
V
1
2
3
4
5
6
7
8
9
24 CLK B
23 CLK M
22 CLK A
21 LDR
DD
M
IN
IN
IN
CLK A
CLK M
CLK B
26
27
28
1
18
17
16
15
14
13
12
NC
A
B
IO
IO
IO
IO
IO
IO
0
1
2
3
4
5
CLK
CLK S
INV
20 M
OUT
OUT
OUT
19 A
18 B
V
DD
TS
17 TFLG
16 GND
V
2
DD
IO
6
M
3
IN
IN
IO 10
5
15 IO
14 IO
13 IO
0
1
2
A
4
IO 11
4
IO 12
3
65-2023-02
3
TMC2023
PRODUCT SPECIFICATION
Pin Descriptions
Pin
J2, J7
C3, R3
Name Package Package
Function
Power
GND
16
1
19, 20 Ground
V
DD
1, 2
Supply Voltage. The TMC2023 operates from a single +5V supply. All V
and
DD
GND pins must be connected.
Control
INV
Inverter Output. Control that inverts the 7-bit digital output. When a HIGH level is
applied to this pin, the outputs IO are logically inverted. See the Timing
0-6
Diagrams for setup and hold requirements.
TS
10
25
Three-State Enable. The three-state control enables and disables the output
buffers. A HIGH level applied to this pin forces outputs into the high impedance
state. This control also allows loading of the internal threshold register.
LDR
21
Load Reference. Control that allows parallel data to be loaded from the B register
into the reference latch for correlation. If LDR is held HIGH, the R latch is
transparent.
Clocks
CLK A
22
23
24
5
26
27
28
7
A Register Clock. Input clocks. Clock input pins for the A register. Each register
may be independently clocked.
CLK M
CLK B
CLK T
CLK S
Inputs
M Register Clock. Input clocks. Clock input pins for the M register. Each register
may be independently clocked.
B Register Clock. Input clocks. Clock input pins for the B register. Each register
may be independently clocked.
Threshold Register. Threshold register clock. Clock input used to load the T
register.
6
8
Digital Summer Clock. Clock input that allows independent clocking of the
pipelined summer network.
M
IN
2
3
Mask Register. Mask register input. Allows the user to choose “no-compare” bit
positions. A “0” in any bit location will result in a no-compare state for that location
(bit position masked).
A
B
4
6
Shift Register. Shift register inputs to the A 64-bit serial register.
Shift Register. Shift register inputs to the B 64-bit serial register.
IN
IN
Outputs
IO
9,10,11, 11,12, Correlation Score. Bidirectional data pins. When outputs are enabled (TS LOW),
12,13, 13,14, data is a 7-bit binary representation of the correlation between the unmasked
6-0
14,15 15,16,17 portions of the R latch and the A register. lO is the MSB. These pins also serve
6
as parallel inputs to load the threshold register. Data present one setup time before
CLK T goes HIGH will be latched into the threshold register.
TFLG
17
21
Threshold Flag. The TFLG output goes HIGH whenever the correlation score is
equal to or greater than the number loaded into the T register (0 to 64).
B
A
18
23
24
22
19
20
Shift Register B. Outputs of shift registers B, A, and M, respectively.
OUT
These may be used to cascade multiple devices.
Shift Register A.
OUT
M
Shift Register M.
OUT
No Connect
NC None
5,18
No Connect. These pins should be left unconnected.
4
PRODUCT SPECIFICATION
TMC2023
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min.
-0.5
-0.5
Typ.
Max.
Units
Power Supply Voltage
Input Voltage
+7.0
V
V
V
V
+0.5
DD
Outputs
Applied Voltage2
Forced Current3,4
Short Circuit Duration
(Single output in HIGH state to GND)
Temperature
-0.5
-3.0
+0.5
DD
V
6.0
mA
1 second
Operating, Case
Operating, Junction
Lead, Soldering (10 seconds)
Storage
-60
-65
+130
+175
+300
+150
°C
°C
°C
°C
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current, flowing into the device.
Operating Conditions
Temperature Range
Standard
Extended
Parameter
Min.
Nom. Max.
Min.
Nom. Max. Units
V
Power Supply Voltage
Clock Pulse Width, LOW
TMC2023
4.75
5.0
5.25
4.5
5.0
5.5
Volts
DD
t
t
t
t
PWL
15
12
8
15
14
10
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Clock Pulse Width, HIGH
TMC2023
PWH
SCOR
SSR
15
12
8
15
14
8
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Data Setup Time, Correlator
TMC2023
12
10
9
14
10
10
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Data Setup Time, Shift Register (A , B , M )
IN IN IN
TMC2023
12
13
10
9
ns
ns
ns
TMC2023-1, -2
TMC2023-3
8
7
5
TMC2023
PRODUCT SPECIFICATION
Operating Conditions (continued)
Temperature Range
Standard Extended
Nom. Max.
Parameter
Min.
Min.
Nom. Max. Units
t
H
Data Input Hold Time, Correlator and Shift Register
All grades
0
0
ns
f
CLK Frequency, Correlator, Shift Register and Flag Sections
CLK
TMC2023
25
30
35
50
25
30
35
50
MHz
MHz
MHz
MHz
V
TMC2023-1
TMC2023-2
TMC2023-3
V
V
V
Input Voltage, Logic HIGH
Input Voltage, Logic HIGH, A,B,M,S CLKS
Input Voltage, Logic LOW
2.0
2.0
2.0
2.4
IH
V
lHC
IL
0.8
-2.0
4.0
70
0.8
-2.0
4.0
V
I
I
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
Case Temperature
mA
mA
°C
OH
OL
T
0
A
C
T
-55
125
°C
Electrical Characteristics
Temperature Range
Standard Extended
Min. Max. Min. Max. Units
Parameter
Conditions
I
Power Supply Current,
Quiescent
V
DD
= Max, V = LOW, T = HIGH
IN
5
10
mA
DDQ
S
I
Power Supply Current,
Unloaded
V
= Max, T = HIGH
S
DDU
DD
TMC2023, f
CLK
= 25 MHz
55
75
55
75
mA
mA
mA
mA
mA
mA
V
TMC2023-1, f
TMC2023-2, f
TMC2023-3, f
= 30 MHz
= 35 MHz
= 50 MHz
CLK
CLK
CLK
75
75
100
+10
-10
100
+10
-10
I
I
Input Current, Logic HIGH
Input Current, Logic LOW
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= Max, V = V
IN DD
IH
= Max, V = 0V
IN
IL
V
V
I
Output Voltage, Logic HIGH
Output Voltage, Logic LOW
Output Leakage Current, HIGH1
Output Leakage Current, LOW1
Short Circuit Output Current
= Min, I
OH
= Max
2.4
2.4
OH
= Min, l = Max
OL
0.4
+40
-40
0.4
+40
-40
V
OL
= Max, V = VDD
IN
mA
mA
OZH
OZL
OS
I
= Max, V = GND
IN
l
= Max, Output HIGH, one pin to
-100
-100 mA
ground, one second duration
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz
10
10
10
10
pF
pF
l
A
T = 25°C, f = 1 MHz
A
O
Note:
1. These values are the I and I for the T Register.
IL IH
6
PRODUCT SPECIFICATION
TMC2023
Switching Characteristics
Temperature Range
Standard Extended
Min. Max. Min. Max.
Parameter
Conditions
= Min.
Units
t
t
t
Output Delay, Correlator
TMC2023
V
DD
DCOR
DSR
DF
C
LOAD
= 40 pF
22
19
17
22
20
18
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Output Delay, Shift Register
TMC2023
V
DD
= Min.
C
LOAD
= 40 pF
22
20
18
25
22
20
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Output Delay, Flags
TMC2023
V
DD
= Min.
C
LOAD
= 40 pF
20
17
15
4
22
19
17
4
ns
ns
ns
ns
TMC2023-1, -2
TMC2023-3
t
t
Output Hold Time All Grades
V
DD
= Min.
HO
C
= 40 pF
LOAD
V = Min.
DD
Three-State Output Enable Delay
TMC2023
ENA
C
LOAD
= 40 pF
20
16
15
25
20
18
ns
ns
ns
TMC2023-1, -2
TMC2023-3
t
Three-State Output Disable Delay
TMC2023
V
C
= Min.
DIS
DD
= 40 pF
LOAD
20
16
14
24
18
16
ns
ns
ns
TMC2023-1, -2
TMC2023-3
Application Notes
The TMC2023 can be cascaded to implement correlations of
more than 64 bits. Typically, all clocks are tied together and
the A, B, and M outputs of preceding stages are connected to
the respective inputs of subsequent stages. An external sum-
mer is required to generate the composite correlation score.
Use of the T register and TFLG require additional hardware
for this configuration. The TMC2221 correlator provides 128
taps.
When comparing a multi-bit word to a single-bit reference,
the outputs from the individual correlators must be appropri-
ately weighted. This weighting reflects the relative impor-
tance of the different bit positions. Normally simple shifts
division by 2, 4, 8… provide the required weighting. The
TMC2220 correlator provides 32-tap 4x1 correlation.
7
TMC2023
PRODUCT SPECIFICATION
LDR = HIGH
t
t
PWH
PWL
T = LOW
S
B
= REFERENCE
IN
T REGISTER PRELOADED
CLK A
CLK S
C
C
C
C
N+3
N
N+1
N+2
t
SSR
t
H
A
A
A
A
A
A
N+4
IN
N
N+1
N+2
N+3
t
DCDR
IO
S
S
F
S
F
S
F
S
F
0-6
N-4
N-3
N-2
N-1
N
t
t
D
DF
F
TFLG
N-4
N-3
N-2
N-1
N
65-2023-03
Figure 1. Continuous Correlation
C
N
C
C
C
CLK S
CLK B
2
3
C
C
C
C
C
C
5
63
64
1
2
3
4
t
t
H
SSR
B
B
B
B
B
3
B
B
5
IN
64
1
2
4
t
t
PWH
PWL
LDR
t
DCDR
IO
OUT
0-6
1
t
T
B
= LOW
DSR
S
= PRELOADED
IN
T REGISTER PRELOADED
t
HO
B
B
B
B
B
3
B
B
5
OUT
64
1
2
4
65-2023-04
Figure 2. Cross-Correlation
8
PRODUCT SPECIFICATION
TMC2023
1/f
CLK
CLK A
CLK S
C
C
C
C
C
N+4
N
N+1
N+2
N+3
A
A
A
A
A
N+4
A
N
N+1
N+2
N+3
IN
TS
t
t
ENA
DIS
IO
OUT
0-6
S
S
S
S
S
N+1
N-4
N-2
N-1
N
IO
0-6
IN
THRESHOLD DATA
t
t
H
SCOR
t
t
PWH
PWL
CLK T
TFLG
t
DF
F
F
F
N+1
N-1
N
B
= REFERENCE
IN
LDR = HIGH
NEW THRESHOLD
65-2023-05
Figure 3. Threshold Register Loading
V
DD
SUBSTRATE
p
n
CONTROL
INPUT
CLK
INV
INVALID
65-2023-06
65-2023-07
Figure 4. Invert Control Timing
Figure 5. Equivalent Input Circuit
V
DD
SUBSTRATE
p
t
ENA
TS
t
OUTPUT
DIS
0.5V
2.0V
0.8V
Three-State
Outputs
n
0.5V
High Impedance
65-2023-08
65-2023-09
Figure 6. Equivalent Output Circuit
Figure 7. Threshold Levels for Three-State
Measurements
9
TMC2023
PRODUCT SPECIFICATION
CLK A
CLK B
CLK M
CLK S
A
B
A
B
A
B
A
B
A
B
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
TMC2023
#1
TMC2023
#2
TMC2023
#N
INPUT
DATA
IN
IN
M
IO
M
M
IO
M
M
IO
0-6
IN
0-6
IN
0-6
IN
7
7
7
SUMMER
log N + 7
65-2023-10
2
Figure 8. Cascading for Extended-Length Correlation
MSB
7
A
B
IN
TMC2023
#1
IN
INPUT
7
7
7
7
7
7
A
B
REGISTER
IN
DATA
TMC2023
#2
Ö2
Ö4
Ö8
WORD
IN
A
B
IN
TMC2023
#3
IN
CORRELATION
OUTPUT
SUMMER
A
B
IN
TMC2023
#4
IN
REFERENCE
CODE
LSB
7
7
A
B
IN
TMC2023
#N
N-1
Ö2
IN
65-2023-11
Figure 9. Multi-Bit x 1-Bit Correlation
10
PRODUCT SPECIFICATION
TMC2023
Mechanical Dimensions
28-Lead LCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not be wider than
the B1 dimension.
Min.
Max.
Min.
Max.
A
.060
.050
.022
.006
.442
.100
.088
.028
.022
.460
1.52
1.27
.56
2.54
2.24
.71
3, 6
3, 6
2
A1
B1
B3
D/E
D1/E1
D2/E2
e
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.).
.15
.56
2, 5
11.23
11.68
.300 BSC
7.62 BSC
3. Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
.150 BSC
.050 BSC
.040 REF
.020 REF
3.81 BSC
1.27 BSC
1.02 REF
.51 REF
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
h
4
4
j
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
L1
.045
.055
.095
.015
1.14
1.40
2.41
.38
L2
.075
.003
1.91
.08
L3
5
ND/NE
N
7
7
28
28
6. Chip carriers shall be constructed of a minimum of two ceramic layers.
LID
See Note 1
PLANE 2
PLANE 1
D
A1
L3
B3
B1
E
DETAIL "A"
A
Index Corner
(j) x 45¡
(h) x 45¡
3 PLCS
4
DETAIL "A"
e
D2
D1
L2
L1
11
TMC2023
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
24-Lead Plastic DIP .300" Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
A
—
.210
—
—
.38
5.33
—
A1
A2
B
.015
.115
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
.195
2.53
4.95
.014
.045
.008
1.125
.005
.300
.240
.36
1.14
.20
.022
.070
.015
1.275
—
.56
1.78
.38
B1
C
4
2
D
28.58
.13
32.39
—
D1
.325
.280
7.62
6.10
8.26
7.11
E
E1
e
2
5
.100 BSC
2.54 BSC
eB
L
N
—
.430
.160
—
10.92
4.06
.115
2.92
24
24
D
1
12
E1
D1
13
24
E
e
A
A1
C
L
eB
B1
B
12
TMC2023
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
24-Lead Plastic DIP .600" Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
A
—
.250
—
—
.38
6.35
—
A1
A2
B
.015
.125
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
.195
3.18
4.95
.014
.030
.008
1.150
.005
.600
.485
.36
.76
.022
.070
.015
1.290
—
.56
1.78
.38
B1
C
.20
4
2
D
29.21
.13
32.77
—
D1
.625
.580
15.24
12.32
15.88
14.73
E
E1
e
eB
L
2
5
.100 BSC
2.54 BSC
—
.700
.200
—
17.78
5.08
.115
2.92
N
24
24
D
12
1
E1
D1
13
24
E
e
A1
A
A2
C
L
eB
B
B1
13
PRODUCT SPECIFICATION
TMC2023
Mechanical Dimensions (continued)
28-Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45¡.
A
.165
.090
.020
.013
.026
.485
.450
.180
.120
—
4.19
2.29
.51
4.57
3.05
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm).
A1
A2
B
.021
.032
.495
.456
.33
.53
B1
.66
.81
D/E
D1/E1
D3/E3
e
12.32
11.43
12.57
11.58
3
2
.300 BSC
.050 BSC
.042 .048
7.62 BSC
1.27 BSC
1.07 1.22
J
ND/NE
N
7
7
28
28
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A
A1
– C – LEAD COPLANARITY
ccc C
B
A2
14
PRODUCT SPECIFICATION
TMC2023
Mechanical Dimensions (continued)
24-Lead Side Brazed DIP Package
Notes:
Inches
Millimeters
1. Index area: a notch or a pin one identification mark shall be
located adjacent to pin one. The manufacturer's identification
shall not be used as pin one identification mark.
Symbol
Notes
Min.
Max.
Min.
Max.
A
.120
.014
.040
.008
1.180
.575
.175
.023
.065
.015
1.220
.610
3.05
.36
4.44
.58
2. The minimum limit for dimension "b2" may be .023 (.58mm)
for leads number 1, 12, 13, and 24 only.
b1
b2
c1
D
7
2
7
1.02
.20
1.65
.38
3. Dimension "Q" shall be measured from the seating plane to the
base plane.
29.97
14.60
30.99
15.49
4. The basic pin spacing is .100 (2.54mm) between centerlines.
Each pin centerline shall be located within ±.010 (.25mm) of its
exact longitudinal position relative to pins 1 and 24.
E
e
.100 BSC
.600 BSC
2.54 BSC
15.24 BSC
4, 8
6
5. Applies to all four corners (leads number 1, 12, 13, and 24).
6. "eA" shall be measured at the centerline of the leads.
eA
L
.125
.200
.060
3.18
5.08
1.52
.025
.005
.005
0.63
0.13
0.13
3
5
Q
7. All leads - Increase maximum limit by .003(.08mm) measured
at the center of the flat when lead finish is applied.
S1
S2
—
—
—
—
8. Twenty-two spaces.
D
Note 1
12
1
E
13
24
S1
eA
S2
A
L
Q
c1
b2
b1
e
Standard Military Drawing
These devices are also available as products manufactured, tested, and screened in compliance with Standard Military Draw-
ings (SMD). The nearest vendor equivalent product is shown in the table; however, the applicable SMD is the sole controlling
document defining the SMD product.
SMD
Product Number
TMC2023J7V
TMC2023J7V1
TMC2023J2V
TMC2023J2V1
TMC2023C3V
TMC2023C3V1
Speed
25MHz
30MHz
25MHz
30MHz
25MHz
30MHz
Package
5962-89711 01JA
5962-89711 02JA
5962-89711 01LA
5962-89711 02LA
5962-89711 013A
5962-89711 023A
24 Pin Side Brazed DIP 0.6" Wide
24 Pin Side Brazed DIP 0.6" Wide
24 Pin Side Brazed DIP 0.3" Wide
24 Pin Side Brazed DIP 0.3" Wide
28 Contact Chip Carrier
28 Contact Chip Carrier
15
TMC2023
PRODUCT SPECIFICATION
Ordering lnformation
Product
Number
fCLK
(MHz)
Package
Marking
Temperature
STD: T = 0 to 70°C
Screening
Commercial
Commercial
Commercial
Commercial
Package
24-pin 0.3" Plastic DIP
24-pin 0.3" Plastic DIP
24-pin 0.3" Plastic DIP
24-pin 0.3" Plastic DIP
TMC2023N2C
TMC2023N2C1
TMC2023N2C2
TMC2023N2C3
TMC2023J2V
TMC2023J2V1
TMC2023J2V2
TMC2023J2V3
TMC2023N7C
TMC2023N7C1
TMC2023N7C2
TMC2023N7C3
TMC2023J7V
TMC2023J7V1
TMC2023J7V2
TMC2023J7V3
TMC2023R3C
TMC2023R3C1
TMC2023R3C2
TMC2023R3C3
TMC2023C3V
25
30
35
50
25
30
35
50
25
30
35
50
25
30
35
50
25
30
35
50
25
2023J2C
2023J2C1
2023J2C2
2023J2C3
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
EXT: T = -55 to 125°C
MIL-STD-883 24-pin 0.3" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.3" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.3" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.3" Ceramic Side Brazed DIP
2023J2V
2023J2V1
2023J2V2
2023J2V3
2023N7C
2023N7C1
2023N7C2
2023N7C3
2023J7V
C
EXT: T = -55 to 125°C
C
EXT: T = -55 to 125°C
C
EXT: T = -55 to 125°C
C
STD: T = 0 to 70°C
Commercial
Commercial
Commercial
Commercial
24-pin 0.6" Plastic DIP
24-pin 0.6" Plastic DIP
24-pin 0.6" Plastic DIP
24-pin 0.6" Plastic DIP
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
EXT: T = -55 to 125°C
MIL-STD-883 24-pin 0.6" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.6" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.6" Ceramic Side Brazed DIP
MIL-STD-883 24-pin 0.6" Ceramic Side Brazed DIP
C
EXT: T = -55 to 125°C
2023J7V1
2023J7V2
2023J7V3
2023R3C
2023R3C1
2023R3C2
2023R3C3
2023C3V
C
EXT: T = -55 to 125°C
C
EXT: T = -55 to 125°C
C
STD: T = 0 to 70°C
Commercial
Commercial
Commercial
Commercial
28 Lead PLCC
28 Lead PLCC
28 Lead PLCC
28 Lead PLCC
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
STD: T = 0 to 70°C
A
EXT: T = -55 to 125°C
MIL-STD-883 28-Contact Hermetic Ceramic Chip
Carrier
C
TMC2023C3V1
TMC2023C3V2
TMC2023C3V3
30
35
50
EXT: T = -55 to 125°C
MIL-STD-883 28-Contact Hermetic Ceramic Chip
Carrier
2023C3V1
2023C3V2
2023C3V3
C
EXT: T = -55 to 125°C
MIL-STD-883 28-Contact Hermetic Ceramic Chip
Carrier
C
EXT: T = -55 to 125°C
MIL-STD-883 28-Contact Hermetic Ceramic Chip
Carrier
C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock#DS70002023
Ó 1998 Fairchild Semiconductor Corporation
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