SL1461MPAS [ZARLINK]
Wideband PLL FM Demodulator; 宽带锁相环调频解调器型号: | SL1461MPAS |
厂家: | ZARLINK SEMICONDUCTOR INC |
描述: | Wideband PLL FM Demodulator |
文件: | 总13页 (文件大小:539K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL1461SA
Wideband PLL FM Demodulator
Advance Information
DS4358
ISSUE 1.3
September 1999
The SL1461SA is a wideband PLL FM demodulator,
intended primarily for application in satellite tuners.
The device contains all elements necessary, with the
exception of external oscillator sustaining network and loop
feedback components, to form a complete PLL system
operating at frequencies up to 800MHz.
Ordering Information
SL1461SA/KG/MPAS
An AFC with window adjust is provided, whose output
signalcanbeusedtocorrectforanyfrequencydriftatthehead
end local oscillator.
FEATURES
I Single chip PLL system for wideband FM
demodulation
I Simple low component count application
I Allows for application of threshold extension
I Fully balanced low radiation design
I High operating input sensivity
I Improved VCO stability with variations in supply or
temperature
AFC PUMP
1
2
3
4
5
6
7
8
16
15
14
13
12
AFC OUTPUT
AFC WINDOW ADJUST
VEE
VCC
VIDEO FEEDBACK +
VIDEO –
OSCILLATOR +
OSCILLATOR –
AGC BIAS
VIDEO +
11
10
VIDEO FEEDBACK –
VIDEO OUTPUT
RF INPUT
AGC OUTPUT
RF INPUT
9
I AGC detect and bias adjust
MP16
I 75Ω video output drive with low distortion levels
I Dynamic self biasing analog AFC
I Full ESD Protection*
Fig.1 Pin connections - top view
APPLICATIONS
I Satellite receiver systems
* Normal ESD handling procedures should be observed
I Data communications Systems
6
14
VIDEO
AGC BIAS
FEEDBACK +
8
12
13
VIDEO +
VIDEO –
RF INPUTS
9
7
11
10
1
AGC OUTPUT
VIDEO
FEEDBACK –
VIDEO
OUTPUT
AFC PUMP
4
5
16
LOCAL
OSCILLATOR
AFC OUTPUT
2
AFC WINDOW
ADJUST
Fig.2 SL1461SA block diagram
SP1461SA Advance Information
ELECTRICAL CHARACTERISTICS
Tamb =-20°Cto+80°C, VCC =+4.5Vto+5.5V. Theelectricalcharacteristicsareguaranteedbyeitherproductiontestordesign.
They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Value
Units
Characteristics
Conditions
Min.
Typ.
Max.
Supply current
36
40
mA
MHz
dBm
dBm
MHz/V
%
Operating frequency
Input sensitivity
300
800
-40
Preamp limiting
Input overload
0
VCO sensitivity (dF/dV)
VCO linearity
25
32
25
39
Refer to application in Fig. 3
Refer to application in Fig. 3; with
13.5MHz p-p deviation
See note 5
VCO supply stability
VCO temperature stability
Phase detector gain
2.0
20
MHz/V
KHz/°C
V/rad
V/rad
Ω
See note 5
0.5
0.25
570
25
Differential loop filter
Single ended loop filter
Single ended
Loop amplifier input impedance
Loop amplifier output impedance
Loop amplifier open loop gain
Loop amplifier gain bandwidth product
Loop amplifier output swing
Video drive output impedance
Video drive:
450
55
700
Single ended
Ω
38
dB
Single ended
240
MHz
Vp-p
Ω
Single ended
Single ended
1.2
95
75
Luminance nonlinearity
- differential gain
1.9
0.5
1.0
5
2.5
3
%
%
1KΩ load, See note 3 and 4
75KΩ load, See note 3 and 4
- differential phase
Degree 75KΩ load, See note 3 and 4
- intermodulation
-40
dB
dB
%
See notes 1, 3 and 4
- signal/noise
66
72
0.3
0.4
1KΩ load, See note 2 and 4
1KΩ load, See note 3 and 4
1KΩ load, See note 3 and 4
Maximum load voltage drop 2V
- Tilt
3
- baseline distortion
2
%
AGC output current
10
0
400
250
400
µA
µA
µA
µA
µA
V
AGC bias current
AFC window current
0
400µA gives 1.5V deadband window
AFC charge pump current
AFC leakage current
AFC output saturation voltage
50
With charge pump disabled
AFC output enabled
10
0.4
Note 1. Product of input modulation f 1 at 4.43MHz, 13.5MHz p–p deviation and f 2 at 6MHz p–p deviation, (PAL chroma and sound
subcarriers).
Note 2. Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz bandwidth
with no input modulation.
Note 3. Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk.
Note 4. See page 3
Note 5. Assumingoperatingfrequencyof479.5MHzsetwithVCC@5.0Vandambienttemperatureof+20°C.OnlyappliestoApplication
shown in Fig. 3. also refer to Fig. 8.
2
Advance Information SL1461SA
TEST CONFIGURATION
BASE BAND VIDEO 1V p–p
VIDEO GENERATOR
ROHDE & SCHWARZ SGPF
TV SAT TEST TX
ROHDE & SCHWARZ SFZ
RF CARRIER FREQ 479.5MHz
FM MODULATION 13.5MHz P–P
PRE–EMPHASISED VIDEO
SL1461 TEST APPLICATION BOARD
See Fig. 3 for details
MONTFORD
TEST OVEN
PRE EMPHASISED BASE BAND VIDEO
VIDEO AMPLIFIER/
DE EMPHASISED NETWORK
DE EMPHASISED BASE BAND VIDEO 1V p–p
VIDEO ANALYSER
ROHDE & SCHWARZ UAF
The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in
theElectricalCharacteristicsTablecoincidewithhightemperaturesandextremesofsupplyvoltage.Noadjustmenttotherecorded
figures has been made to compensate for the effects of temperature on the external components of the application test board, in
particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature
compensation of the external circuitry will result in performance figures closer to the stated typical figures.
Fig.2 SL1461SA block diagram
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE at 0V
Characteristics
Conditions
Min.
Typ.
Max.
Supply voltage
-0.3
7
V
Vp-p
V
RF input voltage
2.5
RF input DC offset
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
125
Oscillator DC offset
Video DC offset
V
V
Video feedback DC offset
Video output DC offset
AFC pump DC offset
AFC disable DC offset
AFC deadband DC offset
AGC bias DC offset
AGC output DC offset
Storage temperature
Junction temperature
V
V
V
V
V
V
V
°C
°C
°C/W
150
MP16 package thermal resistance,
chip to ambient
111
3
SP1461SA Advance Information
ABSOLUTE MAXIMUM RATINGS cont.
All voltages are referred to VEE at 0V
Characteristics
Conditions
Min.
Typ.
Max.
MP16 package thermal resistance,
chip to case
41
°C/W
Power consumption at 5.5V
ESD protection - pins 1 to 15
ESD protection - Pin 16
250
mW
kV
2
Mil-std-883 method 3015 class 1
Mil-std-883 method 3015 class 1
1.7
kV
+5V
1nF
C12
100nF
47 F
C4
AGC BIAS
AFC WINDOW ADJUST
RV2
2K
50K
R6
27K
RV1
C3
C1
C2
47nF
4K7
100nF
TP4
R1
1
2
3
4
5
6
7
8
16
D1
15
14
13
12
100pF
C11
R5
TP1
TP2
BB515
BB515
C5
1K2
470nF
C10
R2
5K1
R4
D2
11
10
TP3
100pF
1K2
VIDEO OUTPUT
C9
47 F
4n7
C6
9
R3
C7
4K7
1nF
1nF
C8
RF INPUT
Fig.3 Standard application circuit
FUNCTIONAL DESCRIPTION
threshold performance, and gives a good safety margin over
the typical sensitivity of
-40dBm.
The SL1461SA is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiringaminimumexternalcomponentcount.Itcontainsall
the elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signaltocorrectforanyfrequencydriftintheoutdoorunitlocal
oscillator. A block diagram is contained in Fig. 2 and the
typical application in Fig. 3.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which
is generatedby an on–board oscillator. The oscillator block
uses an external varactor tuned sustaining network and is
optimised for high linearity over the normal deviation range.
A typical frequency versus voltage characteristic for the
oscillator is contained in Fig. 7. The loop output is designed
to compensate for first order temperature variation effects;
the typical stability is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential
orsingleendedmode;iftheappropriatephasedetectorgains
are assumed in calculating loop filters, both modes should
give the same loop response.
The internal pin connections are contained in Fig.6/6a
In normal applications the second satellite IF frequency
of typically 402 or 479.5MHz is fed to the RF preamplifier,
which has a working sensitivity of typically -40 dBm,
depending on application and layout. The preamplifier
contains an RF level detect circuit, which generates an AGC
signal that can be used for controlling the gain of the IF
amplifier stages, so maintaining a fixed level to the RF input
of the SL1461SA, for optimum threshold performance. The
bias point of the AGC circuit can be adjusted to cater for
variation in AGC line voltage requirement and device input
power. The typical AGC curves are shown in Fig. 9. It is
recommended that the device is operated with an input signal
between-30and-35dBm.Thisensuresoptimumlinearityand
Theloopamplifierdrivesa75Ω outputimpedancebuffer
amplifier,whichcaneitherbeconnectedtoa75Ω loadorused
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
4
Advance Information SL1461SA
DESIGN OF PLL LOOP PARAMETERS
C1
R2
GAIN = K VOLT/RAD
D
RF INPUT
R1
BASEBAND OUTPUT
GAIN = K RAD SEC/VOLT
0
VCO
Fig.4
TheSL1461SAisnormallyusedasatype1secondorder
loop and can be represented by the above diagram. For such
a system the following parameters apply;
where:
K0 is the VCO gain in radian seconds per volt
K
D is the phase detector gain in volts per radian
n is the natural loop bandwidth
is the loop damping factor
R1 is loop amplifier input impedance
1
Note: K0 is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
2
and
Fromthesefactorstheloop3dBbandwidthcanbedetermined
from the following expression;
K0KD
1
2
2
n
2
n
AFC FACILITY
The SL1461SA contains an analog frequency error
compared with two reference voltages, corresponding to the
extremes of the deadband, or window. These voltages are
variable and set by the window adjust input.
The comparators produce two digital outputs
corresponding to voltages above or below the voltage
window,orfrequencyaboveorbelowdeadband.Thesedigital
control signals are used to control a complimentary current
source pump. The current signals are then fed to the input of
an amplifier which is arranged as an integrator, so integrating
the
detect circuit, which generates DC voltage proportional to the
integral of frequency error. If the incident RF is high then the
AFCvoltageincreases, iflowthenthevoltagedecreases. The
AFC voltage can then be converted by an ADC to be read by
the micro controller for frequency fine tuning; if used in an I2C
system it is recommended the device is used with either the
SP5055 or SP5056 frequency synthesiser which contains an
internal ADC readable via the I2C bus.
The voltage corresponding to frequency alignment is
arbitrary and user defined; if used with the SP5055 it is
suggested the aligned voltage is 0.375 VCC , corresponding to
the centre code of the ADC on port 6.
The AFC detect circuit contains a deadband centre
around the aligned frequency. The deadband can be adjusted
fromzerowindowtoapproximately25MHzwidthassumingan
oscillator dF/dV of 15MHz/V. If the incident RF is within this
window the AFC voltage does not integrate, except by
component leakage.
pulses into a DC voltage.
If the frequency is correctly aligned both the current
source and sink are disabled, therefore the DC output voltage
remains constant. There will be a small drift due to component
leakage; the maximum drift can be calculated from;
With reference to Fig.5; in normal operation the
demodulated video is fed to a dual comparator where it is
5
SP1461SA Advance Information
WINDOW
ADJUST
V
HI
V
ALIGN
LO
V
FREQ
VCC
VCC
+
–
REXT
C
EXT
BASEBAND
VIDEO
V
AFC
+
–
VEE
Fig.5 AFC system block diagram
6
Advance Information SL1461SA
VCC
AGC BIAS
VREF; 2.7V
VREF; 2V
AGC OUTPUT
AGC output
AGC bias adjust
VREF; 3V
AFC WINDOW
2x1500
RF INPUTS
VREF; 1.6V
RF inputs
AFC window adjust
VCC
AFC PUMP
VIDEO +
10K
VIDEO –
AFC OUTPUT
330
330
2mA
2mA
AFC output stage
Video amp outputs
Fig.6 SL1461SA I/O port internal circuitry
7
SP1461SA Advance Information
VREF; 1.2V
2 x 5k
OSCILLATOR +
OSCILLATOR –
Local oscillator
FROM PHASE DETECTOR
2x570
VCC
68
VIDEO
OUTPUT
105
VIDEO
FEEDBACK +
VIDEO
FEEDBACK –
4mA
Video amp feedback inputs
Fig.6a SL1461SA I/O port internal circuitry
Video output drive
FREQ MHz
520
500
480
460
440
420
400
360
1
1.5
2
2.5
3
3.5
4
4.5
5
DC VOLTAGE
Fig.7 Typical VCO frequency vs DC control voltage
8
Advance Information SL1461SA
VCO STABILITY vs TEMP and SUPPLY
480
479.5
479
478.5
478
SUPPLY (V)
4.5
4.75
5
477.5
477
5.25
5.5
476.5
476
475.5
–20
5
30
5 5
80
TEMP/°C
Fig.8 SL1461SA VCO centre frequency uncompensated temperature stability
2.0
1.5
AGC
OUTPUT
1.0
0.5
VOLTAGE
AGC BIAS RESISTOR 5.1K
AGC BIAS CURRENT 297
A
AGC LOAD RESISTOR 3.9K
AGC BIAS RESISTOR 10.5K
AGC BIAS CURRENT 150
A
AGC LOAD RESISTOR 4.7K
AGC BIAS RESISTOR 32K
AGC BIAS CURRENT 52
A
AGC LOAD RESISTOR 10K
–70
–60
–50
–40
–30
–20
–10
0
VCC = 5.0 VOLTS
RF INPUT LEVEL (dBm) UNMODULATED
Fig.9 SL1461SA AGC output voltage for differing values of AGC bias resistor
APPLICATION NOTES
Capture range
Under conditions when there is no RF input signal
EXAMPLE
Loop out of lock
present, the SL1461SA may react to spurious radiation from
the free running oscillator coupling into the RF inputs.
Because of the constant phase error between the VCO input
tothephasedetectorandthespuriouslycoupledsignalviathe
RF input, the phase comparator will drive the control voltage
to either the bottom or the top of the range.
Tuning voltage =4.3V (maximum)
frequency =520MHz (maximum
Itisonlypossibletocapturesignalsbelowthisfrequencysince
the VCO is already at its maximum frequency.
Testing of capture range should be done with the device
operatingundernormalconditions. Aninputsignalofbetween
-35dBm to -10dBm is suitable for such a measurement.
In such a case, the capture range will be asymmetrical
about the VCO free running frequency, since any control
voltage will only be able to tune the VCO in one direction if the
tuning voltage is already at the max or min.
This effect can be avoided by driving the RF input
differentially or achieving good common mode rejection to the
VCO signal.
The lock range is independant of the above effects and
will be symmetric about the centre of the phase detector S-
curve provided the VCO is correctly aligned.
9
SP1461SA Advance Information
Lock range
Lock range should be symmetric about the centre of the
S-curve. When the oscillator is sitting in the centre of the
S-curve, thetwovideooutputswillbeatthesameDCvoltage.
The easiest way to centralise the VCO is to input an RF
carrier which is being modulated by a low frequency
squarewave. The tuning coil(s) should be adjusted until the
AFC voltage toggles between 0.2V and VCC-0.7V. The smaller
the FM deviation of the squarewave used, the more accurate
the setting will be.
A pre-emphasised video input containing black to white
transitions can also be used for this setting, since the DC
contentinapre-emphasedvideoismuchlessthanthatinnon
pre–emphasised video. This is important as any dc content in
the input waveform will introduce an offset in the AFC transi-
tion point.
RF oscillator design
The standard application circuit for the SL1461SA is
shown in Fig.3 The layout of the VCO tank should follow
normal good RF techniques - ie as compact as possible. This
will minimise parasitics, thus giving improved VCO linearity
and stability. The PCB layout used for testing purpose is
shown in Fig. 10.
Setting up of oscillator
The setting can be confirmed by measuring the DC
voltage on the two video outputs, the voltages should be the
same when the oscillator is centred around the incoming
frequency. ThisDCmeasurementmustbecarriedoutwithan
unmodulated carrier of the required frequency. Modulation
mustnotbepresent,sincebydefinition,thedcvoltageswould
be changing, thus making accurate measurement difficult.
The VCO should be set up so that the desired input RF
frequency is at the centre of the lock range. This will coincide
with the centre of the S-curve and the point at which the AFC
toggles when set to zero deadband.
10
Advance Information SL1461SA
Fig.10 Layout of demo board with component locations
11
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