SL1461S [ETC]

WIDEBAND PLL FM DEMODULATOR; 宽带锁相环调频解调器
SL1461S
型号: SL1461S
厂家: ETC    ETC
描述:

WIDEBAND PLL FM DEMODULATOR
宽带锁相环调频解调器

文件: 总13页 (文件大小:196K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SEPTEMBER 1993  
PRELIMINARY INFORMATION  
D.S. 3754 1.6  
SL1461  
WIDEBAND PLL FM DEMODULATOR  
The SL1461 is a wideband PLL FM demodulator, intended  
primarily for application in satellite tuners.  
The device contains all elements necessary, with the  
exception of external oscillator sustaining network and loop  
feedback components, to form a complete PLL system  
operating at frequencies up to 800MHz.  
An AFC with window adjust is provided, whose output  
signal can be used to correct for any frequency drift at the head  
AFC PUMP  
AFC WINDOW ADJUST  
VEE  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
AFC OUTPUT  
VCC  
VIDEO FEEDBACK +  
VIDEO –  
OSCILLATOR +  
OSCILLATOR –  
AGC BIAS  
end local oscillator  
.
VIDEO +  
11  
10  
VIDEO FEEDBACK –  
VIDEO OUTPUT  
RF INPUT  
AGC OUTPUT  
RF INPUT  
FEATURES  
J Single chip PLL system for wideband FM  
demodulation  
9
J
J
J
J
J
Simple low component count application  
Allows for application of threshold extension  
Fully balanced low radiation design  
High operating input sensitivity  
MP16  
Fig. 1 Pin connections top view  
AGC detect and bias adjust  
J 75W video output drive with low distortion  
APPLICATIONS  
J Satellite receiver systems  
Data communications systems  
levels  
J
Dynamic self biasing analog AFC  
Full ESD protection *  
J
J
ORDERING INFORMATION  
*
Normal ESD handling procedures should be observed  
SL1461S/KG/MPAS  
6
14  
VIDEO  
FEEDBACK +  
AGC BIAS  
8
12  
13  
VIDEO +  
VIDEO –  
RF INPUTS  
9
7
11  
10  
1
AGC OUTPUT  
VIDEO  
FEEDBACK –  
VIDEO  
OUTPUT  
AFC PUMP  
4
5
16  
LOCAL  
OSCILLATOR  
AFC OUTPUT  
2
AFC WINDOW  
ADJUST  
Fig. 2 SL1461 block diagram  
SL1461  
ELECTRICAL CHARACTERISTICS  
Tamb=–20°C to )80°C, VCC=)4.5V to )5.5V. These characteristics are guaranteed by either production test or design.  
They apply within the specified ambient temperature and supply voltage unless otherwise stated.  
Value  
Characteristics  
Supply current  
Units  
Conditions  
Min  
Typ  
Max  
40  
36  
mA  
MHz  
dBm  
dBm  
MHz/V  
%
Operating frequency  
Input sensitivity  
300  
800  
–40  
Preamp limiting  
Input overload  
0
VCO sensitivity (dF/dV)  
VCO linearity  
25  
32  
39  
Refer to application in Fig. 3a  
.25  
Refer to application in Fig. 3a; with  
13.5MHz p–p deviation  
Phase detector gain  
0.5  
0.25  
V/rad  
V/rad  
Differential loop filter  
Single ended loop filter  
Loop amplifier input  
impedance  
450  
570  
25  
700  
W
Single ended  
Single ended  
Loop amplifier output  
impedance  
W
Loop amplifier open loop gain  
38  
dB  
Single ended  
Single ended  
Loop amplifier gain bandwidth  
product  
240  
MHz  
Loop amplifier output swing  
1.2  
95  
Vp–p  
Single ended  
V
ideo drive output impedance  
ideo drive;  
55  
75  
W
V
Luminance nonlinearity  
– differential gain  
1.9  
0.5  
1.0  
5
2.5  
3
%
%
1KW load, See note 3 & 4  
75W load, See note 3 & 4  
75W load, See note 3 & 4  
See notes 1+3 & 4  
– differential phase  
– intermodulation  
Degree  
dB  
dB  
%
–40  
– Signal/noise  
66  
72  
0.3  
0.4  
1KW load, See note 2 & 4  
1KW load, See note 3 & 4  
1KW load, See note 3 & 4  
Maximum load voltage drop 2V  
–Tilt  
3
– baseline distortion  
AGC output current  
AGC bias current  
2
%
10  
0
400  
250  
400  
mA  
mA  
mA  
mA  
mA  
V
AFC window current  
AFC charge pump current  
AFC leakage current  
AFC output saturation voltage  
0
400 A gives 1.5V deadband window  
m
50  
10  
With charge pump disabled  
AFC output enabled  
0.4  
Note 1. Product of input modulation f at 4.43MHz, 13.5MHz p–p deviation and f2 at 6MHz p–p deviation, (PAL chroma and  
1
sound subcarriers).  
Note 2. Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz  
bandwidth with no input modulation.  
Note 3 Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk.  
Note 4 See page 3  
2
SL1461  
TEST CONFIGURATION  
BASE BAND VIDEO 1V p–p  
VIDEO GENERATOR  
ROHDE & SCHWARZ SGPF  
TV SAT TEST TX  
ROHDE & SCHWARZ SFZ  
RF CARRIER FREQ 479.5MHz  
FM MODULATION 13.5MHz P–P  
PRE–EMPHASISED VIDEO  
SL1461 TEST APPLICATION BOARD  
See Fig. 3a for details  
MONTFORD  
TEST OVEN  
PRE EMPHASISED BASE BAND VIDEO  
VIDEO AMPLIFIER/  
DE EMPHASISED NETWORK  
DE EMPHASISED BASE BAND VIDEO 1V p–p  
VIDEO ANALYSER  
ROHDE & SCHWARZ UAF  
The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in  
the Electrical Characteristics Table coincide with high temperatures and extremes of supply voltage. No adjustment to the recorded  
figures has been made to compensate for the effects of temperature on the external components of the application test board, in  
particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature  
compensation of the external circuitry will result in performance figures closer to the stated typical figures.  
Note 4.  
ABSOLUTE MAXIMUM RATINGS  
All voltages are referred to V at 0V  
.
EE  
Characteristic  
Supply voltage  
Min  
Max  
7
Units  
Conditions  
–0.3  
V
V p–p  
V
RF input voltage  
2.5  
RF input DC offset  
Oscillator +&–DC offset  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–55  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
125  
V
V
V
V
ideo +&–DC offset  
V
ideo feedback +&–DC offset  
ideo output DC offset  
V
V
AFC pump DC offset  
AFC disable DC offset  
AFC deadband DC offset  
AGC bias DC offset  
V
V
V
V
AGC output DC offset  
Storage temperature  
Junction temperature  
V
°C  
°C  
°C/W  
150  
MP16 package thermal resistance,  
chip to ambient  
111  
3
SL1461  
ABSOLUTE MAXIMUM RATINGS cont.  
All voltages are referred to V at 0V  
.
EE  
MP16 package thermal resistance  
chip to case  
41  
°C/W  
Power consumption at 5.5V  
ESD protection – pins 1 to 15  
ESD protection – pin 16  
250  
mW  
kV  
2
Mil–std –883 method 3015 class1  
Mil–std –883 method 3015 class1  
1.7  
kV  
V CC  
100nF  
AGC BIAS  
2K  
AFC WINDOW ADJUST  
50K  
27K  
47mF  
47nF  
4K7  
100nF  
1
2
3
4
5
6
7
8
16  
15  
120pF  
BB833  
BB833  
14  
13  
12  
22pF  
22pF  
1K2  
1K2  
11  
10  
5K1  
120pF  
VIDEO OUTPUT  
4n7  
9
47mF  
4K7  
1nF  
1nF  
RF INPUT  
Fig.3. Standard application circuit with oscillator referenced to ground  
V CC  
100nF  
AGC BIAS  
AFC WINDOW ADJUST  
2K  
50K  
27K  
47mF  
47nF  
4K7  
100nF  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
220R  
82pF  
BB833  
BB833  
1K2  
1K2  
620R  
82pF  
11  
10  
5K1  
VIDEO OUTPUT  
4n7  
9
47mF  
1nF  
4K7  
1nF  
RF INPUT  
Fig.3a Application circuit used for video drive characterisation measurements  
4
SL1461  
FUNCTIONAL DESCRIPTION  
The SL1461 is a wideband PLL FM demodulator, optimised  
for application in satellite receiver systems and requiring a  
minimum external component count. It contains all the  
elements required for construction of a phase locked loop  
circuit, with the exception of tuning components for the local  
oscillator, and an AFC detector circuit for generation of error  
signal to correct for any frequency drift in the outdoor unit local  
oscillator. A block diagram is contained in Fig. 2 and the typical  
application in Fig. 3.  
are shown in Fig. 9.  
The output of the preamplifier is fed to the mixer section  
which is of balanced design for low radiation. In this stage the  
RF signal is mixed with the local oscillator frequency, which is  
generated by an on–board oscillator. The oscillator block uses  
an external varactor tuned sustaining network and is  
optimised for high linearity over the normal deviation range. A  
typical frequency versus voltage characteristic for the  
oscillator is contained in Fig. 7. The loop output is designed to  
compensate for first order temperature variation effects; the  
typical stability is shown in Fig. 8  
The internal pin connections are contained in Fig.6/6a.  
The output of the mixer is then fed to the loop amplifier  
around which feedback is applied to determine loop transfer  
characteristic . Feedback can be applied either in differential  
or single ended mode; if the appropriate phase detector gains  
are assumed in calculating loop filters, both modes should  
give the same loop response.  
In normal applications the second satellite IF frequency of  
typically 402 or 479.5MHz is fed to the RF preamplifier, which  
has a working sensitivity of typically –40 dBm, depending on  
application and layout. The preamplifier contains an RF level  
detect circuit, which generates an AGC signal that can be used  
for controlling the gain of the IF amplifier stages, so  
maintaining a fixed level to the RF input of the SL1461, for  
optimum threshold performance. The bias point of the AGC  
circuit can be adjusted to cater for variation in AGC line voltage  
requirement and device input power. The typical AGC curves  
The loop amplifier drives a 75W output impedance buffer  
amplifier, which can either be connected to a 75  
W
load or used  
to drive a high input impedance stage giving greater linearity  
and approximately 6dB higher demodulated signal output  
level.  
DESIGN OF PLL LOOP PARAMETERS  
C1  
R2  
GAIN = K VOLT/RAD  
D
RF INPUT  
R1  
BASEBAND OUTPUT  
GAIN = K RAD SEC/VOL  
T
0
VCO  
Fig.  
4
The SL1461 is normally used as a type 1 second order loop  
and can be represented by the above diagram. For such a  
system the following parameters apply;  
where:  
K0 is the VCO gain in radian seconds per volt  
KD is the phase detector gain in volts per radian  
wn is the natural loop bandwidth  
z
is the loop damping factor  
R1 is loop amplifier input impedance  
t1 + C1.R1  
t2 + C1.R2  
and  
Note:  
K
K
is dependant on sensitivity of VCO used.  
= 0.25V/rad single ended, 0.5V/rad differential  
O
D
From these factors the loop 3dB bandwidth can be determined  
from the following expression;  
K0KD  
t1 +  
w2n  
2
2
2
2z  
wn  
w3dB + w2n(2z2 ) 1) " wn2 (2z ) 1) ) 1  
Ǹ
t2 +  
1
Ǹ
2
Which approximates to w3dB + 2wnĂĂwhenĂĂz +  
5
SL1461  
AFC FACILITY  
The SL1461 contains an analog frequency error detect  
circuit, which generates DC voltage proportional to the  
integral of frequency error. If the incident RF is high then the  
AFC voltage increases, if low then the voltage decreases. The  
AFC voltage can then be converted by an ADC to be read by  
the micro controller for frequency fine tuning; if used in an I2C  
system it is recommended the device is used with either the  
SP5055 or SP5056 frequency synthesiser which contains an  
internal ADC readable via the I2C bus.  
compared with two reference voltages, corresponding to the  
extremes of the deadband, or window. These voltages are  
variable and set by the window adjust input.  
The comparators produce two digital outputs  
corresponding to voltages above or below the voltage window  
,
or frequency above or below deadband. These digital control  
signals are used to control a complimentary current source  
pump. The current signals are then fed to the input of an  
amplifier which is arranged as an integrator, so integrating the  
pulses into a DC voltage.  
If the frequency is correctly aligned both the current source  
and sink are disabled, therefore the DC output voltage  
remains constant. There will be a small drift due to component  
leakage; the maximum drift can be calculated from;  
The voltage corresponding to frequency alignment is  
arbitrary and user defined; if used with the SP5055 it is  
suggested the aligned voltage is 0.375 V , corresponding to  
CC  
the centre code of the ADC on port 6.  
The AFC detect circuit contains a deadband centred  
around the aligned frequency. The deadband can be adjusted  
from zero window to approximately 25MHz width assuming an  
oscillator dF/dV of 15MHz/V. If the incident RF is within this  
window the AFC voltage does not integrate, except by  
component leakage.  
VCC  
dV  
dt  
I
2500.C  
+
whereĂĂĂI +  
Ă,ĂĂ C + CEXT  
REXT  
With reference to Fig.5; in normal operation the  
demodulated video is fed to a dual comparator where it is  
WINDOW  
ADJUST  
VHI  
VALIGN  
VLO  
FREQ  
VCC  
VCC  
+
REXT  
CEXT  
BASEBAND  
VIDEO  
VAFC  
+
VEE  
Fig. 5 AFC system block diagram  
6
SL1461  
VCC  
AGC BIAS  
VREF; 2.7V  
VREF; 2V  
AGC OUTPUT  
AGC output  
AGC bias adjust  
VREF; 3V  
AFC WINDOW  
2x1500  
RF INPUTS  
VREF; 1.6V  
RF inputs  
AFC window adjust  
VCC  
AFC PUMP  
VIDEO +  
10K  
VIDEO –  
AFC OUTPUT  
330  
330  
2mA  
2mA  
AFC output stage  
Video amp outputs  
Fig.6 SL1461 I/O port internal circuitry  
7
SL1461  
VREF; 2.5V  
2 x 5k  
OSCILLATOR +  
OSCILLATOR –  
Local oscillator  
FROM PHASE DETECTOR  
2x570  
VCC  
68  
VIDEO  
OUTPUT  
105  
VIDEO  
FEEDBACK +  
VIDEO  
FEEDBACK –  
4mA  
Video amp feedback inputs  
Video output drive  
Fig. 6a SL1461 I/O port internal circuitry  
FREQ MHz  
482  
FREQ MHz  
520  
500  
480  
460  
440  
420  
400  
360  
481  
480  
479  
1
1.5  
2
2.5  
DC VOLTAGE  
Fig. 7 Typical VCO frequency vs DC control voltage  
3
3.5  
4
4.5  
5
478  
–20  
80  
20  
TEMP/°C  
Fig. 8 SL1461 VCO centre frequency uncompensated  
temperature stability  
.
8
SL1461  
2.0  
1.5  
1.0  
0.5  
AGC  
OUTPUT  
VOLTAGE  
AGC BIAS RESISTOR 5.1K  
AGC BIAS CURRENT 297mA  
AGC LOAD RESISTOR 3.9K  
AGC BIAS RESISTOR 10.5K  
AGC BIAS CURRENT 150mA  
AGC LOAD RESISTOR 4.7K  
AGC BIAS RESISTOR 32K  
AGC BIAS CURRENT 52mA  
AGC LOAD RESISTOR 10K  
–70  
–60  
–50  
–40  
–30  
–20  
–10  
0
VCC = 5.0 VOLTS  
RF INPUT LEVEL (dBm) UNMODULATED  
Fig.9 SL1461 AGC output voltage for differing values of AGC bias resistor  
APPLICATION NOTES  
Capture range  
Under conditions when there is no RF input signal present,  
the SL1461 may react to spurious radiation from the free  
running oscillator coupling into the RF inputs. Because of the  
constant phase error between the VCO input to the phase  
detector and the spuriously coupled signal via the RF input,  
the phase comparator will drive the control voltage to either the  
bottom or the top of the range.  
In such a case, the capture range will be asymmetrical  
about the VCO free running frequency, since any control  
voltage will only be able to tune the VCO in one direction if the  
tuning voltage is already at the max or min.  
S–curve. When the oscillator is sitting in the centre of the  
S–curve, the two video outputs will be at the same DC voltage.  
RF oscillator design  
The standard application circuit for the SL1461 is shown in  
Fig.3 The layout of the VCO tank should follow normal good  
RF techniques – ie as compact as possible. This will minimise  
parasitics, thus giving improved VCO linearity and stability.  
The PCB layout used for testing purpose is shown in Fig. 11.  
This effect can be avoided by driving the RF input  
differentially or achieving good common mode rejection to the  
VCO signal.  
The lock range is independant of the above effects and will  
be symmetric about the centre of the phase detector S–curve  
provided the VCO is correctly aligned.  
Setting up of oscillator  
The VCO should be set up so that the desired input RF  
frequency is at the centre of the lock range. This will coincide  
with the centre of the S–curve and the point at which the AFC  
toggles when set to zero deadband.  
The easiest way to centralise the VCO is to input an RF  
carrier which is being modulated by a low frequency  
squarewave. The tuning coil(s) should be adjusted until the  
EXAMPLE  
AFC voltage toggles between 0.2V and V  
the FM deviation of the squarewave used, the more accurate  
the setting will be.  
A pre–emphasised video input containing black to white  
transitions can also be used for this setting, since the DC  
content in a pre–emphased video is much less than that in non  
pre–emphasised video. This is important as any dc content in  
the input waveform will introduce an offset in the AFC transition  
point.  
. The smaller  
CC–0.7V  
Loop out of lock  
Tuning voltage =4.3V (maximum)  
frequency =520MHz (maximum  
It is only possible to capture signals below this frequency since  
the VCO is already at its maximum frequency  
Testing of capture range should be done with the device  
operating under normal conditions. An input signal of between  
–35dBm to –10dBm is suitable for such a measurement.  
.
The setting can be confirmed by measuring the DC voltage  
on the two video outputs, the voltages should be the same  
when the oscillator is centred around the incoming frequency  
.
This DC measurement must be carried out with an  
unmodulated carrier of the required frequency. Modulation  
must not be present, since by definition, the dc voltages would  
be changing, thus making accurate measurement difficult.  
Lock range  
Lock range should be symmetric about the centre of the  
9
SL1461  
NOTES  
Circuit schematic is  
shown in Fig. 3.  
TP1=VIDEO –  
TP2=VIDEO +  
TP3=AGC O/P  
TP4=AFC O/P  
All surface mount  
components mounted  
on underside of board  
Fig. 11 Layout of demo board with oscillator referenced to GND  
10  
SL1461  
11  
SL1461  
PACKAGE DETAILS  
Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre.  
9.80/10.01  
(0.386/0.394)  
16 LEAD MINIATURE PLASTIC MP16  
0.69 (0.027) MAX  
AT 4 PLACES  
PIN 1  
1.27 (0.050) NOM  
PIN SPACING  
PIN 1 IDENTIFICATION  
0.25/0.51  
(0.010/0.020) X45°  
0.19/0.25  
(0.007/0.010)  
8°MAX  
0.41/1.27  
(0.016/0.050)  
0.35/0.49  
(0.014/0.019)  
0.10/0.25  
(0.004/0.010)  
5.80/6.20  
(0.228/0.244)  
HEADQUARTERS OPERATIONS  
CUSTOMER SERVICE CENTRES  
GEC PLESSEY SEMICONDUCTORS  
Cheney Manor, Swindon,  
F
FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F  
Fax: (1) 64 46 06 07  
Wiltshire SN2 2QW, United Kingdom.  
F
F
F
F
GERMANY Munich Tel: (089) 3609 06 0 Tx: 523980 Fax: (089) 3609 06 55  
T
el: (0793) 518000  
ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993  
Fax: (0793) 51841  
1
JAPAN Tokyo Tel: (03) 3296–0281 Fax: (03) 3296–0228  
NORTH AMERICA Integrated Circuits and Microwave Products,  
Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023  
Hybrid Products, Farmingdale, USA Tel: (516) 293 8686  
Fax: (516) 293 0061  
GEC PLESSEY SEMICONDUCTORS  
.O. box 660017 1500 Green Hills Road,  
P
F
F
F
SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872  
SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736  
UNITED KINGDOM & SCANDINAVIA  
Scotts Valley, California 95067–0017,  
United States of America. Tel: (408) 438 2900  
Fax: (408) 438 5576  
Swindon Tel: (0793) 518510 Tx: 444410 Fax: (0793) 518582  
These are supported by Agents and Distributors in major countries world–wide.  
E
GEC Plessey Semiconductors 1993 Publication No. D.S. 3754 Issue No. 1.6 September 1993  
This publication is issued to provide outline information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of  
any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the  
capability, performance or suitability of any product or service. The Company reserves the right to alter without notice the specification, design, price of any product or service.  
Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of  
equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication of data used is up  
to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All  
products and materials are sold and services provided subject to the Company’s conditions of sale, which are available on request.  
12  
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