MT88E41AE [ZARLINK]
CMOS Extended Voltage Calling Number Identification Circuit (ECNIC); CMOS更宽的电压主叫号码识别电路（ ECNIC ）
| 型号： | MT88E41AE |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | CMOS Extended Voltage Calling Number Identification Circuit (ECNIC) |
| 文件： | 总16页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MT88E41
CMOS
Extended Voltage Calling Number
Identification Circuit (ECNIC)
Data Sheet
DS5717
Issue 3
February 1998
Features
•
•
•
•
1200 baud BELL 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation
Ordering Information
MT88E41AE 16 Pin Plastic DIP
MT88E41AS 16 Pin SOIC
MT88E41AN 20 Pin SSOP
-40 °C to +85 °C
Compatible with Bellcore GR-30-CORE and SR-
TSV-002476
High input sensitivity: -36dBm minimum FSK
Detection Level
Simple serial 3-wire data interface eliminating the
need for a UART
Description
•
•
•
•
•
•
Power down mode
The MT88E41 Extended Voltage Calling Number
Identification Circuit (ECNIC) is a CMOS integrated
circuit providing an interface to various calling line
information delivery services that utilize 1200 baud
BELL 202 or CCITT V.23 FSK voiceband data
transmission schemes. The ECNIC receives and
demodulates the signal and outputs data into a simple
3-wire serial interface.
Internal gain adjustable amplifier
Carrier detect status output
Uses 3.579545 MHz crystal
2.7 - 5.5V operation
Low power CMOS technology
Applications
•
Calling Number Delivery (CND), Calling Name
Delivery (CNAM) and Calling Identity on Call
Waiting (CIDCW) features of Bellcore CLASSSM
service
Typically, the FSK modulated data containing
information on the calling line is sent before alerting the
called party or during the silent interval between the first
and second ring using either CCITT V.23
recommendations or Bell 202 specifications.
•
•
•
•
•
•
Feature phones
Phone sets, adjunct boxes
FAX machines
The ECNIC accepts and demodulates both CCITT V.23
and BELL 202 signals. Along with serial data and clock,
the ECNIC provides a data ready signal to indicate the
reception of every 8-bit character sent from the Central
Telephone answering machines
Database query systems
Battery powered applications
GS
DATA
Receive
Bandpass
Filter
Data and Timing
IN-
-
DR
FSK
Demodulator
Recovery
+
IN+
DCLK
CAP
VRef
Bias
Generator
Carrier
Detector
CD
to other
circuits
Clock
Generator
VSS VDD IC1 IC2
PWDN
OSC1 OSC2
Figure 1 - Functional Block Diagram
CLASSSM is a service mark of Bellcore
SEMICMF.019
1
MT88E41
Data Sheet
Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as
is, depending on the application.
16
15
14
13
12
11
10
9
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
VDD
IC2
IC1
PWDN
CD
DR
DATA
DCLK
IN+
IN-
GS
VRef
CAP
NC
OSC1
NC
VDD
IC2
NC
NC
IC1
PWDN
CD
DR
DATA
DCLK
OSC2
VSS
9
10
16 PIN PLASTIC DIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description Table
Pin #
20
Name
Description
16
1
2
3
1
2
3
IN+ Non-inverting Op-Amp (Input).
IN- Inverting Op-Amp (Input).
GS Gain Select (Output). Gives access to op-amp output for connection of feedback
resistor.
4
4
VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp
inputs.
5
6
5
7
CAP Capacitor. Connect a 0.1mF capacitor to VSS.
OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an
external clocking source.
7
9
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external
clock, this pin should be left open.
8
9
10
11
VSS Power supply ground.
DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz
(3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit
start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each
DCLK pulse coincides with the middle of the data bits output at the DATA pin. No
DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to
clock the eight data bits from the 10 bit data word into a serial-to-parallel converter.
10
11
12
12
13
14
DATA Data (Output). Serial data output corresponding to the FSK input and switching at
the input baud rate. Mark frequency at the input corresponds to a logic high, while
space frequency corresponds to a logic low at the DATA output. With no FSK
input, DATA is at logic high. This output stays high until CD has become active.
DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse
of each word. This can be used to identify the data (8-bit word) boundary on the
serial output stream. Typically, DR is used to latch the eight data bits from the
serial-to-parallel converter into a microcontroller.
CD Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been
present for a specified time on the line. A time hysteresis is provided to allow for
momentary discontinuity of carrier.
SEMICMF.019
2
Data Sheet
MT88E41
Pin Description Table (continued)
Pin #
Name
Description
16
20
13
15
PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device
including the input op-amp and the oscillator.
14
15
16
16
19
20
IC1 Internal Connection 1. Connect to VSS.
IC2 Internal Connection 2. Internally connected, leave open circuit.
VDD Positive power supply voltage.
6, 8, 17, 18 NC No Connection.
SEMICMF.019
3
MT88E41
Data Sheet
1.0
Functional Description
The MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a device compatible with the
Bellcore proposal (GR-30-CORE) on generic requirements for transmitting asynchronous voiceband data to
Customer Premises Equipment (CPE) from a serving Stored Program Controlled Switching System (SPCS) or a
Central Office (CO). This data transmission technique is applicable in a variety of services like Calling Number
Delivery (CND), Calling Name Delivery (CNAM) or Calling Identity Delivery on Call Waiting (CIDCW) as specified in
Custom Local Area Signalling Service (CLASSSM) calling information delivery features by Bellcore.
With CND, CNAM and CIDCW service, the called subscriber has the capability to display or to store the information
on the calling party which is sent by the CO and received by the ECNIC.
In the CND service, information about a calling party is embedded in the silent interval between the first and second
ring. During this period, the ECNIC receives and demodulates the 1200 baud FSK signal (compatible with Bell-202
specification) and outputs data into a 3-wire serial interface.
In the CIDCW service, information about a second calling party is sent to the subscriber, (while the subscriber is
engaged in another call). During this period, the ECNIC receives and demodulates the FSK signal as in the CND
case.
The ECNIC is designed to provide the data transmission interface required for the above service at the called
subscriber location either in the on-hook case as in CND, or the off-hook case, as in CIDCW. The functional
block diagram of the ECNIC is shown in Figure 1. Note however, for CIDCW applications, a separate CAS (CPE
Alerting Signal) detector is required.
R1
R4
IN+
IN-
C1
C2
R5
GS
R2
R3
V
Ref
MT88E41
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kW
R2 = 60kW, R3 = 37.5 kW
R3 = (R2R5) / (R2 + R5)
INPUT IMPEDANCE
VOLTAGE GAIN
2
2
(A diff) = R5/R1
R1 + (1/wC)
(Z diff) = 2
IN
V
Figure 3 - Differential Input Configuration
SEMICMF.019
4
Data Sheet
MT88E41
IN+
IN-
R
C
IN
GS
R
F
V
Ref
MT88E41
VOLTAGE GAIN
(A ) = R / R
IN
V
F
Figure 4 - Single-Ended Input Configuration
In Europe, Caller ID and CIDCW services are being proposed. These schemes may be different from their North
American counterparts. In most cases, 1200 baud CCITT V.23 FSK is used instead of Bell 202. Because the ECNIC
can also demodulate 1200 baud CCITT V.23 with the same performance, it is suitable for these applications.
Although the main application of the ECNIC is to support CND and CIDCW service, it may also be used in any
application where 1200 baud Bell 202 and/or CCITT V.23 FSK data reception is required.
1.1
Input Configuration
The input arrangement of the MT88E41 provides an operational amplifier, as well as a bias source (VRef) which is
used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS)
for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 4.
Figure 3 shows the necessary connections for a differential input configuration.
1.2
User Interface
The ECNIC provides a powerful 3-pin interface which can reduce the external hardware and software requirements.
The ECNIC receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin. For each
received stop bit start bit sequence, the ECNIC outputs a fixed frequency clock string of 8 pulses at the DCLK pin.
Each clock rising edge corresponds to the centre of each DATA bit cell (providing the incoming baud rate matches
the DCLK rate). DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data
into a peripheral device such as a serial to parallel shift register or a micro-controller. The ECNIC also outputs an
end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word
sent from the Central Office. This output is typically used to interrupt a micro-controller. The three outputs together,
eliminate the need for a UART (Universal Asynchronous Receiver Transmitter) or the high software overhead of
performing the UART function (asynchronous serial data reception).
Note that the 3-pin interface may also output data generated by voice since these frequencies are in the input
frequency detection band of the device. The user may choose to ignore these outputs when FSK data is not
expected, or force the ECNIC into its powerdown mode.
1.3
Power Down Mode
For applications requiring reduced power consumption, the ECNIC can be forced into power down when it is not
needed to receive FSK data. This is done by pulling the PWDN pin high. In powerdown mode, the crystal oscillator,
op-amp and internal circuitry are all disabled and the ECNIC will not react to the input signal. DATA and DCLK are
at logic high, and DR and CD are at high impedance or at logic high when pulled up with resistors.The ECNIC can
be awakened for reception of the FSK signal by pulling the PWDN pin to ground (see Figure 9).
SEMICMF.019
5
MT88E41
Data Sheet
1.4
Carrier Detect
The presence of the FSK signal is indicated by a logic low at the carrier detect (CD) output. This output has built in
hysteresis to prevent toggling when the received signal is shortly interrupted. Note that the CD output is also
activated by voice since these frequencies are in the input frequency detection band of the device. The user may
choose to ignore this output when FSK data is not expected, or force the ECNIC into its powerdown mode.
MT88E41
MT88E41
MT88E41
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
to the
next MT88E41
3.579545 MHz
Figure 5 - Common Crystal Connection
1.5
Crystal Oscillator
The ECNIC uses a crystal oscillator as the master timing source for filters and the FSK demodulator. The crystal
specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode:
3.579545 MHz
±0.1%(-40°C+85°C)
Parallel
Load capacitance:
18 pF
150 ohms
2 mW
Maximum series resistance:
Maximum drive level (mW):
e.g. CTS MP036S
A number of MT88E41 devices can be connected as shown in Figure 5 such that only one crystal is required. The
connection between OSC2 and OSC1 can be D.C. coupled as shown, or A.C. coupled using 30pF capacitors.
Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs
left unconnected.
1.6
VRef and CAP Inputs
VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1mF
capacitor is required between CAP and VSS to suppress noise on VRef.
SEMICMF.019
6
Data Sheet
MT88E41
2.0
Applications
The circuit shown in Figure 6 illustrates the use of the MT88E41 device in a typical FSK receiver system. Bellcore
Special Report SR-TSV-002476 specifies that the FSK receiver should be able to receive FSK signal levels as
follows:
Received Signal Level at 1200Hz:
-32dBm to -12dBm
Received Signal Level at 2200Hz:
-36dBm to -12dBm
This condition can be attained by choosing suitable values of R1 and R2. The MT88E41 configured in a unity gain
mode as shown in Fig. 6 meets the above level requirements.
For applications requiring detection of lower FSK signal level, the input op amp may be configured to provide
adequate gain.
VDD
MT88E41
VDD
C1
C3
R4
IN +
R1
R3
IN -
IC2
IC1
GS
R2
PWDN
CD
VRef
CAP
OSC1
OSC2
VSS
To
Controller
DR
X-tal
C2
DATA
DCLK
Notes:
R1, R2 = 100 kW 1%
R3, R4 = 100 kW 10%
C1, C2, C3 = 0.1mF 20%
X-tal = 3.579545 MHz
Figure 6 - Application Circuit (Single-Ended Input)
SEMICMF.019
7
MT88E41
Data Sheet
Absolute Maximum Ratings* - Voltages are with respect to V unless otherwise stated.
SS
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
DC Power Supply Voltage VDD to VSS
Voltage on any pin
VDD
VP
-0.3
-0.3
6
VDD+0.3
±10
V
V
Current at any pin (except VDD and VSS
)
I I/O
TST
PD
mA
°C
Storage Temperature
-65
+150
500
Package Power Dissipation
mW
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated
SS
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
DC Power Supply Voltage
Clock Frequency
VDD
fOSC
Dfc
2.7
5.5
V
MHz
%
3.579545
Tolerance on Clock Frequency
Operating Temperature
±0.1
-40
+85
°C
DC Electrical Characteristics†
Test
Characteristics
Sym
IDDQ
Min
Typ*
Max
Units
Conditions
1
2
3
Standby Supply Current
VDD=2.7V
VDD=5.5V
PWDN=VDD
S
U
P
P
L
7
15
14
28
mA
mA
Operating Supply Current
IDD
PWDN=VSS
VDD=2.7V
VDD=5.5V
1
3
2
5
mA
mA
Y
Low Level Output Voltage
High Level Output Voltage
VOL
VOH
0.4
V
V
IOL=2.5mA
IOH=0.8mA
DATA
DCLK
V
-0.4
DD
DR
CD
4
5
Sink Current
IOL
2.5
mA VOL=0.4V
Schmitt Input High Threshold
Schmitt Input Low Threshold
VT+
VT-
0.48*VDD
0.28*VDD
0.68*VDD
0.48*VDD
V
V
PWDN
VRef
6
7
8
9
Schmitt Hysterisis
Input Current
VHYS
IIN
0.2
V
10
mA
V
V
SS £ VIN £ VDD
Output Voltage
Output Resistance
VRef 0.5VDD - 0.05
RRef
0.5VDD + 0.05
2
No Load
kW
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
* Typical figures are at 25°C and are for design aid only.
SEMICMF.019
8
Data Sheet
MT88E41
Electrical Characteristics† - Gain Setting Amplifier
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
VSS £ VIN £ VDD
1
2
3
4
5
6
7
8
9
Input Leakage Current
Input Resistance
IIN
Rin
1
mA
MW
mV
dB
5
Input Offset Voltage
VOS
PSRR
CMRR
AVOL
fC
25
Power Supply Rejection Ratio
Common Mode Rejection
DC Open Loop Voltage Gain
Unity Gain Bandwidth
30
30
30
.2
40
40
32
0.3
1kHz ripple on VDD
VCMmin £ VIN £ VCMmax
dB
dB
MHz
V
-0.5
Output Voltage Swing
VO
0.5
Vpp Load ³ 50kW
DD
Maximum Capacitive Load (GS)
CL
100
pF
kW
V
10 Maximum Resistive Load (GS)
RL
50
V
-1.0
11 Common Mode Range Voltage
VCM
1.0
DD
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FSK Detection
Characteristics
Input Detection Level
Sym
Min
Typ‡
Max
Units
Notes*
1
-36
12.3
-9
275
dBm 1, 2, 3
mV 1, 2, 3
2
3
Input Baud Rate
1188 1200 1212
baud
7
Input Frequency Detection
Bell 202 1 (Mark)
1188 1200 1212
2178 2200 2222
Hz
Hz
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0
1280.5 1300 1319.5
2068.5 2100 2131.5
Hz
Hz
(Space)
4
Input Noise Tolerance 20 log(
SNR
20
dB
2, 3, 4, 5
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
SEMICMF.019
9
MT88E41
Data Sheet
AC Electrical Characteristics† - Timing
Characteristics
Power-up time
Sym
tPU
tPD
tIAL
tIAH
Min
Typ‡
Max
Units
Notes*
1
2
35
50
1000
25
ms
ms
PWDN
OSC1
Power-down time
Input FSK to CD low delay
Input FSK to CD high delay
Hysteresis
100
11
3
ms
ms
ms
bps
ms
ns
CD
4
8
8
5
DATA
6
Rate
1188
1200
1
1212
5
6,12
7
Input FSK to DATA delay
Rise time
tIDD
tR
8
200
200
8
8
9
Fall time
tF
ns
DATA
DCLK
10
11
12
13
14
15
DATA to DCLK delay
DCLK to DATA delay
Frequency
tDCD
tCDD
6
6
416
416
ms
6, 7, 10
ms
6, 7, 10
1200 1202.8 1205
Hz
ms
7
7
7
7
DCLK
High time
tCH
tCL
415
415
415
416
416
416
417
417
417
Low time
ms
DCLK
DR
DCLK to DR delay
tCRD
ms
16
17
18
Rise time
Fall time
Low time
tRR
tFF
tRL
10
ms
ns
ms
9
9
7
DR
200
417
415
416
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1.
dBm=decibels above or below a reference power of 1mW into 600W.
Using unity gain test circuit shown in Figure 6.
Mark and Space frequencies have the same amplitude.
Band limited random noise (200-3200Hz).
Referenced to the minimum input detection level.
FSK input data at 1200 ±12 baud.
2.
3.
4.
5.
6.
7.
OSC1 at 3.579545 MHz ±0.2%.
8.
10k to V , 50pF to V
SS
SS.
9.
10k to V , 50pF to V
.
SS
DD
10.
11.
12.
Function of signal condition.
The device will stop functioning within this time, but more time may be required to reach I
For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
.
DDQ
SEMICMF.019
10
Data Sheet
MT88E41
t
t
CDD
DCD
t
F
t
R
DATA
DCLK
t
t
CH
CL
t
F
t
R
Figure 7 - DATA and DCLK Output Timing
t
t
RR
FF
DR
t
RL
Figure 8 - DR Output Timing
SEMICMF.019
11
MT88E41
Data Sheet
checksum
channel seizure
Mark state
2 sec
TIP/RING
PWDN
Input FSK
Data
Second
Ringing
First Ringing
500ms
(min)
200ms
(min)
t
PU
t
PD
OSC2
CD *
t
t
IAH
IAL
DATA
High (Input Idle)
High (Input Idle)
DCLK
DR *
* with external pull-up resistor
Figure 9 - Input and Output Timing (Bellcore CND Service)
SEMICMF.019
12
Data Sheet
MT88E41
start
stop
start
stop
start
stop
TIP/RING
DATA
b7
b6
b6
b0 b1 b2
b0 b1 b2 b3 b4 b5
b7
b6
b0 b1 b2 b3 b4 b5
b7
b6
1
0
1
0
1
0
t
IDD
start
start
start
b0 b1 b2
b7
b0 b1 b2 b3 b4 b5
b7
b0 b1 b2 b3 b4 b5
b7
stop
stop
stop
DCLK
DR *
t
CRD
* with external pull-up resistor
Figure 10 - Serial Data Interface Timing
SEMICMF.019
13
MT88E41
Data Sheet
SEMICMF.019
14
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