MT8888CSR [ZARLINK]

Integrated DTMF Transceiver with Intel Micro Interface; 集成双音多频收发器与英特尔微型接口


型号：	MT8888CSR
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	Integrated DTMF Transceiver with Intel Micro Interface 集成双音多频收发器与英特尔微型接口电信集成电路电信信令电路电信电路光电二极管
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中文：	中文翻译
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MT8888C

Integrated DTMF Transceiver

with Intel Micro Interface

Data Sheet

September 2005

Features

Ordering Information

•

Central office quality DTMF transmitter/receiver

MT8888CE

MT8888CS

MT8888CN

MT8888CP

MT8888CE1

MT8888CS1

MT8888CN1

MT8888CP1

MT8888CPR

MT8888CSR

20 Pin PDIP

20 Pin SOIC

24 Pin SSOP

28 Pin PLCC

20 Pin PDIP*

20 Pin SOIC*

Tubes

Low power consumption

High speed Intel micro interface

Adjustable guard time

Automatic tone burst mode

Call progress tone detection to -30 dBm

24 Pin SSOP* Tubes

28 Pin PLCC* Tubes

28 Pin PLCC

20 Pin SOIC

MT8888CSR1 20 Pin SOIC*

Tape & Reel

Applications

MT8888CPR1 28 Pin PLCC* Tape & Reel

*Pb Free Matte Tin

•

Credit card systems

Paging systems

-40°C to +85°C

The receiver section is based upon the industry

standard MT8870 DTMF receiver while the transmitter

utilizes a switched capacitor D/A converter for low

distortion, high accuracy DTMF signalling. Internal

counters provide a burst mode such that tone bursts

can be transmitted with precise timing. A call progress

filter can be selected allowing a microprocessor to

analyze call progress tones.

Repeater systems/mobile radio

Interconnect dialers

Personal computers

Description

The MT8888C is a monolithic DTMF transceiver with

call progress filter. It is fabricated in CMOS technology

offering low power consumption and high reliability.

The MT8888C utilizes an Intel micro interface, which

allows the device to be connected to a number of

popular microcontrollers with minimal external logic.

Data

Row and

D/A

Transmit Data

Bus

∑

Column

TONE

Converters

Buffer

Counters

Status

Interrupt

Logic

Tone Burst

Gating Cct.

Control

Logic

IRQ/CP

Control

IN+

IN-

Dial

Tone

Filter

High Group

Filter

Digital

Algorithm

and Code

Converter

Control

I/O

Control

Low Group

Filter

OSC1

OSC2

Oscillator

RS0

Circuit

Control

Logic

Receive Data

Steering

Logic

Bias

Circuit

V_DDV_RefV_SS

ESt

St/GT

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT8888C

Data Sheet

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

VDD

St/GT

ESt

IRQ/CP

IN+

IN-

VRef

VSS

OSC1

OSC2

TONE

VDD

St/GT

ESt

IRQ/CP

•

VRef

VSS

OSC1

OSC2

RS0

20 PIN PLASTIC DIP/SOIC

24 PIN SSOP

28 PIN PLCC

Figure 2 - Pin Connections

Pin Description

Pin #

Name

IN+ Non-inverting op-amp input.

Description

IN-

Inverting op-amp input.

Gain Select. Gives access to output of front end differential amplifier for

connection of feedback resistor.

V_RefReference Voltage output (V_DD/2).

V_SSGround (0V ).

OSC1 DTMF clock/oscillator input. Connect a 4.7 MΩ resistor to VSS if crystal oscillator is

used.

OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2

completes the internal oscillator circuit. Leave open circuit when OSC1 is driven

externally.

TONE Output from internal DTMF transmitter.

WR Write microprocessor input. TTL compatible.

Chip Select input. Active Low. This signal must be qualified externally by address

latch enable (ALE) signal, see Figure 14.

RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.

RD Read microprocessor input. TTL compatible.

IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this

output goes low when a valid DTMF tone burst has been transmitted or received.

In call progress mode, this pin will output a rectangular signal representative of the

input signal applied at the input op-amp. The input signal must be within the

bandwidth limits of the call progress filter, see Figure 8.

14-17 18-21 19-22 D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.

TTL compatible.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

Pin Description (continued)

Pin #

Name

Description

ESt

Early Steering output. Presents a logic high once the digital algorithm has

detected a valid tone pair (signal condition). Any momentary loss of signal

condition will cause ESt to return to a logic low.

St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V_TSt

detected at St causes the device to register the detected tone pair and update the

output latch. A voltage less than V_TStfrees the device to accept a new tone pair.

The GT output acts to reset the external steering time-constant; its state is a

function of ESt and the voltage on St.

V_DDPositive power supply (5 V typical).

8, 9, 3,5,10,

16,17 11,16,

23,25

No Connection.

1.0 Functional Description

The MT8888C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain

setting amplifier and a DTMF generator which employs a burst counter to synthesize precise tone bursts and

pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.

The Intel micro interface allows microcontrollers, such as the 8080, 80C31/51 and 8085, to access the MT8888C

internal registers.

2.0 Input Configuration

The input arrangement of the MT8888C provides a differential-input operational amplifier as well as a bias source

(V_Ref), which is used to bias the inputs at V_DD/2. Provision is made for connection of a feedback resistor to the op-

amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in

Figure 3. Figure 4 shows the necessary connections for a differential input configuration.

3.0 Receiver Section

Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order

switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies

(see Table 1). These filters incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter

output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.

Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of

unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the

incoming DTMF signals.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

IN+

IN-

R_IN

R_F

V_Ref

MT8888C

VOLTAGE GAIN

(A_V) = R_F/ R_IN

Figure 3 - Single-Ended Input Configuration

IN+

IN-

V_Ref

MT8888C

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF

R1 = R4 = R5 = 100 kΩ

R2 = 60kΩ, R3 = 37.5 kΩ

R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

(A_Vdiff) - R5/R1

INPUT IMPEDANCE

(Z_INdiff) = 2 R1²+ (1/ωC)²

Figure 4 - Differential Input Configuration

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

F_LOW

F_HIGH

DIGIT

D₃

D₂

D₁

D₀

697

770

852

941

697

770

852

941

1209

1336

1477

1209

1336

1477

1209

1336

1477

1336

1209

1477

1633

Table 1 - Functional Encode/Decode Table

Note: 0= LOGIC LOW, 1= LOGIC HIGH

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the

incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm

protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency

deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the

detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry

specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition

will cause ESt to assume an inactive state.

4.0 Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character

recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt

causes v_c(see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt

remains high) for the validation period (t_GTP), v_creaches the threshold (V_TSt) of the steering logic to register the

tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT

output is activated and drives v_cto V_DD. GT continues to drive high as long as ESt remains high. Finally, after a

short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received

tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate

bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering

flag is active.

The contents of the output latch are updated on an active delayed steering transition. This data is presented to the

four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to

validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together

with the capability of selecting the steering time constants externally, allows the designer to tailor performance to

meet a wide variety of system requirements.

V_DD

MT8888C

V_DD

St/GT

ESt

t_GTA= (R1C1) In (V_DD/ V_TSt

)

t_GTP= (R1C1) In [V_DD/ (V_DD-V_TSt)]

Figure 5 - Basic Steering Circuit

5.0 Guard Time Adjustment

The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen

according to the following inequalities (see Figure 7):

_REC≥ t_DPmax+t_GTPmax- t_DAmin

_REC≤ t_DPmin+t_GTPmin- t_DAmax

_ID≥ t_DAmax+t_GTAmax- t_DPmin

_DO≤ t_DAmin+t_GTAmin- t_DPmax

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

_GTP= (R_PC1) In [V_DD/ (V_DD-V_TSt)]

_GTA= (R1C1) In (V_DD/V_TSt

_P= (R1R2) / (R1 + R2)

)

V_DD

St/GT

ESt

a) decreasing tGTP; (tGTP < tGTA)

t_GTP= (R1C1) In [V_DD/ (V_DD-V_TSt)]

t_GTA= (R_pC1) In (V_DD/V_TSt

R_P= (R1R2) / (R1 + R2)

)

V_DD

St/GT

b) decreasing tGTA; (tGTP > tGTA)

ESt

Figure 6 - Guard Time Adjustment

The value of t_DPis a device parameter (see AC Electrical Characteristics) and t_RECis the minimum signal duration

to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be

selected by the designer. Different steering arrangements may be used to select independent tone present (t_GTP

)

and tone absent (t_GTA) guard times. This may be necessary to meet system specifications which place both accept

and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor

system parameters such as talk off and noise immunity.

Increasing t_RECimproves talk-off performance since it reduces the probability that tones simulated by speech will

maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t_RECwith a long t_DO

would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs

are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in

Figure 7 with a description of the events in Figure 9.

6.0 Call Progress Filter

A call progress mode, using the MT8888C, can be selected allowing the detection of various tones, which identify

the progress of a telephone call on the network. The call progress tone input and DTMF input are common,

however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be

detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call

progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are

hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained

from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of

the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and

consequently the IRQ/CP pin will remain low.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

EVENTS

t_REC

t_DO

t_ID

t_REC

TONE

#n + 1

TONE

#n + 1

TONE #n

V_in

t_DA

t_DP

ESt

t_GTP

t_GTA

V_TSt

St/GT

t_PStRX

RX₀-RX₃

DECODED TONE # (n-1)

# (n + 1)

# n

t_PStb3

Read

Status

IRQ/CP

Figure 7 - Receiver Timing Diagram

LEVEL

(dBm)

-25

250

500

750

FREQUENCY (Hz)

= Reject

= May Accept

= Accept

Figure 8 - Call Progress Response

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

EXPLANATION OF EVENTS

TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.

TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.

END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS

V_in

DTMF COMPOSITE INPUT SIGNAL.

ESt

St/GT

EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.

STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.

RX₀-RX₃4-BIT DECODED DATA IN RECEIVE DATA REGISTER

DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A

VALID DTMF SIGNAL.

INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS

IRQ/CP

INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS READ.

t_REC

t_ID

t_DO

t_DP

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.

MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.

MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.

TIME TO DETECT VALID FREQUENCIES PRESENT.

t_DA

TIME TO DETECT VALID FREQUENCIES ABSENT.

t_GTP

t_GTA

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

Figure 9 - Description of Timing Events

7.0 DTMF Generator

The DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs

with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The

sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable

dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a

DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the

encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the

receiver output code. The individual tones which are generated (f_LOWand f_HIGH) are referred to as Low Group and

High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 94 Hz. The high group

frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB

to compensate for high group attenuation on long loops.

The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length

of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched

and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time

segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate

count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time

segments is fixed at 32, however, by varying the segment length as described above the frequency can also be

varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and

highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which

are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other

DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst

accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can

be seen from Figure 8 that the distortion products are very low in amplitude.

Scaling Information

10 dB/Div

Start Frequency = 0 Hz

Stop Frequency = 3400 Hz

Marker Frequency = 697 Hz and

1209 Hz

Figure 10 - Spectrum Plot

8.0 Burst Mode

In certain telephony applications it is required that DTMF signals being generated are of a specific duration

determined either by the particular application or by any one of the exchange transmitter specifications currently

existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is

capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms,

which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the

appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing

described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)

is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have

been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard

burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses

when the burst mode is disabled by enabling and disabling the transmitter.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

9.0 Single Tone Generation

A single tone mode is available whereby individual tones from the low group or high group can be generated. This

mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion

measurements. Refer to Control Register B description for details.

OUTPUT FREQUENCY (Hz)

ACTIVE

%ERROR

INPUT

SPECIFIED

ACTUAL

697

770

699.1

766.2

+0.30

-0.49

-0.54

+0.74

+0.57

-0.32

-0.35

+0.73

852

847.4

941

948.0

1209

1336

1477

1633

1215.9

1331.7

1471.9

1645.0

Table 2 - Actual Frequencies Versus Standard Requirements

10.0 Distortion Calculations

The MT8888C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The

internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic

components and intermodulation products. The total harmonic distortion for a single tone can be calculated using

Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental

frequency expressed as a percentage.

V²_2f+ V²_3f+ V²_4f+ .... V²

THD (%) = 100

V_fundamental

Figure 11 - Equation 1. THD (%) For a Single Tone

The Fourier components of the tone output correspond to V_2f.... V_nfas measured on the output waveform. The total

harmonic distortion for a dual tone can be calculated using Equation 2. V_Land V_Hcorrespond to the low group

amplitude and high group amplitude, respectively and V²_IMDis the sum of all the intermodulation components. The

internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as

shown in Figure 10.

V²_2L+ V²_3L+ .... V²_nL+ V²

V²_3H+ .. V²_nH+ V²

IMD

THD (%) = 100

V²_L+ V²

Figure 12 - Equation 2. THD (%) For a Dual Tone

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

11.0 DTMF Clock Circuit

The internal clock circuit is completed with the addition of a standard television color burst crystal. The crystal

specification is as follows:

Frequency:

3.579545 MHz

±0.1%

Frequency Tolerance:

Resonance Mode:

Load Capacitance:

Parallel

18pF

Maximum Series Resistance: 150 ohms

Maximum Drive Level:

e.g. CTS Knights MP036S

2mW

Toyocom

TQC-203-A-9S

A number of MT8888C devices can be connected as shown in Figure 13 such that only one crystal is required.

Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left

unconnected.

MT8888C

OSC1 OSC2

3.579545 MHz

Figure 13 - Common Crystal Connection

12.0 Microprocessor Interface

The MT8888C incorporates an Intel microprocessor interface which is compatible with fast versions (16 MHz) of the

80C51. No wait cycles need to be inserted.

Figure 19 and Figure 20 are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By

NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated.

Figure 14 summarizes the connection of these Intel processors to the MT8888C transceiver.

The microprocessor interface provides access to five internal registers. The read-only Receive Data Register

contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data

accomplished with two control registers (see Table 6 and Table 7), CRA and CRB, which have the same address. A

write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation

to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The

read-only status register indicates the current transceiver state (see Table 8).

A software reset must be included at the beginning of all programs to initialize the control registers upon power-up

or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers.

The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when

the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a

squarewave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external

pull-up resistor (see Figure 15).

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

RS0

FUNCTION

Write to Transmit Data Register

Read from Receive Data Register

Write to Control Register

Read from Status Register

Table 3 - Internal Register Functions

RSEL

IRQ

CP/DTMF

TOUT

Table 4 - CRA Bit Positions

C/R

S/D

TEST

BURST

ENABLE

Table 5 - CRB Bit Positions

BIT

NAME

DESCRIPTION

TOUT

Tone Output Control. A logic high enables the tone output; a logic low turns the tone output

off. This bit controls all transmit tone functions.

CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;

a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and

transmitting DTMF signals. In CP mode a rectangular wave representation of the received

tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control

specified in the AC Electrical Characteristics for Call Progress.

Note: DTMF signals cannot be detected when CP mode is selected.

IRQ

Interrupt Enable. A logic high enables the interrupt function; a logic low deactivates the

interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,

b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been

received for a valid guard time duration, or 2) the transmitter is ready for more data (burst

mode only).

RSEL

will be directed to control register A.

Table 6 - Control Register A Description

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

BIT

NAME

DESCRIPTION

BURST

Burst Mode Select. A logic high deactivates burst mode; a logic low enables burst mode.

When activated, the digital code representing a DTMF signal (see Table 1) can be written

to the transmit register, which will result in a transmit DTMF tone burst and pause of equal

durations (typically 51 msec). Following the pause, the status register will be updated (b1 -

Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been

enabled.

When CP mode (control register A, b1) is enabled the normal tone burst and pause

durations are extended from a typical duration of 51 msec to 102 msec.

When BURST is high (deactivated) the transmit tone burst duration is determined by the

TOUT bit (control register A, b0).

TEST

S/D

Test Mode Control. A logic high enables the test mode; a logic low deactivates the test

mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the

signal present on the IRQ/CP pin will be analogous to the state of the DELAYED

STEERING bit of the status register (see Figure 7, signal b3).

Single or Dual Tone Generation. A logic high selects the single tone output; a logic low

selects the dual tone (DTMF) output. The single tone generation function requires further

selection of either the row or column tones (low or high group) through the C/R bit (control

C/R

Column or Row Tone Select. A logic high selects a column tone output; a logic low selects

a row tone output. This function is used in conjunction with the S/D bit (control register B,

b2).

Table 7 - Control Register B Description

BIT

NAME

STATUS FLAG SET

STATUS FLAG CLEARED

IRQ

Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

Interrupt is inactive. Cleared after

Status Register is read.

TRANSMIT DATA

(BURST MODE ONLY)

Pause duration has terminated

and transmitter is ready for new

data.

Cleared after Status Register is

read or when in non-burst mode.

RECEIVE DATA REGISTER

FULL

Valid data is in the Receive Data

Cleared after Status Register is

read.

Set upon the valid detection of

the absence of a DTMF signal.

Cleared upon the detection of a

valid DTMF signal.

DELAYED STEERING

Table 8 - Status Register Description

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

8031/8051

8080/8085

MT8888C

A8-A15

RS0

D0-D3

Figure 14 - MT8888C Interface Connections for Various Intel Micros

V_DD

MT8880C

VDD

St/GT

ESt

IN+

DTMF/CP

INPUT

IN-

VRef

VSS

OSC1

OSC2

TONE

X-tal

R_L

To µP

or µC

IRQ/CP

DTMF

OUTPUT

RS0

Notes:

R1, R2 = 100 kΩ 1%

R3 = 374 kΩ 1%

R4 = 3.3 kΩ 10%

R5 = 4.7 MΩ 10%

R_L= 10 k Ω (min.)

* Microprocessor based systems can inject undesirable noise into the supply rails.

The performance of the MT8888C can be optimized by keeping

noise on the supply rails to a minimum. The decoupling capacitor (C3) should be

connected close to the device and ground loops should be avoided.

C1 = 100 nF 5%

C2 = 100 nF 5%

C3 = 100 nF 10%*

C4 = 10 nF 10%

X-tal = 3.579545 MHz

Figure 15 - Application Circuit (Single-Ended Input)

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

5.0 VDC

MMD6150 (or

equivalent)

2.4 kΩ

3 kΩ

TEST POINT

130 pF

24 kΩ

100 pF

MMD7000 (or

equivalent)

Test load for D0-D3 pins

Test load for IRQ/CP pin

Figure 16 - Test Circuits

INITIALIZATION PROCEDURE

A software reset must be included at the beginning of all programs to initialize the control registers after power up.The

initialization procedure should be implemented 100ms after power up.

Description:

Control

Data

RS0

1) Read Status Register

2) Write to Control Register

3) Write to Control Register

4) Write to Control Register

5) Write to Control Register

6) Read Status Register

TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence:

RS0

1) Write to Control Register A

(tone out, DTMF, IRQ, Select Control Register B)

2) Write to Control Register B

(burst mode)

3) Write to Transmit Data Register

(send a digit 7)

4) Wait for an interrupt or poll Status Register

5) Read the Status Register

-if bit 1 is set, the Tx is ready for the next tone, in which case...

Write to Transmit Register

(send a digit 5)

-if bit 2 is set, a DTMF tone has been received, in which case....

Read the Receive Data Register

-if both bits are set...

Read the Receive Data Register

Write to Transmit Data Register

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE

DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO

200 ms (± 4 ms).

Figure 17 - Application Notes

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

Absolute Maximum Ratings*

Parameter

Power supply voltage V_DD-V_SS

Symbol

Min.

Max.

Units

V_DD

V_I

Voltage on any pin

V_SS-0.3

-65

V_DD+0.3

Current at any pin (Except V_{DD and}V_SS

)

°C

Storage temperature

T_ST

P_D

+150

1000

Package power dissipation

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (V_SS) unless otherwise stated.

Parameter

Sym.

Min.

Typ.^‡

Max.

Units

Test Conditions

Positive power supply

Operating temperature

Crystal clock frequency

V_DD

T_O

4.75

-40

5.00

5.25

+85

°C

f_CLK

3.575965 3.579545 3.583124

MHz

‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics - ^†- V_SS=0 V.

Characteristics

Sym.

Min.

Typ.^‡Max. Units

Test Conditions

Operating supply voltage

Operating supply current

Power consumption

V_DD

I_DD

4.75

5.0

7.0

5.25

P_C

57.8

High level input voltage

(OSC1)

V_IHO

3.5

2.2

Note 9*

Low level input voltage

(OSC1)

V_ILO

V_TSt

V_OLO

V_OHO

1.5

2.5

0.1

Note 9*

Steering threshold voltage

2.3

V_DD=5V

Low level output voltage

(OSC2)

No load

Note 9*

High level output voltage

(OSC2)

No load

Note 9*

4.9

2.4

Output leakage current

(IRQ)

I_OZ

V_Ref

R_OR

V_IL

µA

V_OH=2.4 V

V_Refoutput voltage

2.5

1.3

2.6

No load, V_DD=5V

_Refoutput resistance

kΩ

Low level input voltage

High level input voltage

Input leakage current

0.8

V_IH

I_IZ

2.0

µA

V_IN=V_SSto V_DD

Source current

Sink current

I_OH

I_OL

-1.4

2.0

-6.6

4.0

V_OH=2.4V

V_OL=0.4V

Data

Bus

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

DC Electrical Characteristics (continued) - ^†- V_SS=0 V. (continued)

Characteristics

Source current

Sym.

Min.

Typ.^‡Max. Units

Test Conditions

V_OH=4.6V

ESt

and

St/Gt

I_OH

I_OL

-0.5

-3.0

Sink current

V_OL=0.4V

I_OL

IRQ/

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25 °C, V_DD=5V and for design aid only: not guaranteed and not subject to production testing.

* See “Notes” following AC Electrical Characteristics Tables.

Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated,

VSS= 0V.

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Input leakage current

Input resistance

I_IN

R_IN

100

MΩ

_SS≤ V_IN≤ V_DD

Input offset voltage

V_OS

Power supply rejection

Common mode rejection

DC open loop voltage gain

Unity gain bandwidth

Output voltage swing

PSRR

CMRR

A_VOL

1 kHz

C_L= 20p

1.0

0.5

MHz

V_O

V_DD-0.5

100

R_L≥ 100 kΩ to V_SS

Allowable capacitive load (GS)

C_L

R_L

kΩ

PM>40°

V_O= 4Vpp

R_L= 50kΩ

10 Allowable resistive load (GS)

11 Common mode range

V_CM

1.0

V_DD-1.0

Figures are for design aid only: not guaranteed and not subject to production testing.

Characteristics are over recommended operating conditions unless otherwise stated.

MT8888C AC Electrical Characteristics ^†- Voltages are with respect to ground (V_SS) unless otherwise stated.

Characteristics

Sym.

Min.

Typ.^‡Max.

Units

Notes*

1,2,3,5,6

Valid input signal levels

(each tone of composite

signal)

-29

dBm

27.5

869

mV_RMS

† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 15.

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

AC Electrical Characteristics ^†- Voltages are with respect to ground (V_SS) unless otherwise stated. f_C=3.579545 MHz

Characteristics

Sym.

Min.

Typ.^‡Max.

Units

Notes*

Positive twist accept

Negative twist accept

Freq. deviation accept

Freq. deviation reject

Third tone tolerance

Noise tolerance

2,3,6,9

2,3,5

±1.5%± 2Hz

±3.5%

2,3,5

-16

-12

2,3,4,5,9,10

2,3,4,5,7,9,10

2,3,4,5,8,9

Dial tone tolerance

† Characteristics are over recommended operating conditions unless otherwise stated.

‡ Typical figures are at 25°C, V_DD= 5 V, and for design aid only: not guaranteed and not subject to production testing.

* *See “Notes” following AC Electrical Characteristics Tables.

AC Electrical Characteristics^†- Call Progress - Voltages are with respect to ground (V_SS), unless otherwise stated.

Characteristics

Accept Bandwidth

Sym.

Min.

Typ.^‡Max. Units

Conditions

@ -25 dBm,

f_A

310

500

Note 9

Lower freq. (REJECT)

Upper freq. (REJECT)

f_LR

f_HR

290

540

@ -25 dBm

Call progress tone detect level (total

power)

-30

dBm

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, V_DD=5 V, and for design aid only: not guaranteed and not subject to production testing

AC Electrical Characteristics ^†- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual values are

user selectable as per Figures 5, 6 and 7.

Characteristics

Sym.

Min.

Typ.^‡Max. Units

Conditions

Minimum tone accept duration

Maximum tone reject duration

Minimum interdigit pause duration

Maximum tone drop-out duration

t_REC

t_ID

t_DO

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, V_DD=5 V, and for design aid only: not guaranteed and not subject to production testing

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

AC Electrical Characteristics^†- Voltages are with respect to ground (V_SS), unless otherwise stated.

Characteristics

Sym.

Min.

Typ.^‡

Max.

Units

Conditions

Tone present detect time

Tone absent detect time

Delay St to b3

t_DP

t_DA

t_PStb3

t_PStRX

ms Note 11

0.5

8.5

µs

See Figure 7

Delay St to RX₀-RX₃

Tone burst duration

t_BST

t_PS

t_BSTE

t_PSE

ms DTMF mode

ms Call Progress mode

dBm R_L=10kΩ

Tone pause duration

Tone burst duration (extended)

Tone pause duration (extended)

High group output level

Low group output level

Pre-emphasis

100

-6.1

-8.1

104

-2.1

-4.1

V_HOUT

V_LOUT

dB_P

dBm R_L=10kΩ

R_L=10kΩ

Output distortion (Single Tone)

THD

-35

25 kHz Bandwidth

R_L=10kΩ

Frequency deviation

f_D

R_LT

±0.7

±1.5

f_C=3.579545 MHz

Output load resistance

Crystal/clock frequency

Clock input rise and fall time

Clock input duty cycle

Capacitive load (OSC2)

kΩ

f_C

3.5759 3.5795 3.5831 MHz

t_CLRF

DC_CL

C_LO

110

Ext. clock

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics^†- MPU Interface - Voltages are with respect to ground (V_SS), unless otherwise stated.

Characteristics

Sym.

Min.

Typ.^‡Max.

Units

Conditions

Figure 18

RD/WR clock frequency

RD/WR cycle period

f_CYC

t_CYC

t_{R, F}

t_AS

t_AH

4.0

250

MHz

Figure 18

RD/WR rise and fall time

Address setup time

Figure 18

Figures 19 & 20

Figures 18, 19 & 20

Figures 19 & 20

Address hold time

Data hold time (read)

RD to valid data delay (read)

RD, WR pulse width low

RD, WR pulse width high

t_DHR

t_DDR

t_PWL

t_PWH

t_DSW

t_DHW

C_IN

100

150

100

10 Data setup time (write)

11 Data hold time (write)

12 Input Capacitance (data bus)

Zarlink Semiconductor Inc.

MT8888C

Data Sheet

AC Electrical Characteristics^†- MPU Interface (continued)- Voltages are with respect to ground (V_SS), unless otherwise

Characteristics

Sym.

Min.

Typ.^‡Max.

Units

Conditions

13 Output Capacitance (IRQ/CP)

C_OUT

† Characteristics are over recommended operating conditions unless otherwise stated

‡ Typical figures are at 25°C, V_DD=5 V, and for design aid only: not guaranteed and not subject to production testing

Notes:

dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.

Digit sequence consists of all 16 DTMF tones.

Tone duration=40 ms. Tone pause=40 ms.

Nominal DTMF frequencies are used.

Both tones in the composite signal have an equal amplitude.

The tone pair is deviated by ± 1.5%±2 Hz.

Bandwidth limited (3 kHz) Gaussian noise.

The precise dial tone frequencies are 350 and 440 Hz (±2%).

Guaranteed by design and characterization. Not subject to production testing.

10. Referenced to the lowest amplitude tone in the DTMF signal.

11.

For guard time calculation purposes.

t_CYC

t_R

t_F

t_PWH

t_PWL

RD/WR

Figure 18 - RD/WR Clock Pulse

t_PWL

t_PWH

t_AS

t_AH

CS, RS0

t_DHR

t_DDR

DATA BUS

Figure 19 - 8031/8051/8085 Read Timing Diagram

t_PWL

t_PWH

t_AS

t_AH

CS, RS0

t_DSW

t_DHW

DATA BUS

Figure 20 - 8031/8051/8085 Write Timing Diagram

Zarlink Semiconductor Inc.

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visit our Web Site at

www.zarlink.com

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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such

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property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in

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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in

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Purchase of Zarlink’s I²C components conveys a licence under the Philips I²C Patent rights to use these components in and I²C System, provided that the system

conforms to the I²C Standard Specification as defined by Philips.

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

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