MT8889CE1 [MICROSEMI]
DTMF Signaling Circuit, CMOS, PDIP20, LEAD FREE, PLASTIC, MS-001AD, DIP-20;
| 型号： | MT8889CE1 |
| 厂家： | 
Microsemi |
| 描述： | DTMF Signaling Circuit, CMOS, PDIP20, LEAD FREE, PLASTIC, MS-001AD, DIP-20 电信 光电二极管 电信集成电路 |
| 文件： | 总24页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Data Sheet
July 2008
Features
•
•
•
•
•
•
Central office quality DTMF transmitter/receiver
Ordering Information
Low power consumption
MT8889CE
MT8889CS
MT8889CN
MT8889CE1
MT8889CS1
MT8889CN1
MT8889CSR
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
20 Pin PDIP*
20 Pin SOIC*
24 Pin SSOP*
20 Pin SOIC
Tubes
Tubes
High speed adaptive micro interface
Adjustable guard time
Tubes
Tubes
Tubes
Tubes
Automatic tone burst mode
Tape & Reel
Tape & Reel
MT8889CSR1 20 Pin SOIC*
*Pb Free Matte Tin
Call progress tone detection to -30 dBm
-40°C to +85°C
Applications
•
•
•
•
•
Credit card systems
Paging systems
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
D0
Data
Bus
Buffer
Row and
D/A
Transmit Data
D1
D2
D3
∑
Column
TONE
Converters
Register
Counters
Status
Register
Interrupt
Logic
Tone Burst
Gating Cct.
Control
Logic
IRQ/CP
Control
Register
A
IN+
IN-
GS
+
-
Dial
Tone
Filter
High Group
Filter
Digital
DS/RD
CS
Algorithm
and Code
Converter
Control
Register
B
I/O
Low Group
Filter
Control
OSC1
OSC2
Oscillator
R/W/WR
RS0
Circuit
Control
Logic
Receive Data
Register
Steering
Logic
Bias
Circuit
VDD VRef VSS
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.
MT8889C
Data Sheet
Functional Description
The MT8889C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the
MT8889C internal registers.
24
23
22
21
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
VSS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
•
NC
VRef
VSS
OSC1
OSC2
NC
NC
NC
NC
D3
D2
D1
D0
5
25
24
23
22
21
20
19
6
7
8
9
OSC1
OSC2
TONE
R/W/WR
CS
10
11
NC
9
9
10
10
11
12
IRQ/CP
DS/RD
RS0
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
24
Name
Description
20
28
1
2
3
1
2
3
1
2
4
IN+
IN-
GS
Non-inverting op-amp input.
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for
connection of feedback resistor.
4
5
6
4
5
6
6
7
8
VRef
VSS
Reference Voltage output (VDD/2).
Ground (0V).
OSC1 DTMF clock/oscillator input. Connect a 4.7 MΩ resistor to VSS if crystal oscillator
is used.
7
7
9
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8
9
10
11
12
12
TONE Output from internal DTMF transmitter.
13 R/W (WR) (Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
10
14
CS
Chip Select input. This signal must be qualified externally by either address
strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal,
see Figure 14.
11
12
13
14
15
17
RS0
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this
input is only required when the device is being accessed. TTL compatible.
2
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
Pin Description (continued)
Pin #
Name
Description
20
24
28
13
15
18
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this
output goes low when a valid DTMF tone burst has been transmitted or received.
In call progress mode, this pin will output a rectangular signal representative of
the input signal applied at the input op-amp. The input signal must be within the
bandwidth limits of the call progress filter, see Figure 8.
14-17 18-21 19-22
D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or
RD = 1 (Intel). TTL compatible.
18
19
22
23
26
27
ESt
Early Steering output. Presents a logic high once the digital algorithm has
detected a valid tone pair (signal condition). Any momentary loss of signal
condition will cause ESt to return to a logic low.
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt
detected at St causes the device to register the detected tone pair and update the
output latch. A voltage less than VTSt frees the device to accept a new tone pair.
The GT output acts to reset the external steering time-constant; its state is a
function of ESt and the voltage on St.
20
24
28
VDD
NC
Positive power supply (5 V typical).
No Connection.
8, 9, 3,5,10,
16,17 11,16,
23-25
1.0 Input Configuration
The input arrangement of the MT8889C provides a differential-input operational amplifier as well as a bias source
(VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
2.0 Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
3
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
IN+
IN-
RIN
C
GS
RF
VRef
MT8889C
VOLTAGE GAIN
(AV) = RF / RIN
Figure 3 - Single-Ended Input Configuration
IN+
IN-
C1
C2
R1
R4
R5
R2
GS
R3
VRef
MT8889C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(AV diff) - R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 4 - Differential Input Configuration
FLOW
FHIGH
1209
DIGIT
D3
D2
D1
D0
697
697
697
770
770
770
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1336
1477
1209
1336
1477
Table 1 - Functional Encode/Decode Table
4
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
FLOW
FHIGH
1209
DIGIT
D3
D2
D1
D0
852
852
852
941
941
941
697
770
852
941
7
8
9
0
*
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1336
1477
1336
1209
1477
1633
1633
1633
1633
#
A
B
C
D
Table 1 - Functional Encode/Decode Table (continued)
0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
3.0 Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed
steering flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
5
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
VDD
MT8889C
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt
)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
tREC ≥ tDPmax + tGTPmax - tDAmin
tREC ≤ tDPmin + tGTPmin - tDAmax
tID ≥ tDAmax + tGTAmax - tDPmin
tDO ≤ tDAmin + tGTAmin - tDPmax
t
GTP = (RPC1) In [VDD / (VDD-VTSt)]
GTA = (R1C1) In (VDD/VTSt
P = (R1R2) / (R1 + R2)
t
)
R
VDD
C1
St/GT
R1
R2
ESt
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
tGTA = (RpC1) In (VDD/VTSt
RP = (R1R2) / (R1 + R2)
)
VDD
C1
St/GT
R1
R2
b) decreasing tGTA; (tGTP > tGTA)
ESt
Figure 6 - Guard Time Adjustment
6
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP
)
and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept
and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor
system parameters such as talk off and noise immunity.
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
4.0 Call Progress Filter
A call progress mode, using the MT8889C, can be selected allowing the detection of various tones, which identify
the progress of a telephone call on the network. The call progress tone input and DTMF input are common,
however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call
progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are
hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained
from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and
consequently the IRQ/CP pin will remain low.
EVENTS
A
B
C
D
E
F
tREC
tDO
tID
tREC
TONE
#n + 1
TONE
#n + 1
TONE #n
Vin
tDA
tDP
ESt
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
b3
DECODED TONE # (n-1)
# (n + 1)
# n
tPStb3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
7
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
LEVEL
(dBm)
-25
0
250
500
750
FREQUENCY (Hz)
= Reject
= May Accept
= Accept
Figure 8 - Call Progress Response
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
E)
F)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
4-BIT DECODED DATA IN RECEIVE DATA REGISTER
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
St/GT
RX0-RX3
b3
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE
STATUS REGISTER IS READ.
IRQ/CP
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
tREC
tID
tDO
tDP
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA
TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP
tGTA
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
Figure 9 - Description of Timing Events
8
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
5.0 DTMF Generator
The DTMF transmitter employed in the MT8889C is capable of generating all sixteen standard DTMF tone pairs
with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The
sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable
dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a
DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the
encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the
receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and
High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB
to compensate for high group attenuation on long loops.
The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above the frequency can also be
varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and
highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which
are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other
DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst
accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can
be seen from Figure 6 that the distortion products are very low in amplitude.
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
9
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
6.0 Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration
determined either by the particular application or by any one of the exchange transmitter specifications currently
existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is
capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms
which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the
appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing
described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)
is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have
been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard
burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses
when the burst mode is disabled by enabling and disabling the transmitter.
7.0 Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This
mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion
measurements. Refer to Control Register B description for details.
OUTPUT FREQUENCY (Hz)
ACTIVE
%ERROR
INPUT
SPECIFIED
697
ACTUAL
699.1
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
770
766.2
852
847.4
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
Table 2 - Actual Frequencies Versus Standard Requirements
10
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
8.0 Distortion Calculations
The MT8889C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The
internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic
components and intermodulation products. The total harmonic distortion for a single tone can be calculated using
Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental
frequency expressed as a percentage.
V22f + V23f + V24f + .... V2
nf
THD (%) = 100
Vfundamental
Figure 11 - Equation 1. THD (%) For a Single Tone
The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total
harmonic distortion for a dual tone can be calculated using Equation 2. VL and VH correspond to the low group
amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The
internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as
shown in Figure 10.
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
THD (%) = 100
V2L + V2
H
Figure 12 - Equation 2. THD (%) For a Dual Tone
9.0 DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
3.579545 MHz
±0.1%
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Parallel
18 pF
Maximum Series Resistance: 150 ohms
Maximum Drive Level: 2 mW
e.g.
CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8889C devices can be connected as shown in Figure 13 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left
unconnected.
11
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
MT8889C
MT8889C
MT8889C
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
3.579545 MHz
Figure 13 - Common Crystal Connection
10.0 Microprocessor Interface
The MT8889C design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
•
•
Continuous activity on DS/RD is not necessary to update the internal status registers.
senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD), R/W (WR)
and CS inputs.
•
•
generates equivalent CS signal for internal operation for all processors.
differentiates between multiplexed and non-multiplexed microprocessor buses. Address and data are
latched in accordingly.
•
compatible with Motorola and Intel processors.
Figure 19 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members
of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the
chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800
and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal
logic senses the state of data strobe (DS). When DS is low, Motorola processor operation is selected.
Figure 20 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS)
input is formed by NANDing address strobe (AS) and address decode output. Again, the MT8889C examines the
state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the
Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 14(a) summarizes connection of
these Motorola processors to the MT8889C DTMF transceiver.
Figures 21 and 22 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-controllers
with multiplexed address and data buses. The MT8889C latches in the state of RD on the falling edge of CS. When
RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-
byte address (P2) decode output, CS can be generated. Figure 14(b) summarizes the connection of these Intel
processors to the MT8889C transceiver.
NOTE: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller interface
and this pin must not be tied permanently low.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write
operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-
only status register indicates the current transceiver state (see Table 8).
12
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 17). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 15).
Motorola
R/W
Intel
WR
RS0
RD
FUNCTION
Write to Transmit
Data Register
0
0
0
1
1
Read from Receive
Data Register
0
1
0
Write to Control Register
Read from Status Register
1
1
0
1
0
1
1
0
Table 3 - Internal Register Functions
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 4 - CRA Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
ENABLE
Table 5 - CRB Bit Positions
13
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
MC6800/6802
MT8889C
CS
MT8889
MC68HC11
A0-A15
A8-A15
AS
CS
RS0
D0-D3
VMA
AD0-AD3
DS
D0-D3
RS0
D0-D3
DS/RD
R/W/WR
DS/RD
RW
Φ2
R/W/WR
RW
(a)
8031/8051
8080/8085
MC6809
MT8889
MT8889C
A0-A15
CS
A8-A15
ALE
CS
RS0
Q
E
D0-D3
RS0
D0-D3
D0-D3
R/W
P0
RD
R/W/WR
DS/RD
DS/RD
R/W/WR
WR
(b)
Figure 14 - a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros
BIT
NAME
DESCRIPTION
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low turns the tone
output off. This bit controls all transmit tone functions.
b1
CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress
mode; a logic low enables DTMF mode. In DTMF mode the device is capable of receiving
and transmitting DTMF signals. In CP mode a rectangular wave representation of the
received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled
(control register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
b3
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
RSEL
Register Select. A logic high selects control register B for the next write cycle to the
control register address. After writing to control register B, the following control register
write cycle will be directed to control register A.
Table 6 - Control Register A Description
14
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
BIT
NAME
DESCRIPTION
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
b2
b3
TEST
S/D
Test Mode Control. A logic high enables the test mode; a logic low de-activates the test
mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the
signal present on the IRQ/CP pin will be analogous to the state of the DELAYED
STEERING bit of the status register (see Figure 7, signal b3).
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low
selects a row tone output. This function is used in conjunction with the S/D bit (control
register B, b2).
Table 7 - Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8 - Status Register Description
15
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
VDD
MT8880C
C3
R4
VDD
IN+
C1
R1
C2
St/GT
ESt
DTMF/CP
INPUT
IN-
GS
R3
R2
D3
VRef
VSS
D2
D1
OSC1
OSC2
TONE
R/W/WR
CS
R5
D0
X-tal
RL
To µP
or µC
IRQ/CP
DS/RD
RS0
DTMF
OUTPUT
C4
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
R5 = 4.7 MΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8889C can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
Figure 15 - Application Circuit (Single-Ended Input)
5.0 VDC
5.0 VDC
MMD6150 (or
equivalent)
2.4 kΩ
3 kΩ
TEST POINT
TEST POINT
130 pF
24 kΩ
100 pF
MMD7000 (or
equivalent)
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 16 - Test Circuits
16
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after power
up. The initialization procedure should be implemented 100ms after power up.
Description:
Motorola
Intel
Data
b1
RS0
R/W
WR RD
b3
b2
b0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
1
1
0
X
0
0
1
0
X
X
0
0
0
0
X
X
0
0
0
0
X
X
0
0
0
0
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
1
R/W
0
WR
0
RD
1
b3
b2
1
b1
0
b0
1
1) Write to Control Register A
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
1
0
0
0
1
1
0
0
0
1
0
1
0
1
3) Write to Transmit Data Register
(send a digit 7)
0
0
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register
1
1
1
0
1
X
0
X
1
X
0
X
1
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
0
0
0
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
1
1
0
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
0
1
0
1
0
0
1
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
Figure 17 - Application Notes
17
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
Absolute Maximum Ratings*
Parameter
Power supply voltage VDD-VSS
Symbol
Min.
Max.
Units
1
2
3
4
5
VDD
VI
6
V
Voltage on any pin
VSS-0.3
-65
VDD+0.3
10
V
Current at any pin (Except VDD and VSS
)
mA
°C
Storage temperature
TST
PD
+150
1000
Package power dissipation
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Parameter
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
Positive power supply
Operating temperature
Crystal clock frequency
VDD
TO
4.75
-40
5.00
5.25
+85
V
°C
fCLK
3.575965 3.579545 3.583124
MHz
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - V =0 V.
SS
Characteristics
Sym.
Min. Typ.‡ Max. Units
Test Conditions
1
2
3
4
Operating supply voltage
Operating supply current
Power consumption
VDD
IDD
4.75
5.0
7.0
5.25
11
V
mA
mW
V
S
U
P
PC
57.8
High level input voltage
(OSC1)
VIHO
3.5
Note 9*
I
N
P
U
T
S
5
Low level input voltage
(OSC1)
VILO
VTSt
VOLO
VOHO
1.5
2.5
0.1
V
V
V
V
Note 9*
6
7
Steering threshold voltage
2.2
2.3
VDD=5V
Low level output voltage
(OSC2)
No load
Note 9*
O
U
T
P
U
T
8
9
High level output voltage
(OSC2)
No load
Note 9*
4.9
2.4
Output leakage current
(IRQ)
IOZ
VRef
ROR
VIL
1
10
µA
V
VOH=2.4 V
S
10
11
12
13
14
V
Ref output voltage
2.5
1.3
2.6
No load, VDD=5V
VRef output resistance
Low level input voltage
High level input voltage
Input leakage current
kΩ
V
D
i
g
i
0.8
10
VIH
IIZ
2.0
V
µA
VIN=VSS to VDD
t
a
l
15
16
17
18
Source current
Sink current
IOH
IOL
IOH
IOL
-1.4
2.0
-0.5
2
-6.6
4.0
-3.0
4
mA VOH=2.4V
mA VOL=0.4V
mA VOH=4.6V
mA VOL=0.4V
Data
Bus
ESt
and
St/GT
Source current
Sink current
18
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
DC Electrical Characteristics† (continued)- V =0 V.
SS
Characteristics
Sink current
Sym.
Min. Typ.‡ Max. Units
16 mA VOL=0.4V
Test Conditions
IRQ/
CP
19
IOL
4
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
Input leakage current
Input resistance
IIN
RIN
100
nA
MΩ
mV
dB
VSS ≤ VIN ≤ VDD
10
Input offset voltage
VOS
25
Power supply rejection
Common mode rejection
DC open loop voltage gain
Unity gain bandwidth
Output voltage swing
PSRR
CMRR
AVOL
BW
50
40
1 kHz
dB
40
dB
CL = 20p
CL = 20p
1.0
0.5
MHz
V
VO
VDD-0.5
100
RL ≥ 100 kΩ to VSS
9
Allowable capacitive load (GS)
CL
RL
pF
kΩ
V
PM>40°
VO = 4Vpp
RL = 50kΩ
10 Allowable resistive load (GS)
11 Common mode range
50
VCM
1.0
VDD-1.0
Figures are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
MT8889C AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡ Max.
Units
Notes*
1,2,3,5,6
1,2,3,5,6
Valid input signal levels
(each tone of composite
signal)
-29
+1
dBm
R
X
1
27.5
869
mVRMS
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 15.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes*
1
2
3
4
5
6
7
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
8
8
dB
dB
2,3,6,9
2,3,6,9
2,3,5
±1.5%± 2Hz
±3.5%
R
X
2,3,5
-16
-12
22
dB
dB
dB
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9
Dial tone tolerance
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
19
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Accept Bandwidth
Sym.
Min.
Typ.‡
Max. Units
Conditions
@ -25 dBm,
1
fA
310
500
Hz
Note 9
2
3
4
Lower freq. (REJECT)
Upper freq. (REJECT)
fLR
fHR
290
540
Hz
Hz
@ -25 dBm
@ -25 dBm
Call progress tone detect level (total
power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual values are user
selectable as per Figures 5, 6 and 7.
Characteristics
Sym.
Min.
Typ.‡ Max. Units
Conditions
1
2
3
4
Minimum tone accept duration
Maximum tone reject duration
Minimum interdigit pause duration
Maximum tone drop-out duration
tREC
tREC
tID
40
20
40
20
ms
ms
ms
ms
tDO
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions
T
O
N
E
1
2
3
4
Tone present detect time
Tone absent detect time
Delay St to b3
tDP
tDA
tPStb3
tPStRX
3
11
4
14
ms Note 11
ms Note 11
0.5
8.5
13
8
µs
µs
See Figure 7
See Figure 7
I
N
Delay St to RX0-RX3
5
6
Tone burst duration
tBST
tPS
tBSTE
tPSE
50
50
52
52
ms DTMF mode
ms DTMF mode
ms Call Progress mode
ms Call Progress mode
dBm RL=10kΩ
Tone pause duration
7
Tone burst duration (extended)
Tone pause duration (extended)
High group output level
Low group output level
Pre-emphasis
100
100
-6.1
-8.1
0
104
104
-2.1
-4.1
3
T
O
N
E
8
9
VHOUT
VLOUT
dBP
10
11
12
13
14
15
dBm RL=10kΩ
O
U
T
2
dB
dB
RL=10kΩ
Output distortion (Single Tone)
THD
-35
25 kHz Bandwidth
RL=10kΩ
Frequency deviation
fD
±0.7
±1.5
%
fC=3.579545 MHz
Output load resistance
RLT
10
50
kΩ
20
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
AC Electrical Characteristics† (continued) - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions
16
17
18
19
Crystal/clock frequency
Clock input rise and fall time
Clock input duty cycle
fC
3.5759 3.5795 3.5831 MHz
X
T
A
L
tCLRF
DCCL
CLO
110
60
ns
%
Ext. clock
Ext. clock
40
50
Capacitive load (OSC2)
30
pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡ Max.
Units
Conditions
Figure 18
1
2
3
4
5
6
7
8
9
DS/RD/WR clock frequency
DS/RD/WR cycle period
DS/RD/WR low pulse width
DS/RD/WR high pulse width
DS/RD/WR rise and fall time
R/W setup time
fCYC
tCYC
tCL
4.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
250
Figure 18
150
Figure 18
tCH
100
20
Figure 18
tR,tF
tRWS
tRWH
tAS
Figure 18
23
20
0
Figures 19 & 20
Figures 19 & 20
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
Figures 19 - 22
R/W hold time
Address setup time (RS0)
Address hold time (RS0)
tAH
40
22
20
10 Data hold time (read)
tDHR
tDDR
tDSW
tDHW
tCSS
tCSH
CIN
11 DS/RD to valid data delay (read)
12 Data setup time (write)
13 Data hold time (write)
100
45
10
45
40
14 Chip select setup time
35
15 Chip select hold time
16 Input Capacitance (data bus)
17 Output Capacitance (IRQ/CP)
5
5
COUT
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES:
1. dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2.
Digit sequence consists of all 16 DTMF tones.
3. Tone duration=40 ms. Tone pause=40 ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amplitude.
6. The tone pair is deviated by ± 1.5%±2 Hz.
7. Bandwidth limited (3 kHz) Gaussian noise.
8. The precise dial tone frequencies are 350 and 440 Hz (±2%).
9. Guaranteed by design and characterization. Not subject to production testing.
10. Referenced to the lowest amplitude tone in the DTMF signal.
11. For guard time calculation purposes.
21
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
tCYC
tR
tF
tCH
tCL
DS/RD/WR
Figure 18 - DS/RD/WR Clock Pulse
tRWH
tRWS
DS
Q clk*
A0-A15
(RS0)
16 bytes of Addr
R/W(read)
tDDR
tDHR
Read Data
(D3-D0)
R/W (write)
➀
tDSW
tDHW
Write data
(D3-D0)
➀
tCSS
tCSH
tAH
tAS
CS = (E + Q).Addr [MC6809]
tAH
CS = VMA.Addr [MC6800, MC6802]
*microprocessor pin
tAS
➀
tCSS
tCSH
Figure 19 - MC6800/MC6802/MC6809 Timing Diagram
Note: ➀ tDSW is from data to DS falling edge; tCSH is from DS rising edge to CS rising edge
22
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
tRWS
DS
tRWH
R/W
tDHR
tDDR
tAS
Read
AD3-AD0
(RS0, D0-D3)
Addr
Data
Write
AD3-AD0
(RS0-D0-D3)
Data
tDHW
Addr
tDSW
tAH
tCSH
Addr *
non-mux
High Byte of Addr
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 20 - MC68HC11 Bus Timing (with multiplexed address and data buses)
tCSS
ALE*
RD
tDHR
tAS
tDDR
tAH
A0-A7
P0*
(RS0,
D0-D3)
Data
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 21 - 8031/8051/8085 Read Timing Diagram
23
Zarlink Semiconductor Inc.
MT8889C
Data Sheet
ALE*
WR
tCSS
tDSW
Data
tAS
tAH
A0-A7
tDHW
P0*
(RS0,
D0-D3)
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 22 - 8031/8051/8085 Write Timing Diagram
24
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