XCR3256XL-7PQ144C [XILINX]
256 Macrocell CPLD; 256宏单元CPLD
| 型号： | XCR3256XL-7PQ144C |
| 厂家： | 
XILINX, INC |
| 描述： | 256 Macrocell CPLD |
| 文件： | 总10页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3256XL 256 Macrocell CPLD
0
14
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
Features
Description
•
•
•
•
7.5 ns pin-to-pin logic delays
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
System frequencies up to 140 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
-
-
-
144-pin TQFP (116 user I/O pins)
208-pin PQFP (160 user I/O)
280-ball CS BGA (160 user I/O)
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate
implementation allows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to Figure 1 and Table 1 showing the ICC vs. Fre-
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25 C).
•
•
Optimized for 3.3V systems
-
-
-
Ultra low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five metal layer re-
programmable process
-
FZP™ CMOS design technology
Advanced system features
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per logic block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per logic block
•
•
•
•
•
•
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V industrial grade voltage range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
DS013 (v1.2) May 3, 2000
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
140
120
100
80
60
40
20
0
0
20
40
60
Frequency (MHz)
Figure 1: XCR3256XL Typical ICC vs. Frequency at VCC = 3.3V, 25 C
80
100
120
140
160
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25 C
Frequency (MHz)
0
1
10
20
40
60
80
100
120
140
Typical ICC (mA)
0.02
0.91
8.87
17.7
34.8
51.5
68
84.2
100.1 116.6
(1)
DC Electrical Characteristics Over Recommended Operating Conditions
Symbol
VOH
VOL
Parameter
Output High voltage for 3.3V outputs
Output Low voltage for 3.3V outputs
Input leakage current
Test Conditions
IOH = –8 mA
Min.
Max.
-
Unit
V
2.4
IOL = 8 mA
-
0.4
10
10
100
2
V
IIL
VIN = GND or VCC
VIN = GND or VCC
VCC = 3.6V
f = 1 MHz
–10
A
IIH
I/O High-Z leakage current
Standby current
–10
A
ICCSB
ICC
-
-
A
Dynamic current(2,3)
mA
mA
pF
pF
pF
f = 50 MHz
-
60
8
CIN
Input pin capacitance(4)
Clock input capacitance(4)
I/O pin capacitance(4)
f = 1 MHz
-
CCLK
CI/O
f = 1 MHz
5
-
12
10
f = 1 MHz
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Table 1, Figure1 for typical values.
3. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
4. Typical values not tested.
2
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DS013 (v1.2) May 3, 2000
1-800-255-7778
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
(1,2)
AC Electrical Characteristics Over Recommended Operating Conditions
-7
-10
-12
Symbol
TPD1
TPD2
TCO
Parameter
Propagation delay time (single p-term)
Propagation delay time (OR array)(3)
Clock to output (global synchronous pin clock)
Setup time fast
Min.
Max.
7.0
7.5
4.5
-
Min.
Max.
9.0
10.0
5.8
-
Min.
Max.
10.8
12.0
6.9
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
s
-
-
-
-
-
-
-
-
-
TSUF
TSU
2.0
2.5
3.0
Setup time
4.8
-
6.5
-
7.9
-
TH
Hold time
0
-
0
-
0
-
TWLH
TPLH
TR
Global clock pulse width (High or Low)
P-term clock pulse width (High or Low)
Input rise time
3.0
-
4.0
-
5.0
-
4.5
-
6.0
-
7.5
-
-
-
-
-
-
-
-
-
20
20
140
40
9.0
9.0
8.0
9.0
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
20
TL
Input fall time
20
20
fSYSTEM
TCONFIG
TPOE
TPOD
TPCO
TPAO
Notes:
Maximum system frequency
Configuration time(4)
105
40
88
40
P-term OE to output enabled
P-term OE to output disabled (5)
P-term clock to output
11.0
11.0
10.3
11.0
13.0
13.0
12.4
13.0
ns
ns
ns
ns
P-term set/reset to output valid
1. Specifications measured with one output switching.
2. See XPLA3 Family Data Sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. Typical current draw during configuration is 10 mA at 3.6V.
5. Output CL = 5 pF.
DS013 (v1.2) May 3, 2000
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
Timing Model
The XPLA3 architecture follows a simple timing model that
allows deterministic timing in design and redesign. The
basic timing model is shown in Figure 2. One key feature of
the XPLA3 CPLD is the ability to have up to 48 product term
inputs into a single macrocell and maintain consistent tim-
ing. This is achieved through the use of a fully populated
PLA (Programmable AND Programmable OR Array) which
also has the ability to share product terms and only use the
required amount of product terms per macrocell. There is a
fast path (TLOGI1) into the macrocell which is used if there is
a single product term. The TLOGI2 path is used for multiple
product term timing. For optimization of logic, the XPLA3
CPLD architecture includes a Fold-back NAND path
(TLOGI3). There is a fast input path to each macrocell if used
as an Input Register (TFIN). XPLA3 also includes universal
control terms (TUDA) that can be used for synchronization of
the macrocell registers in different logic blocks. There is
also slew rate control and output enable control on a per
macrocell basis.
T
F
T
T
LOGI1,2
T
T
T
DLT
CE
IN
OUT
EN
SLEW
Q
T
FIN
T
UDA
T
T
LOGI3
S/R
GCK
DS017_02_042800
Figure 2: XPLA3 Timing Model
4
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1-800-255-7778
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Internal Timing Parameters
-7
-10
-12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
TIN
Input buffer delay
Fast input buffer delay
-
-
-
-
-
2.5
2.2
1.0
2.5
4.5
-
-
-
-
-
3.3
2.8
1.3
2.8
5.2
-
-
-
-
-
4.0
3.3
1.5
3.3
6.0
ns
ns
ns
ns
ns
TFIN
TGCK
TOUT
TEN
Global clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Internal Register and Combinatorial Delays
TLDI
Latch transparent delay
-
0.8
4.0
2.0
3.0
-
1.3
-
-
1.0
5.5
2.5
4.5
-
1.6
-
-
1.2
6.7
3.0
5.5
-
2.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSUI
Register setup time
THI
Register hold time
-
-
-
TECSU
TECHO
TCOI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
-
-
-
-
-
1.0
2.0
5.0
2.0
2.5
1.3
2.0
7.0
2.5
3.5
1.6
2.2
8.0
3.0
4.2
TAOI
-
-
-
TRAI
-
-
-
TLOGI1
TLOGI2
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
-
-
-
Feedback Delays
TF
ZIA delay
-
2.8
-
3.7
-
4.4
ns
Time Adders
TLOGI3
TUDA
Fold-back NAND delay
-
-
-
6.0
2.0
4.0
-
-
-
8.0
2.5
5.0
-
-
-
9.5
3.0
6.0
ns
ns
ns
Universal delay
TSLEW
Slew rate limited delay
DS013 (v1.2) May 3, 2000
www.xilinx.com
5
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
390Ω
390Ω
35 pF
R1
R2
C1
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Closed
Closed
Open
Closed
T
T
(High)
POE
R2
C1
(Low)
POE
T
P
Note: For T
, C1 = 5 pF
POD
S2
DS013_03_050200
Figure 3: AC Load Circuit
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
+3.0V
0V
90%
10%
T
R
T
L
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
1
2
4
8
16
inputs and outputs, unless otherwise specified.
Number of Adjacent Outputs Switching
DS017_05_042800
DS013_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
6
www.xilinx.com
1-800-255-7778
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 2: XCR3256XL Pin Descriptions (Continued)
Pin Descriptions
BScan
Table 2: XCR3256XL Pin Descriptions
Function
D0
CS280
E14
D14
A14
C13
B13
A13
A12
PQ208
197
TQ144
114
116
117
-
Order
506
502
498
494
490
480
476
BScan
Order
Function
A0
CS280
E18
PQ208
TQ144
D1
196
6
7
106
-
736
732
D2
195
A1
E19
D3
194
104
(TDO)
A2
A3
F15*
F17
F18
F19
G16
G17
G19
H16
B19
B18
B17
A18
A17
C16
A16
E15
D15
A15
H17
H18
H19
J16
8*
9
728*
724
720
710
706
702
698
694
552
548
544
540
536
526
522
518
514
510
690
686
682
678
674
664
660
656
652
648
-
D4
193
118
119
120
103
102
101
100
99
-
D11
D12
192
A4
10
190
A11
A12
A13
A14
A15
B0
11
C12
189
D13
D14
D15
E0
(TDO)
(TDO)
121
-
12
B12
D12
L17*
L18
188
187
28*
29
-
122
468
464
644*
640
13
15
89 (TCK)
-
16
-
E1
4
107
108
-
L19
B1
3
E2
E3
(TCK)
30 (TCK)
31
88
87
86
84
-
-
B2
206
205
204
203
202
201
199
198
17
M16
M18
M17
N16
N19
N18
N17
U10
T10
W11
U11
T11
W12
U12
T12
V13
U13
P16
P18
R19
R16
R18
632
628
618
614
610
606
602
460
456
452
448
444
434
430
426
422
418
598
594
590
586
582
B3
-
E4
33
B4
109
110
111
-
E11
E12
E13
E14
E15
F0
34
B11
B12
B13
B14
B15
C0
35
36
83
82
-
37
112
113
98
97
96
94
93
92
-
38
78
-
F1
77
55
56
-
C1
18
F2
76
C2
19
F3
73
C3
20
F4
71
60
61
62
63
-
C4
J17
21
F11
F12
F13
F14
F15
G0
70
C11
C12
C13
C14
C15
CLK0/IN0
CLK1/IN1
CLK2/IN2
CLK3/IN3
J18
22
69
K16
K17
K18
L16
A10
D11
C11
B11
24
68
25
91
90
-
67
26
66
65
81
-
27
39
181
182
183
184
128
127
126
125
G1
40
-
G2
42
80
79
78
-
G3
43
-
G4
44
*Note: BScan Order for CS280 and PQ208 only.
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
7
R
XCR3256XL 256 Macrocell CPLD
Table 2: XCR3256XL Pin Descriptions (Continued)
Table 2: XCR3256XL Pin Descriptions (Continued)
BScan
BScan
Function
G11
CS280
R17
R15
T17
T16
U19
E10
E11
E12
E13
E5
PQ208
TQ144
Order
Function
CS280
T14
R14
W15
U15
V15
T15
V16
W17
B1
PQ208
TQ144
Order
406
402
398
388
384
380
376
372
368
364
360
356
352
342
338
334
330
326
184*
180
176
172
168
158
154
150
146
142
322
318
314
310
306
296
292
-
45
46
47
48
49
82
75
185
180
152
134
94
72
50
32
14
200
174
-
77
-
572
H2
62
68
G12
568
H3
61
69
G13
75
74
-
564
H4
60
-
G14
560
H11
H12
H13
H14
H15
I0
59
70
G15
556
58
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
52
57
124
129
3
-
57
71
-
56
-
-
55
72
-
153
154
159
160
161
162
163
164
166
167
151*
150
149
148
147
146
145
144
142
141
168
169
170
171
172
173
175
2
-
I1
C3
1
E7
17
33
59
64
85
105
135
-
-
I2
A4
-
-
E8
-
I3
B5
E9
-
I4
C5
143
-
G15
G5
-
I11
I12
I13
I14
I15
J0
A5
-
E6
142
141
140
139
4 (TDI)
-
H15
H5
-
D6
-
B6
J15
J5
-
A6
-
-
D2*
D1
K15
K5
-
-
-
J1
-
-
-
J2
E3
5
L15
L5
-
-
-
J3
E2
6
-
-
-
J4
E4
7
M15
M5
-
-
-
J11
J12
J13
J14
J15
K0
E1
8
-
-
-
F5
-
N15
N5
-
-
-
F3
9
-
-
-
F4
10
11
-
R7
-
-
-
G3
D7
R8
-
-
-
R9
-
-
-
K1
C7
-
R10
R11
R12
R13
T13
W14
-
-
-
K2
B7
138
-
-
-
-
-
K3
A7
-
-
K4
C8
137
136
134
133
-
-
-
K11
K12
K13
B8
65
64
66
67
414
410
C9
H1
B9 (TDI) 176 (TDI)
*Note: BScan Order for CS280 and PQ208 only.
8
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1-800-255-7778
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 2: XCR3256XL Pin Descriptions (Continued)
Table 2: XCR3256XL Pin Descriptions (Continued)
BScan
BScan
Function
K14
K15
L0
CS280
D10
C10
G2
G1
G4
H1
PQ208
177
178
140
139
138
137
136
135
133
132
131
130
79
TQ144
Order
284
280
138
134
130
126
122
112
108
104
100
96
Function
O3
CS280
W5
T5
PQ208
96
TQ144
41
40
-
Order
132
218
131
O4
97
214
-
O11
O12
O13
O14
O15
P0
V5
98
204
L1
-
U5
99
39
38
-
200
L2
12
W4
U4
100
101
102
118
117
115
114
113
112
111
110
109
108
116
83
196
L3
14
192
L4
H3
15
W3
P1
37
-
188
46
42
38
34
30
20
16
12
8
L11
L12
L13
L14
L15
M0
H2
16
J2
-
P1
P2
-
J3
18
P2
P4
29
30
31
32
-
K2
19
P3
R3
K3
-
P4
R2
W10
T9
-
276
272
268
264
260
250
246
242
238
234
92*
P11
P12
P13
P14
P15
PORT_EN
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R4
M1
80
54
T3
M2
U9
81
53
U1
34
35
36
13
51
58
123
130
24
50
73
76
95
115
144
-
M3
T8
84
-
V1
M4
T7
86
49
U2
4
M11
M12
M13
M14
M15
N0
W7
V7
87
48
P3
-
88
47
V9
-
U7
89
46
V11
A11
B10
F2
74
-
W6
T6
90
-
186
179
143
125
107
85
-
91
45
-
K4*
L1
129*
128
20 (TMS)
-
-
N1
88
L4
-
127
(TMS)
V2
-
N2
N3
L2 (TMS)
L3
21
22
23
25
-
-
U8
-
126
124
123
122
121
120
119
92
80
U14
T18
P15
J19
D17
C14
D13
C6
63
-
N4
M1
76
41
-
N11
N12
N13
N14
N15
O0
M3
66
23
-
M4
62
5
-
N1
26
27
28
44
43
42
58
191
165
-
-
-
N2
54
-
-
N3
50
-
-
V6
230
226
222
-
-
-
O1
U6
93
*Note: BScan Order for CS280 and PQ208 only.
O2
R6
95
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
9
R
XCR3256XL 256 Macrocell CPLD
Ordering Information
Example: XCR3256XL -7 PQ 208 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Options
Temperature Range
Speed Options
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Packaging Options
TQ144: 144-pin Thin Quad Flat Package
PQ208: 208-pin Plastic Quad Flat Package
CS280: 280-ball Chip Scale Package
Table 3: XCR3256XL JTAG Pinout by package Type
(Pin Number)
Device
XCR3256XL
TCK
89
Port Enable
TMS
20
TDI
4
TDO
104
189
C12
144-pin TQ
208-pin PQ
280-pin CS
13
116
P3
30
127
L2
176
B9
L19
Component Compatibility
Pins
144
208
280
Type
Plastic TQFP
Plastic PQFP
Plastic BGA
Code
TQ144
C
PQ208
C
CS280
C
XCR3256XL
-7
-10
-12
C, I
C, I
C, I
C, I
C, I
C, I
Revision History
The following table shows the revision history for this document
Date
Version
1.0
Revision
01/21/00
02/10/00
05/03/00
Initial Xilinx release.
Updated Pinout table.
1.1
1.2
Minor updates and added Boundary Scan to pinout table.
10
www.xilinx.com
DS013 (v1.2) May 3, 2000
1-800-255-7778
Preliminary Product Specification
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