XCR3256XLSERIES [ETC]
256 Macrocell CPLD ; 256宏单元CPLD\n
| 型号： | XCR3256XLSERIES |
| 厂家： | 
ETC |
| 描述： | 256 Macrocell CPLD
|
| 文件： | 总12页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XCR3256XL 256 Macrocell CPLD
0
14
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
Features
Description
•
•
•
•
•
Lowest power 256 macrocell CPLD
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 function blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
7.5 ns pin-to-pin logic delays
System frequencies up to 140 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
-
-
-
-
144-pin TQFP (120 user I/O pins)
208-pin PQFP (164 user I/O)
256-ball FBGA (164 user I/O)
280-ball CS BGA (164 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
•
•
Optimized for 3.3V systems
-
-
-
Ultra low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
Figure 1 and Table 1 showing the I vs. Frequency of our
CC
-
XCR3256XL TotalCMOS CPLD (data taken with 16
resetable up/down, 16-bit counters at 3.3V, 25°C).
Advanced system features
-
-
-
-
-
-
-
-
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
140
120
100
80
Eight product term control terms per function block
•
•
•
Fast ISP programming times
60
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
40
•
•
•
Programmable slew rate control per output
Security bit prevents unauthorized access
20
Refer to XPLA3 family data sheet (DS012) for
architecture description
0
20
40
60
Frequency (MHz)
Figure 1: XCR3256XL Typical I vs. Frequency at
80
100 120 140 160
DS013_01_102401
CC
V
= 3.3V, 25°C
CC
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C
CC
CC
Frequency (MHz)
0
1
10
20
40
60
80
68
100
120
140
Typical I (mA)
0.02
0.91
8.87
17.7
34.8
51.5
84.2
100.1
116.6
CC
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS013 (v1.9) January 8, 2002
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
Parameter
Output High voltage
Test Conditions
= –8 mA
Min.
Max.
-
Unit
V
(2)
V
I
I
2.4
OH
OL
OH
OL
V
Output Low voltage for 3.3V outputs
Input leakage current
= 8 mA
-
0.4
10
10
100
2
V
I
I
I
I
V
V
V
= GND or V
= GND or V
–10
µA
µA
µA
mA
mA
pF
pF
pF
IL
IN
CC
CC
I/O High-Z leakage current
Standby current
–10
IH
IN
= 3.6V
-
-
CCSB
CC
CC
(3,4)
Dynamic current
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
-
60
8
(5)
C
C
C
Input pin capacitance
-
IN
(5)
Clock input capacitance
5
-
12
10
CLK
I/O
(5)
I/O pin capacitance
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions.
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. See Table 1, Figure 1 for typical values.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.
CC
5. Typical values, not tested.
100
90
I
(3.3V)
OL
80
70
60
50
40
30
I
(3.3V)
OH
I
(2.7V)
OH
20
10
0
0
0.5
1
1.5
2
2.5
Volts
3
3.5
4
4.5
5
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
2
www.xilinx.com
DS013 (v1.9) January 8, 2002
1-800-255-7778
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
(1,2)
AC Electrical Characteristics Over Recommended Operating Conditions
-7
-10
-12
Symbol
Parameter
Min.
Max.
7.0
7.5
4.5
-
Min.
Max.
9.0
10.0
5.8
-
Min.
Max.
10.8
12.0
6.9
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
µs
µs
ns
ns
ns
ns
T
T
T
T
T
T
T
T
Propagation delay time (single p-term)
-
-
-
PD1
PD2
CO
(3)
Propagation delay time (OR array)
-
-
-
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
-
-
-
2.5
3.0
3.0
SUF
(4)
4.3
-
5.5
-
6.7
-
SU1
4.8
-
6.5
-
7.9
-
SU2
(4)
H
Hold time
0
-
0
-
0
-
(4)
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
3.0
-
4.0
-
5.0
-
WLH
(4)
Tt
4.5
-
6.0
-
7.5
-
PLH
(4)
T
T
-
-
-
-
-
-
-
-
-
20
20
140
120
120
9.0
9.0
8.0
9.0
-
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
-
20
R
(4)
Input fall time
20
20
L
(4)
(4)
f
Maximum system frequency
105
120
120
11.0
11.0
10.3
11.0
88
SYSTEM
(5)
T
T
T
T
T
T
Configuration time
120
120
13.0
13.0
12.4
13.0
CONFIG
(4)
ISP initialization time
INIT
(4)
P-term OE to output enabled
POE
POD
PCO
(4)
(4)
(6)
P-term OE to output disabled
P-term clock to output
(4)
P-term set/reset to output valid
PAO
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 10 mA at 3.6V.
6. Output C = 5 pF.
L
DS013 (v1.9) January 8, 2002
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
Internal Timing Parameters(1,2)
-7
-10
-12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
T
T
T
T
T
Input buffer delay
-
-
-
-
-
2.5
2.2
1.0
2.5
4.5
-
-
-
-
-
3.3
2.8
1.3
2.8
5.2
-
-
-
-
-
4.0
3.3
1.5
3.3
6.0
ns
ns
ns
ns
ns
IN
Fast input buffer delay
FIN
GCK
OUT
EN
Global clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Internal Register and Combinatorial Delays
T
T
T
T
T
T
Latch transparent delay
-
0.8
0.3
2.0
3.0
-
1.3
-
-
1.0
0.5
2.5
4.5
-
1.6
-
-
1.2
0.7
3.0
5.5
-
2.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LDI
Register setup time
SUI
Register hold time
-
-
-
HI
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
-
-
-
ECSU
ECHO
COI
-
-
-
1.0
2.0
5.0
2.0
2.5
1.3
2.0
7.0
2.5
3.5
1.6
2.2
8.0
3.0
4.2
T
-
-
-
AOI
T
-
-
-
RAI
T
T
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
-
-
LOGI1
LOGI2
-
-
-
Feedback Delays
ZIA delay
Time Adders
T
-
2.8
-
3.7
-
4.4
ns
F
T
T
T
Fold-back NAND delay
Universal delay
-
-
-
6.0
2.0
4.0
-
-
-
8.0
2.5
5.0
-
-
-
9.5
3.0
6.0
ns
ns
ns
LOGI3
UDA
Slew rate limited delay
SLEW
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See XPLA3 family data sheet (DS012) for the timing model.
4
www.xilinx.com
1-800-255-7778
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Switching Characteristics
V
CC
S1
Component
Values
R1
R2
C1
390Ω
390Ω
35 pF
R1
V
IN
V
OUT
Measurement
S1
S2
Open
Closed
Open
T
(High)
(Low)
POE
R2
C1
T
Closed
Closed
POE
T
Closed
P
Note: For T
, C1 = 5 pF. Delay measured at
POD
output level of V + 300 mV, V
– 300 mV.
OL
OH
S2
DS013_03_102401
Figure 3: AC Load Circuit
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
+3.0V
0V
90%
10%
T
T
L
R
1.5 ns
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
1
2
4
8
16
Number of Adjacent Outputs Switching
DS017_05_042800
DS013_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
5
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Pin Descriptions
Function Macro-
Table 2: XCR3256XL User I/O Pins
Block
cell
TQ144 PQ208 FT256
CS280
H17
H18
H19
J16
J17
-
TQ144 PQ208 FT256 CS280
3
1
98
17
18
19
20
21
-
G15
G13
F16
G14
G16
-
Total User I/O Pins
120
164
164
164
3
2
97
3
3
96
Table 3: XCR3256XL I/O Pins
3
4
94
Function Macro-
3
5
93
Block
cell
TQ144 PQ208 FT256
CS280
E18
E19
F15
F17
F18
-
3
6
-
1
1
106
-
6
7
C16
F12
D16
E14
E15
-
3
7
-
-
-
-
1
2
(1)
3
8
-
-
-
-
1
3
104
8
3
9
-
-
-
-
1
4
103
9
3
10
11
12
13
14
15
16
1
-
-
-
-
1
5
102
10
-
3
-
92
-
-
-
-
1
6
-
3
22
24
25
26
27
197
196
195
194
193
-
H13
H12
H15
H14
H16
D11
A11
E10
B12
C11
-
J18
K16
K17
K18
L16
E14
D14
A14
C13
B13
-
1
7
-
-
-
-
3
1
8
-
-
-
-
3
91
90
-
1
9
-
-
-
-
3
1
10
11
12
13
14
15
16
1
-
-
-
-
3
1
-
-
-
-
4
114
116
117
-
1
101
11
12
13
15
16
4
F13
E16
F14
F15
G12
E13
D15
C13
A14
E11
-
F19
G16
G17
G19
H16
B19
B18
B17
A18
A17
-
4
2
1
100
4
3
1
99
4
4
1
-
4
5
118
-
1
-
4
6
2
107
4
7
-
-
-
-
2
2
108
3
4
8
-
-
-
-
2
3
-
206
205
204
-
4
9
-
-
-
-
2
4
-
4
10
11
12
13
14
15
16
1
-
-
-
-
2
5
109
4
-
-
-
-
2
6
-
4
119
120
121
-
192
190
B11
A10
A13
A12
2
7
-
-
-
-
4
2
8
-
-
-
-
-
(1)
(1)
(1)
4
189
C10
A9
C12
2
9
-
-
-
4
188
187
28
B12
D12
L17
L18
2
10
11
12
13
14
15
16
-
-
-
-
4
122
D9
2
-
-
-
-
(1)
5
89
J14
J15
2
110
111
-
203
202
201
199
198
A13
D12
B13
C12
A12
C16
A16
E15
D15
A15
5
2
-
29
2
(1)
(1)
(1)
5
3
88
87
86
30
J13
J16
L14
L19
2
5
4
31
33
M16
M18
2
112
113
5
5
2
6
www.xilinx.com
1-800-255-7778
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
cell
TQ144 PQ208 FT256
CS280
Block
cell
11
12
13
14
15
16
1
TQ144 PQ208 FT256
CS280
-
5
6
-
-
-
-
-
-
-
-
7
-
-
45
46
47
48
49
65
64
62
61
60
-
-
M16
M14
N16
L12
P15
T12
R12
N11
T13
P12
-
5
7
7
77
R17
R15
T17
T16
U19
T13
W14
T14
R14
W15
-
5
8
-
-
-
-
7
-
5
9
-
-
-
-
7
75
5
10
11
12
13
14
15
16
1
-
-
-
-
7
74
5
-
-
-
-
7
-
5
84
-
34
35
36
37
38
78
77
76
73
71
-
K15
K14
K16
K13
L15
R9
N9
T10
P10
R10
-
M17
N16
N19
N18
N17
U10
T10
W11
U11
T11
-
8
66
5
8
2
67
5
83
82
-
8
3
68
5
8
4
69
5
8
5
-
6
-
8
6
-
6
2
55
56
-
8
7
-
-
-
-
6
3
8
8
-
-
-
-
6
4
8
9
-
-
-
-
6
5
60
-
8
10
11
12
13
14
15
16
1
-
-
-
-
6
6
8
-
-
-
-
6
7
-
-
-
-
8
70
59
58
57
56
55
153
154
159
160
161
-
R13
M11
T14
N12
R14
D3
C1
B4
E6
A4
-
U15
V15
T15
V16
W17
B1
C3
A4
B5
C5
-
6
8
-
-
-
-
8
-
6
9
-
-
-
-
8
71
6
10
11
12
13
14
15
16
1
-
-
-
-
8
-
6
-
-
-
-
8
72
6
61
62
63
-
70
69
68
67
66
39
40
42
43
44
-
T11
N10
P11
M10
R11
K12
L16
M15
N15
L13
-
W12
U12
T12
V13
U13
P16
P18
R19
R16
R18
-
9
2
6
9
2
1
6
9
3
-
6
9
4
-
6
65
81
-
9
5
143
7
9
6
-
7
2
9
7
-
-
-
-
7
3
80
79
78
-
9
8
-
-
-
-
7
4
9
9
-
-
-
-
-
7
5
9
10
11
12
13
14
15
-
-
-
7
6
9
-
-
-
-
7
7
-
-
-
-
9
-
162
163
164
166
C5
B5
D6
A5
A5
E6
D6
B6
7
8
-
-
-
-
9
142
141
140
7
9
-
-
-
-
9
7
10
-
-
-
-
9
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
7
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
cell
16
1
TQ144 PQ208 FT256
CS280
A6
D2
D1
E3
E2
E4
-
Block
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
cell
TQ144 PQ208 FT256
CS280
H3
-
9
139
167
151
150
149
148
147
-
C6
D1
E4
D2
E3
E1
-
5
15
-
136
-
H4
-
(1)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
4
6
2
-
7
-
-
-
-
3
5
8
-
-
-
-
4
6
9
-
-
-
-
5
7
10
11
12
13
14
15
16
1
-
-
-
-
6
-
-
-
-
-
7
-
-
-
-
16
-
135
133
132
131
130
79
80
81
84
86
-
G2
J1
J3
H2
J5
P9
T9
P8
R8
N8
-
H2
J2
J3
K2
K3
W10
T9
U9
T8
T7
-
8
-
-
-
-
9
-
-
-
-
18
19
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
8
146
145
144
142
141
168
169
170
171
172
-
F4
F1
G5
E2
F3
B6
E7
A6
D7
B7
-
E1
F5
F3
F4
G3
D7
C7
B7
A7
C8
-
-
-
2
54
53
-
9
3
10
4
11
5
49
-
-
6
2
-
7
-
-
-
-
3
138
8
-
-
-
-
4
-
9
-
-
-
-
5
137
10
11
12
13
14
15
16
1
-
-
-
-
6
-
-
-
-
-
-
7
-
-
-
48
47
46
-
87
88
89
90
91
129
128
T8
P7
R7
P6
T7
J2
J4
W7
V7
U7
W6
T6
K4
L1
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
45
(1)
136
134
133
132
131
-
173
175
C7
C8
B8
C9
20
2
-
21
22
23
-
(1)
(1)
(1)
(1)
(1)
(1)
176
A7
B9
3
127
K1
L2
177
178
140
139
138
137
D8
B8
F2
G4
G1
H1
D10
C10
G2
4
126
K3
L3
5
124
K2
M1
6
-
-
-
-
-
-
-
-
-
-
-
-
2
-
G1
7
-
3
12
14
G4
8
-
4
H1
9
-
8
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Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Table 3: XCR3256XL I/O Pins (Continued)
Table 3: XCR3256XL I/O Pins (Continued)
Function Macro-
Function Macro-
Block
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
cell
10
11
12
13
14
15
16
1
TQ144 PQ208 FT256
CS280
-
Block
cell
TQ144 PQ208 FT256
CS280
V1
-
-
-
-
-
16
15
35
36
109
108
N3
T1
-
-
16
16
U2
25
-
123
122
121
120
119
92
93
95
96
97
-
L1
K4
L3
K5
M1
N7
R6
M7
T5
T6
-
M3
M4
N1
N2
N3
V6
U6
R6
W5
T5
-
Notes:
1. JTAG pins.
26
27
28
44
43
42
41
40
-
2
3
4
5
6
7
-
-
-
-
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
15
16
1
-
-
-
-
-
-
-
-
-
98
99
100
101
102
118
117
115
114
113
-
R5
N6
T4
P5
R4
L2
M2
M3
N2
L5
-
V5
U5
W4
U4
W3
P1
P2
P4
R3
R2
-
39
38
-
37
-
2
-
3
29
30
31
-
4
5
6
7
-
-
-
-
8
-
-
-
-
9
-
-
-
-
10
11
12
13
14
-
-
-
-
-
-
-
-
32
-
112
111
110
P1
M4
R1
R4
T3
U1
34
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
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9
R
XCR3256XL 256 Macrocell CPLD
Table 4: XCR3256XL Global, JTAG, Port Enable, Power, and No Connect Pins
Pin Type
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
TCK
TQ144
128
127
126
125
89
PQ208
181
182
183
184
30
FT256
B9
CS280
A10
D11
C11
B11
L19
B9
A8
C9
B10
J13
A7
TDI
4
176
189
127
TDO
104
20
C10
K1
C12
L2
TMS
(1)
(1)
(1)
(1)
PORT_EN
Vcc
13
116
N1
P3
24, 50, 51, 58, 73, 76, 5, 23, 41, 63, 74, 83, 85, E8, E9, F7, F8, F9, F10,
A11, B10, C6, C14,
95, 115, 123, 130, 144
107, 125, 143, 165,
179, 186, 191
G6, G11, H5, H6, H11, D13, D17, F2, J19, L4,
J6, J11, J12, K6, K11, P15, T18, U8, U14, V2,
L7, L8, L9, L10, M8, M9
V9, V11
GND
3, 17, 33, 52, 57, 59, 64, 14, 32, 50, 72, 75, 82,
85, 105, 124, 129, 135 94, 134, 152, 174, 180,
185, 200
E5, F6, F11, G7, G8,
G9, G10, H7, H8, H9,
H10, J7, J8, J9, J10, K7, G15, H5, H15, J5, J15,
E5, E7, E8, E9, E10,
E11, E12, E13, G5,
K8, K9, K10, L6, L11
K5, K15, L5, L15, M5,
M15, N5, N15, R7, R8,
R9, R10, R11, R12,
R13
No Connects
-
1, 2, 51, 52, 53, 54, 103, A1, A2, A3, A15, A16,
104, 105, 106, 155, B1, B2, B3, B14, B15,
A1, A2, A3, A8, A9,
A19, B2, B3, B4, B14,
156, 157, 158, 207, 208 B16, C2, C3, C4, C14, B15, B16, C1, C2, C4,
C15, D4, D5, D10, D13,
D14, E12, F5, G3, H3,
L4, M5, M6, M12, M13,
C15, C17, C18, C19,
D3, D4, D5, D8, D9,
D16, D18, D19, E16,
N4, N5, N13, N14, P2, E17, F1, F16, G18, H4,
P3, P4, P13, P14, P16, J1, J4, K1, K19, M2,
R2, R3, R15, R16, T2, M19, N4, P5, P17, P19,
T3, T15, T16
R1, R5, T1, T2, T4, T19,
U3, U16, U17, U18, V3,
V4, V8, V10, V12, V14,
V17, V18, V19, W1,
W2, W8, W9, W13,
W16, W18, W19
Notes:
1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full
explanation.
10
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DS013 (v1.9) January 8, 2002
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Preliminary Product Specification
R
XCR3256XL 256 Macrocell CPLD
Ordering Information
Example:
XCR3256XL -7 PQ 208 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Speed
Package
Temperature
T = 0°C to + 70°C
-12 12 ns pin-to-pin delay
TQ144 144-pin Thin Quad Flat Pack
C = Commercial
I = Industrial
A
V
= 3.0V to 3.6V
CC
-10 10 ns pin-to-pin delay
-7 7.5 ns pin-to-pin delay
PQ208 208-pin Plastic Quad Flat Package
FT256 256-ball Fine-Pitch Ball Grid Array
T = –40°C to +85°C
A
V
= 2.7V to 3.6V
CC
CS280 280-ball Chip Scale Package
Component Compatibility
Pins
144
208
256
280
Type
Plastic TQFP
Plastic PQFP
Plastic FBGA
Plastic BGA
Code
TQ144
C
PQ208
C
FT256
C
CS280
C
XCR3256XL
-7
-10
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
Revision History
The following table shows the revision history for this document
Date
Version
1.0
Revision
01/21/00
02/10/00
05/03/00
11/20/00
12/11/00
01/17/01
03/05/01
Initial Xilinx release.
Updated Pinout table.
1.1
1.2
Minor updates and added Boundary Scan to pinout table.
1.3
Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High".
Updated specifications and pinout tables.
1.4
1.5
Removed Timing Model.
1.6
Added 256-ball Fine-Pitch Ball Grid Array Package.
DS013 (v1.9) January 8, 2002
www.xilinx.com
11
Preliminary Product Specification
1-800-255-7778
R
XCR3256XL 256 Macrocell CPLD
Date
Version
1.7
Revision
04/11/01
04/19/01
01/08/02
Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed V spec.
OH
1.8
Updated Typical I/V curve, Figure 2: added voltage levels.
1.9
Moved ICC vs Freq. Figure 1 and Table 1 to page 1. Added single p-term setup time (T
)
SU1
to AC Table, renamed T to T
for setup time through the OR array. Updated T
spec
SU
SU2
SUF
to match software timing. Added T
spec. Updated T
spec. Updated T spec to
INIT
CONFIG HI
correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for T delay measurement.
POD
12
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DS013 (v1.9) January 8, 2002
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Preliminary Product Specification
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