XCR3320-10TQ144C_技术文档

APPLICATION NOTE

0

R

XCR3320: 320 Macrocell SRAM

CPLD

0

14*

DS033 (v1.1) February 10, 2000

Product Specification

nique is also what allows Xilinx to offer a true CPLD archi-

tecture in a high density device.

Features

•

320 macrocell SRAM based CPLD

Configuration times of under 1.0 second

IEEE 1149.1 compliant JTAG testing capability

The Xilinx XCR3320 devices use the patented XPLA2

(eXtended Programmable Logic Array) architecture. This

architecture combines the best features of both PAL- and

PLA-type logic structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA2 architecture

is constructed from 80 macrocell Fast Modules that are

connected together by an interconnect array. Within each

Fast Module are four Logic Blocks of 20 macrocells each.

Each Logic Block contains a PAL structure with four dedi-

cated product terms for each macrocell. In addition, each

Logic Block has 32 additional product terms in a PLA struc-

ture that can be shared through a fully programmable OR

array to any of the 20 macrocells. This combination effi-

ciently allocates logic throughout the Logic Block, which

increases device density and allows for design changes

without re-defining the pinout or changing the system tim-

ing. The XCR3320 offers pin-to-pin propagation delays of

7.5 ns through the PAL array of a Fast Module; and if the

PLA array is used, an additional 1.5 ns is added to the

delay, no matter how many PLA product terms are used. If

the interconnect array between Fast Modules is used, there

is a second fixed delay of 2.0 ns. This means that the worst

case pin-to-pin propagation delay within a fast module is

7.5 + 1.5 = 9.0 ns, and the delay from any pin to any other

pin across the entire chip is 7.5 + 2.0 = 9.5 ns if only the

PAL array is used, and 7.5 + 1.5 + 2.0 = 11.0 ns if the PLA

array is used.

-

Five pin JTAG interface

IEEE 1149.1 TAP controller

•

In system configurable

3.3V device with 5V tolerant I/O

Innovative XPLA2 Architecture combines extreme

flexibility and high speeds

•

Eight synchronous clock networks with programmable

polarity at every macrocell

Up to 32 asynchronous clocks support complex

clocking needs

Innovative XOR structure at every macrocell provides

excellent logic reduction capability

Logic expandable to 36 product terms on a single

macrocell

•

Advanced 0.35µ SRAM process

Design entry and verification using industry standard

and Xilinx CAE tools

•

Control Term structure provides either sum terms or

product terms in each logic block for:

-

3-state buffer control

Asynchronous macrocell register reset/preset

•

Global 3-state pin facilitates "bed of nails" testing

without sacrificing logic resources

Programmable slew rate control

Small form factor packages with high I/O counts

Available in commercial and industrial temperature

ranges

•

Each macrocell also has a two input XOR gate with the

dedicated PAL product terms on one input and the PLA

product terms on the other input. This patent-pending Ver-

satile XOR structure allows for very efficient logic optimiza-

tion compared to competing XOR structures that have only

one product term as the second input to the XOR gate. The

Versatile XOR allows an 8-bit XOR function to be imple-

mented in only 20 product terms, compared to 65 product

terms for the traditional XOR approach.

Description

The XCR3320 device is a member of the CoolRunner™

family of high-density SRAM-based CPLDs (Complex Pro-

grammable Logic Device) from Xilinx. This device com-

bines high speed and deterministic pin-to-pin timing with

high density. The XCR3320 uses the patented Fast Zero

Power (FZP™) design technique that combines high speed

and low power for the first time ever in a CPLD. FZP allows

the XCR3320 to have true pin-to-pin timing delays of 7.5 ns,

and standby currents of 100 µA without the need for `turbo

bits' or other power down schemes. By replacing conven-

tional sense amplifier methods for implementing product

terms (a technique that has been used since the bipolar

era) with a cascaded chain of pure CMOS gates, both

standby and dynamic power are dramatically reduced

when compared to other CPLDs. The FZP design tech-

The XCR3320 is SRAM-based, which means that it is con-

figured from an external source at power up. See the con-

figuration section of this data sheet for more information.

The device supports the full JTAG specification (IEEE

1149.1) through an industry standard JTAG interface. It can

also be configured through the JTAG port, which is very

useful for prototyping. See section titled “Device Configura-

tion Through JTAG” on page 29 for more information.

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

1

R

XCR3320: 320 Macrocell SRAM CPLD

The XCR3320 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-

opsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool including WebFITTER.

called the Global Zero Power Interconnect Array (GZIA).

Each Fast Module accepts 64 bits from the GZIA and out-

puts 64 bits to the GZIA. Each Fast Module is essentially an

80 macrocell CPLD with four logic blocks of 20 macrocells

each inside. There are eight dedicated, low-skew, global

clocks for the device; and each Fast Module has access to

any two of these clocks (there are additional asynchronous

clocks available in the Fast Modules, see Figure 3. There

are also Global 3-state (gts) and Global Reset (rstn) pins

that are common to all Fast Modules. When gts is pulled

high, all output buffers in the device will be disabled, caus-

ing all I/O pins to be tri-stated. When rstn is pulled low, all

flip-flops of the device will be reset.

XPLA2 Architecture

Figure 1 shows a high level block diagram of the XCR3320

implementing the XPLA2 architecture. The XPLA2 archi-

tecture is a multi-level, modular hierarchy that consists of

Fast Modules interconnected by a virtual crosspoint switch

V

CC

cclk

din

cclk

din

cclk

din

cclk

dout

V

CC

V

CC

MASTER SERIAL

LEAD

SLAVE #1

SLAVE #2

EEPROM

pgrmn

resetn

pgrmn

resetn

pgrmn

resetn

done

reset/OE

CE

V

CC

crcerrn

hdc

crcerrn

hdc

crcerrn

hdc

M3

M2

M1

M0

M3

M2

M1

M0

M3

M2

M1

M0

SP00665

Figure 1: Xilinx XPLA2 CPLD Architecture

DS033 (v1.1) February 10, 2000

www.xilinx.com

2

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

XPLA2 Fast Module

is a virtual crosspoint switch that connects the Logic Blocks

to each other and to the GZIA. The feedback from all 80

macrocells, input from the I/O pins, and the 64 bit input bus

from the GZIA are input into the LZIA. The LZIA outputs 36

signals into each Logic Block and 64 signals into the GZIA

(Figure 2).

Each Fast Module consists of four Logic Blocks of 20 mac-

rocells each. Depending on the package, either seven or 12

of the 20 macrocells in each Logic Block are connected to

I/O pins, and the remaining macrocells are used as buried

nodes. These four Logic Blocks are connected together by

the Local Zero Power Interconnect Array (LZIA). The LZIA

MC0

MC1

36

20

36

20

LOGIC

BLOCK

LOGIC

BLOCK

I/O

MC19

LZIA

MC0

MC1

MC0

MC1

36

20

36

20

LOGIC

BLOCK

LOGIC

BLOCK

I/O

MC19

64

SP00656

Figure 2: Xilinx XPLA2 Fast Module

sists of a programmable AND array with a programmable

OR array.

XPLA2 Logic Block Architecture

Figure 3 illustrates the XPLA2 Logic Block architecture.

Each Logic Block contains eight control terms, a PAL array,

a PLA array, and 20 macrocells. The 36 inputs from the

LZIA are available to all control terms and to each product

term in both the PAL and the PLA array. The eight control

terms can individually be configured as either SUM or

PRODUCT terms, and are used to control the asynchro-

nous preset and reset functions of the macrocell registers,

the output enables of the 20 macrocells, and for asynchro-

nous clocking. The PAL array consists of a programmable

AND array with a fixed OR array, while the PLA array con-

Each macrocell has four dedicated product terms from the

PAL array. When additional logic is required, each macro-

cell takes the extra product terms from the PLA array. The

PLA array consists of 32 extra product terms that are

shared between the 20 macrocells of the Logic Block. The

PAL product terms can be connected to the PLA product

terms through either an OR gate or an XOR gate. One input

to the XOR gate can be connected to all the PLA terms,

which provides for extremely efficient logic synthesis. An

eight bit XOR function can be implemented in only 20 prod-

uct terms. Each macrocell can use the output from the OR

gate or the XOR gate in either normal or inverted state.

3

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

LZIA

INPUTS

36

8

CONTROL

4

MC0

MC1

MC2

PAL

ARRAY

4

MC19

PLA

ARRAY

(32)

PATENT PENDING

SP00589A

Figure 3: Xilinx XPLA2 Logic Block Architecture

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

4

R

XCR3320: 320 Macrocell SRAM CPLD

XPLA2 Macrocell Architecture

applied, and that the preset/reset feature for each macro-

cell can also be disabled. Each macrocell can choose

between an asynchronous reset or an asynchronous pre-

set function, but both cannot be simultaneously used on the

same register. The global rstn function can always be used,

regardless of whether or not asynchronous reset or preset

control terms are enabled. Control terms CT2, CT3, CT4

and CT5 are used to enable or disable the macrocell's out-

put buffer. The output buffers can also be always enabled or

always disabled. All CoolRunner devices also provide a

Global 3-state (GTS) pin, which, when pulled high, will

3-state all the outputs of the device. This pin is provided to

support "In-Circuit Testin" or "Bed-of-Nails" testing used

during manufacturing.

Figure 4 shows the XPLA2 macrocell architecture used in

the XCR3320. The macrocell can be configured as either a

D- or T-type flip-flop or a combinatorial logic function. A

D-type flip-flop is generally more useful for implementing

state machines and data buffering while a T-type flip-flop is

generally more useful in implementing counters. Each of

these flip-flops can be clocked from any one of four

sources. Two of the clock sources (CLK0 and CLK1) are

from the eight dedicated, low-skew, global clock networks

designed to preserve the integrity of the clock signal by

reducing skew between rising and falling edges. These

clocks are designated as "synchronous" clocks and must

be driven by an external source. Both CLK0 and CLK1 can

clock the macrocell flip-flops on either the rising edge or the

falling edge of the clock signal. The other clock sources are

designated as "asynchronous" and are connected to two of

the eight control terms (CT6 and CT7) provided in each

logic block. These clocks can be individually configured as

any PRODUCT term or SUM term equation created from

the 36 signals available inside the logic block. Thus, in each

Logic Block, there are up to four possible clocks; and in

each Fast Module, there are up to ten possible clocks.

Throughout the entire device, there are up to 40 possible

clocks–eight from the dedicated, low-skew, global clocks,

and two for each of the 16 logic blocks.

For the macrocells in the Logic Block that are associated

with I/O pins, there are two feedback paths to the LZIA: one

from the macrocell, and one from the I/O pin. The LZIA

feedback path before the output buffer is the macrocell

feedback path, while the LZIA feedback path after the out-

put buffer is the I/O pin feedback path. When these macro-

cells are used as outputs, the output buffer is enabled, and

either feedback path can be used to feedback the logic

implemented in the macrocell. When the I/O pins are used

as inputs, the output buffer of these macrocells will be

3-stated and the input signal will be fed into the LZIA via the

I/O feedback path. In this case the logic functions imple-

mented in the buried macrocell can be fed back into the

LZIA via the macrocell feedback path. For macrocells that

are not associated with I/O pins, there is one feedback path

to the LZIA. Logic functions implemented in these buried

macrocells are fed back into the LZIA via this path. All

unused inputs and I/O pins should be properly terminated.

Please refer to “Terminations” on page 8.

The remaining six control terms of each logic block

(CT0-CT5) are used to control the asynchronous pre-

set/reset of the flip-flops and the enable/disable of the out-

put buffers in each macrocell. Control terms CT0 and CT1

are used to control the asynchronous preset/reset of the

macrocell's flip-flop. Note that the power-on reset leaves all

macrocells in the "zero" state when power is properly

TO LZIA

D/T

Q

gts

INIT*

CLK0

GND

CT0

CT1

CT2

CT3

CT4

CT5

CLK1

CT6

GND

CT7

V

CC

GND

rstn

SP00590

*SEE XPLA2 MACROCELL ARCHITECTURE DESCRIPTION

Figure 4: XCR3320 Macrocell Architecture

5

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

PAL array in a Fast Module, and there are fixed delays

added for use of the PLA array or the GZIA. The t_CO

(pin-to-pin) timing specification never changes. For exam-

ple, a combinatorial logic function of four or fewer product

terms constructed from inputs within the same logic block

would have a t_PDdelay of 7.5 ns. If the logic function were

more than four product terms wide, the delay would be t_PD

plus the fixed PLA delay, or 7.5 +1.5 = 9.0 ns. A function

that used the PAL array and inputs from a different Fast

Module would have a propagation delay of t_PDplus the

fixed GZIA delay, or 7.5 + 2.0 = 9.5 ns.

Simple Timing Model

Figure 5 shows the XCR3320 timing model. The XCR3320

timing model is very simple compared to the models of

competing architectures. There are three main timing

parameters: the pin-to-pin delay for combinatorial logic

functions (t_PD), the input pin to register set up time (t_SU),

and the register clock to valid output time (t_CO). As the

model shows, timing is only dependent on whether or not

the PLA array is used, and whether or not the logic function

is created within a single Fast Module or uses the GZIA.

The timing starts with a set time for t_PDand t_SUthrough the

Within a Fast Module:

t

= COMBINATORIAL PAL

PD_PAL

t

= COMBINATORIAL PAL + PLA

PD_PLA

INPUT PIN

OUTPUT PIN

REGISTERED

t

= PAL

= PAL + PLA

REGISTERED

SU_PAL

t

SU_PLA

CO

INPUT PIN

D

Q

GLOBAL CLOCK PIN

Using the Global ZIA:

t

= COMBINATORIAL PAL + GZD

PD_PAL

t

= COMBINATORIAL PAL + PLA ,+ GZD

PD_PLA

INPUT PIN

OUTPUT PIN

REGISTERED

= PAL + GZD

t

REGISTERED

SU_PAL

t

= PAL + PLA + GZD

t

SU_PLA

CO

INPUT PIN

D

Q

OUTPUT PIN

SP00591B

GLOBAL CLOCK PIN

Figure 5: XCR3320 Timing Module

DS033 (v1.1) February 10, 2000

www.xilinx.com

6

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

both high performance and low power, breaking the para-

digm that to have low power, you must have low perfor-

mance. This also makes it possible to manufacture high

density CPLDs like the XCR3320 that consume a fraction

of the power of competing devices. Refer to Figure 6 and

Table 1 showing the I_CCvs. Frequency of the XCR3320

TotalCMOS CPLD (data taken with 20 16-bit counters at

3.3V, 25°C, output buffers disabled).

TotalCMOS Design Technique for Fast Zero

Power

Xilinx is the first to offer a TotalCMOS CPLD, both in pro-

cess technology and design technique. Xilinx employs a

cascade of CMOS gates to implement its product terms

instead of the traditional sense amp approach. This CMOS

gate implementation allows Xilinx to offer CPLDs which are

200

180

160

140

120

I

CC

100

80

60

40

20

(mA)

0

20

40

60

80

100

120

FREQUENCY (MHz)

SP00657

Figure 6: I_CCvs. Frequency at V_CC= 3.3V, 25°C

Table 1: I_CCvs. Frequency (V_CC= 3.3V, 25°C)

Frequency (MHz)

0

1

20

40

60

77

80

100

120

Typical I_CC(mA)

0.01

1.3

26

51

102

126

152

7

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

come close to ground, which could cause the device to

enter JTAG/ISP mode at unspecified times.

Terminations

The CoolRunner XCR3320 CPLDs are TotalCMOS™

devices. As with other CMOS devices, it is important to

consider how to properly terminate unused inputs and I/O

pins when fabricating a PC board. Allowing unused inputs

and I/O pins to float can cause the voltage to be in the linear

region of the CMOS input structures, which can increase

the power consumption of the device. It can also cause the

voltage on a configuration pin to float to an unwanted volt-

age level, interrupting device operation.

Configuration Introduction

The Xilinx CoolRunner series are available in technologies

which use non-volatile (EEPROM-based) and volatile

(SRAM based) configuration memory. The functionality of

the XPLA2 family of the CoolRunner series is defined by

on-chip SRAM. The devices are configured in a manner

similar to that of most FPGAs. This section describes the

configuration of the XCR3320, and applies to all similarly

configured devices to be produced by Xilinx.

The XCR3320 CPLDs have programmable on-chip

pull-down resistors on each I/O pin. These pull-downs are

automatically activated by the fitter software for all unused

I/O pins. Note that an I/O macrocell used as buried logic

that does not have the I/O pin used for input is considered

to be unused, and the pull-down resistors will be turned on.

We recommend that any unused I/O pins on the XCR3320

device be left unconnected.

Either Xilinx or third party software is used to generate a

JEDEC file. The JEDEC file contains the configuration

data, which is loaded into the XCR3320 configuration

memory to control the XCR3320 functionality. This is done

at power-up and/or with configure command. This section

provides some of the trade-offs in selecting a configuration

mode, and provides debug hints for configuration problems.

There are no on-chip pull-down structures associated with

dedicated pins used for device configuration or special

device functions like global reset and global 3-state. Xilinx

recommends that these pins be terminated consistent with

pin functionality. Xilinx recommends the use of weak

pull-up and pull-down resistors for terminating these pins.

See the appropriate configuration section for more informa-

tion on terminating dedicated pins.

There are several different methods of configuring the

XCR3320. The mode used is selected using the mode

select pins. There are three basic configuration methods:

master, slave, and peripheral. The configuration data can

be transmitted to the XCR3320 serially or in parallel bytes.

As a master, the XCR3320 generates the clock and control

signals to strobe configuration data into the XCR3320. As a

slave device, a clock is generated externally, and provided

into the XCR3320s cclk pin. In the peripheral mode, the

XCR3320 interfaces as a microprocessor peripheral.

Please note that M3 should always be High. Table 2 lists

the states for the other mode pins by configuration mode.

When using the JTAG Boundary Scan functions, it is rec-

ommended that 10kΩ pull-up resistors be used on the tdi,

tms, tck, and trstn pins. The tdo signal pin can be left float-

ing unless it is connected to the tdi of another device. Let-

ting these signals float can cause the voltage on tms to

Table 2: Configuration Modes

M2

0

M1

0

M0

0

Cclk

Output

Input

Configuration Mode

Data Format

Serial

Master serial

Slave parallel

0

1

Parallel

0

1

0

Reserved

0

1

Input

Synchronous peripheral

Master parallel - up

Parallel

1

0

Output

1

0

1

Reserved

1

0

1

Input

Slave serial

Serial

DS033 (v1.1) February 10, 2000

www.xilinx.com

8

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Design Flow Overview

configuration data from a PC or workstation hard disk into

the XCR3320. Alternately, the XCR3320 can be loaded

from non-volatile ICs such as serial or parallel EEPROMs,

after converting the JEDEC file to an MCS file using the

jed2mcsutility.

Figure 7 is a diagram of the steps used in configuring the

XCR3320. The development system is used to generate

configuration data in the JEDEC file. Using the

<design>.jedfile, there are two general methods of con-

figuring the XCR3320. The utility download can load the

DESIGN COMPILATION AND FIT

jed

jed2mcs

download

PROM PROGRAMMER

SLAVE SERIAL CONFIGURATION

SP00676

Figure 7: Design Flow

9

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

complete when the internal length count equals the loaded

length count in the length count field, and the required end

of configuration frame is written.

XCR3320 States Of Operation

Prior to becoming operational, the XCR3320 goes through

a sequence of states, including initialization, configuration,

and start-up. This section discusses these three states. In

the master configuration modes, the XCR3320 is the

source of configuration clock (cclk).

All configuration I/Os used as inputs operate with TTL-level

input thresholds during configuration. All I/Os that are not

used during the configuration process are 3-stated with

internal pull-downs. During configuration, registers are

reset. The combinatorial logic begins to function as the

XCR3320 is configured. Figure 6 shows the flow between

the initialization, configuration, and start-up states. Figure 9

gives the general timing information for configuring the

device.

When configuration is initiated, a counter in the XCR3320

is set to zero and begins to count configuration clock cycles

applied to the XCR3320. As each configuration data frame

is supplied to the XCR3320, it is internally assembled into

data words. Each data word is loaded into the internal con-

figuration memory. The configuration loading process is

POWER-UP

POWER-ON TIME DELAY

crcerrn HIGH

–

INITIALIZATION

–

hdc LOW, ldcn HIGH

done LOW

resetn

OR

prgmn

crcerrn LOW

YES

LOW

NO

CONFIGURATION

–

M[3:0] MODE IS SELECTED

resetn

OR

prgmn

CRC

ERROR

CONFIGURATION DATA FRAME WRITTEN

hdc HIGH, ldcn LOW

LOW

dout ACTIVE

crcerrn HIGH, done LOW

DEVICE CONFIGURATION COMPLETE

done RELEASED

–

dout ACTIVE

NO

done

HIGH

YES

START-UP

prgmn

LOW

–

ALL MACROCELL FF’S ARE RESET

OPERATION

I/O BECOMES ACTIVE

SP00622

Figure 8: Chart Of Initialization, Configuration, and Operating States

DS033 (v1.1) February 10, 2000

www.xilinx.com

10

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

V

DD

t

pord

t

PW

prgmn

t

r

crcerrn

resetn

t

cclk

t

smode

M[3:0]

t

CL

I/O active

done

hdc

t

IL

ldcn

INITIALIZATION

CONFIGURATION

START UP

OPERATIONAL

SP00652

Figure 9: General Configuration Mode Timing Diagram

11

www.xilinx.com

1-800-255-7778

DS033 (v1.1) February 10, 2000

R

XCR3320: 320 Macrocell SRAM CPLD

Table 3: General Configuration Mode Timing Characteristics

Symbol

Parameter

Min.

Max.

Unit

All Configuration Modes

t_SMODE

t_HMODE

t_PW

M[3:0] setup time to prgmn high

M[3:0] hold time from done high

0

-

ns

ms

ns

10

50

prgmn pulse width low

Global 3-state disable

-

t_gtsr

40

700

t_IL

Initialization latency (prgmn high to hdc high)

XCR3320

M3 = 1

250

t_PORD

t_r

Master Modes

t_CCLKcclk period

t_CL

Power-on reset delay

1

-

ms

Configuration signal rise time

1.0

M3 = 1

714

135

1667

316

ns

Configuration latency (non-compressed)

XCR3320

ms

Slave Serial, Slave Parallel, And Synchronous Peripheral Modes

t_CCLK

cclk period

Single device

Daisy-chain

Single device

Daisy-chain

100

1000

19

-

ns

t_CL

Configuration latency (non-compressed)

XCR3320

ms

189

tion state. The resetn and prgmn pins must be high before

the XCR3320 will enter the configuration state, and the

mode pins must be stable t_SMODEnanoseconds before they

rise. During the start-up and operating states, only the

assertion of prgmn causes a reconfiguration.

Initialization

Upon power-up, the device goes through an initialization

process. First, an internal power-on-reset circuit is trig-

gered when power is applied. When V_CCreaches the volt-

age at which portions of the XCR3320 begin to operate

(1.5V), the configuration pins are set to be inputs or outputs

based on the configuration mode, as determined by the

mode select inputs M[2:0]. The mode pins must be stable

t_SMODEnanoseconds before the rising edge of prgmn or

resetn. A time-out delay is initiated when V_CCreaches

between 1.0V and 2.0V to allow the power supply voltage to

stabilize. The done output is low. At power-up, if the power

supply does not rise from 1.0V to V_CCin less than 25 ms,

the user should delay configuration by inputting a low into

prgmn or resetn until V_CCis greater than the recommended

minimum operating voltage (3.0V for commercial devices).

If prgmn has a rise time of greater than one microsecond,

resetn must be held low until after prgmn goes high. If the

rise time for prgmn is 1 ms or less, the order in which these

pins go high is arbitrary.

During initialization and configuration, all I/O’s are 3-stated

and the internal weak pull-downs are active. See “Termina-

tions” on page 8 for more information.

Start-up

After configuration, the XCR3320 enters the start-up

phase. This phase is the transition between the configura-

tion and operational states. This transition occurs within

three cclk cycles of the done pin going high (it is acceptable

to have additional cclk cycles beyond the three required).

The system design task in the start-up phase is to ensure

that multi-function pins (See “230-pin Function Table” on

page 36.) transition from configuration signals to user

definable I/Os without inadvertently activating devices in

the system or causing bus contention. The done signal

goes High at the beginning of the start up phase, which

allows configuration sources to be disconnected so that

there is no bus contention when the I/Os become active. In

addition to controlling the XCR3320 during start-up, addi-

tional start-up techniques to avoid contention include using

isolation devices between the XCR3320 and other circuits

in the system, re-assigning I/O locations, and keeping I/Os

3-stated until contentions are resolved. For example,

Figure 10 shows how to use the Global 3-state (GTS) sig-

nal to avoid signal contention when any multi-function pins

The High During Configuration (hdc), Low During Configu-

ration (ldcn), and done signals are active outputs in the

XCR3320’s initialization and configuration states. hdc, ldcn,

and done can be used to provide control of external logic

signals such as reset, bus enable, or EEPROM enable dur-

ing configuration. For master parallel configuration mode,

these signals provide EEPROM enable control and allow

the data pins to be shared with user logic signals.

If configuration has begun, an assertion of resetn or prgmn

initiates an abort, returning the XCR3320 to the initializa-

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

12

R

XCR3320: 320 Macrocell SRAM CPLD

V

DD

t

pord

t

PW

prgmn

t

r

crcerrn

resetn

cclk

t

smode

t

smode

M[3:0]

t

CL

I/O active

t

gtsh

gtsr

GTS

done

hdc

t

HMODE

t

IL

ldcn

INITIALIZATION

CONFIGURATION

START UP

OPERATIONAL

INITIALIZATION

SP00653

Figure 10: Using GTS Signal with Power Up to Avoid Signal Contention with Multi-function Pins Used as I/O

are used as I/O after configuration is finished. Holding gts

high until after the multi-function pins are disconnected

from the driving source allows these pins to transition from

configuration pins to user definable I/O without signal con-

tention. In this case, the I/O become active a t_GTSRdelay

after the gts pin is pulled low.

The flip-flops are reset one cycle after done goes high so

that operation begins in a known state. The done outputs

from multiple XCR3320s can be wire ANDed and used as

an active-high ready signal, to disable PROMs with

active-low enable(s), or to reset to other parts of the system

(see Figure 27).

13

www.xilinx.com

1-800-255-7778

DS033 (v1.1) February 10, 2000

R

XCR3320: 320 Macrocell SRAM CPLD

Configuration Data Format

Overview

The XCR3320 functionality is determined by the state of

internal configuration RAM. This section discusses the con-

figuration data format, and the function of each field in con-

figuration data packets.

2

16

1

4

COMPRESSION

BITS

CRC

BITS

CRC

ENABLE

PREAMBLE/

POSTAMBLE

LEADING 1s

MSB

LSB

SP00594

Configuration Data Packets

Configuration of the XCR3320 is done using configuration

packets. The configuration packet is shown in Figure 11.

The data packet consists of a header and a data frame.

There are four types of data frames. The header is shifted

into the device first, followed by one data frame. Configura-

tion of a single XCR3320 requires 338 data packets, one for

each address. All preceding data must contain only 1’s.

Once a device is configured, it retransmits data of any

polarity. Before and during configuration, all data retrans-

mitted out the daisy-chain port (dout) are 1’s.

Figure 12: 27-bit Header

The header is fixed and consists of five fields:

•

Leading 1s,

Preamble,

CRC Enable,

CRC Bits,

Compression Bits.

The leading 1s enter the device first. The following is a

description of each field in the header.

27

Leading 1s:

DATA FRAME

HEADER

This is a four or greater bit field consisting of 1s.

MSB

LSB

SP00593

Preamble/Postamble:

This is a four bit field which indicates the start of a

frame or the end of configuration:

Preamble: -0010 - signals the beginning of a config-

uration data packet.

Postamble: 0100 -signals the end of configuration.

All other values of the preamble field force configu-

ration of the entire system to restart.

Figure 11: Data Packet

The ordering of the data packets may be random, but they

cannot be mixed with other devices’ data packets. Align-

ment bits are not required between data packets. If used,

alignment bits must be included in the length count, and

they must be at least 2-bits long.

The segments CRC Enable, CRC Bits, and Compression

Bits are valid only if the Preamble field is 0010.

Cyclic Redundancy Check (CRC) Enable:

Table 4: Configuration Frame Size

In this single bit field, a 0 disables CRC checking of

the data stream. If the CRC is disabled the 16 bit

CRC field must be the default described below. A1

enables CRC error checking of the data stream.

Device

Number of frames

XCR3320

338

Data bits/standard frame

Data bits/compressed frame

Data bits/user_code frame

Data bits/isc_code frame

560

14

CRC Error Checking:

560

The CRC field is a 16 bit field. The default value is

1010_1010_1010_1010. The calculated value is

from data, address, stop bit, and first alignment bit

(starting with crc_reg[15:0] = [0]). Using verilog

operators, the crc is calculated as:

560

Maximum configuration

data – # bits/frame x # frames

189280

crc_reg[14:2] <= cr_reg[14:2] << 1;

cr_reg[2] <= cr_reg[15]^din^cr_reg[1];

cr_reg[1] <= cr_reg[0];

cr_reg[0] < cr_reg[15]^din;

cr_reg[15] <= cr_reg[15]^din^cr_reg[14];

If a CRC error is detected, configuration is halted

and must be restarted.

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

14

R

XCR3320: 320 Macrocell SRAM CPLD

Compression Bits:

Compressed Frame

This 2-bit field defines the use of compression of the data

packets.

11

ADDRESS

MSB

1 (0)

2 (11)

00 - Standard mode:

The data packet contains both address and data

01 - Reset mode:

The data packet contains only the address field.

This pattern causes the configuration register to be

reset.

STOP BIT

ALIGN BITS

LSB

SP00597

igure 14: Compressed Frame

10 - Hold mode:

The data packet contains only the address field.

This pattern causes the configuration register to

hold its value.

The compressed frame contains no data.

11 - Set mode:

User Code Frame

The data packet contains only the address field.

This pattern causes the configuration register to be

set.

11

274

24

32

216

1 (0)

2 (11)

LENGTH

COUNT

DEVICE

ID

USER

CODE

STOP

BIT

ALIGN

BITS

Data Frames

ADDRESS UNUSED

MSB

The four types of data frames are standard, compressed,

user_code, and isc_code. All fields must be completely

filled, with 1s used to fill unused bits. The definition of each

frame is described below:

LSB

SP00598

Figure 15: User Code Frame

Standard Frame

The user code is located at address 336.

11

546

1 (0)

2 (11)

Length Count:

This is a 24 bit field containing the length of the

data stream transmitted to configure all of the

devices in the daisy chain. This field is only used by

a XCR3320 if it is in the master mode.

ADDRESS

DATA FRAME

STOP BIT

ALIGN BITS

MSB

LSB

SP00595

Device ID:

igure 13: Standard Frame

Address:

This is a 32-bit field containing XCR3320 device ID:

0000_001_001_010000_1_000_00000010101_1

User Code:

This is an 11 bit field for providing 338 (336 SRAM

plus 2user) addresses.

This is a 216 bit field reserved for user information.

ISC Code Frame

Data:

546 bit field.

The isc_code address is 337.

Stop bit:

This is a one bit field which must be 0.

11

2

272

1 (0)

2 (11)

ADDRESS

ISC CODE

UNUSED

STOP BIT

ALIGN BITS

Align bit:

This is a two bit field which must be 11.

MSB

LSB

UNUSED

SP00599

Figure 16: ISC Frame

The ISC frame allows the user to write an ISC code to the

device.

15

www.xilinx.com

1-800-255-7778

DS033 (v1.1) February 10, 2000

R

XCR3320: 320 Macrocell SRAM CPLD

command, whether a single serial EEPROM is used or mul-

tiple serial ROMs are cascaded, whether the serial

EEPROM contains a single or multiple configuration pro-

grams, etc.

Reconfiguration

To reconfigure the XCR3320 when the device is operating

in the system, a low pulse is input into prgmn. The I/Os not

used for configuration are 3-stated. The XCR3320 then

samples the mode select inputs and begins re-configura-

tion. The mode pins are continuously sampled, so the sig-

nals must be stable while prgmn is low. When configuration

is compete, done is released, allowing it to be pulled high.

Data is read into the XCR3320 sequentially from the serial

ROM. The DATA output from the serial EEPROM is con-

nected directly into the din input of the XCR3320. The cclk

output from the XCR3320 is connected to the CLOCK input

of the serial EEPROM. During the configuration process,

cclk clocks one data bit into the XCR3320 on each rising

edge.

CRC Error Checking

CRC checking is done on each frame if enabled by setting

the CRCen bit in the header. If there is an error, a CRC

error is flagged by pulling crcerrn low. The XCR3320 is

forced into the initialization state, and then moves into the

configuration state after prgmn and resetn go high. The

XCR3320 will also pull crcerrn low if an invalid preamble is

detected within a configuration data packet.

Since the data and clock are direct connects, the

XCR3320/serial EEPROM interface task is to use the sys-

tem or XCR3320 to enable the RESET/OE and CE of the

serial EEPROM(s). The serial EEPROM’s RESET/OE is

programmable to function with RESET active-low and OE

active-high, which allows hdc from the XCR3320 to control

this function.

XCR3320 Configuration Modes

Likewise, the serial EEPROM could be programmed to

function with RESET active high and OE active low, allow-

ing the ldcn pin from the XCR3320 to control this function.

The XCR3320 done pin is connected to the serial

EEPROM CE to enable the EEPROMs during configuration

and disable them when configuration is complete.

The method for configuring the XCR3320 is selected by the

m0, m1, and m2 inputs. The m3 input should be high for all

modes. In master modes, cclk is an output with a nominal

frequency of 1 MHz. In slave modes, cclk is an input with a

maximum frequency of 10 MHz if configuring only a single

device, and 1 MHz if devices are daisy chained.

In Figure 17, the serial EEPROMs RESET/OE pin has

been programmed to function with RESET active low and

OE active high, and it is controlled by the XCR3320’s hdc

pin. This resets the serial EEPROMs during the initializa-

tion state and enables their output during the configuration

state. If a bit error is found during configuration, hdc will go

low, signifying the XCR3320 is back in initialization state

and also resetting the EEPROMs. This restarts the config-

uration process.

Master Serial Mode

In the master serial mode, the XCR3320 loads the configu-

ration data from an external serial ROM. The configuration

data is either loaded automatically at start-up or on a com-

mand to reconfigure. Serial EEPROMs from Altera, Atmel,

Lucent, Microchip, and Xilinx can be used to configure the

XCR3320 in the master serial mode. This provides a simple

four-pin interface in an eight-pin package. Serial EEPROMs

are available in 32K, 64K, 128K, 256K, and 1M bit densi-

ties.

The XCR3320 done pin is routed to the CE pin of the

EEPROMs. The Low signal on done during configuration

enable the serial EEPROMs. At the completion of configu-

ration, the High on done disables the EEPROMs.

Configuration in the master serial mode can be done at

power-up and/or upon a configure command. The system

or the XCR3320 must activate the serial EEPROM’s

RESET/OE and CE inputs. At power-up, the XCR3320 and

serial EEPROM each contain internal power-on reset cir-

cuitry which allows the XCR3320 to be configured without

the system providing an external signal. The power-on

reset circuitry causes the serial EEPROMs’ internal

address pointer to be reset. After power-up, the XCR3320

automatically enters its initialization phase.

In Figure 17, a serial EEPROM is programmed to configure

a XCR3320. When configuration data requirements exceed

the capacity of a single serial EEPROM, multiple serial

EEPROMs can be cascaded to support the configuration of

a single (or multiple) XCR3320(s). After the last bit from the

first serial ROM is read, the serial ROM outputs CEO Low

and 3-states the DATA output. The next serial ROM recog-

nizes the Low on CE input and outputs configuration data

on the DATA output. After configuration is complete, the

XCR3320’s done output into CE disables the serial

EEPROMs.

The serial EEPROM/XCR3320 interface used depends on

such factors as the availability of a system reset pulse,

availability of an intelligent host to generate a configure

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

16

R

XCR3320: 320 Macrocell SRAM CPLD

TO DAISY–CHAINED

DEVICES

dout

din

DATA

CLK

cclk

done

hdc

CE

RESET/OE

V

CC

CEO

XCR3320

prgmn

resetn

V

EXTERNAL

CONTROLLER

IF DESIRED

CC

M3

M2

M1

M0

SP00666

Figure 17: Master Serial Configuration

t

CL

CCLK

t

CH

t

S

t

H

DIN

BIT N

t

D

DOUT

BIT N

SP00584

Figure 18: Master Serial Configuration Mode Timing Diagram

Table 5: Master Serial Configuration Mode Timing Characteristics

Symbol

t_S

Parameter

Min.

60

Nom.

Max.

Unit

ns

din setup time

-

t_H

din hold time

0

-

ns

t_D

cclk to dout delay

cclk low time (M3 = 1)

cclk high time (M3 = 1)

cclk frequency (M3 = 1)

-

300

833

1.4

ns

t_CL

t_CH

t_C

357

0.6

500

1.0

ns

MHz

17

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Master Parallel Mode

In applications in which a serial EEPROM stores multiple

configuration programs, the subsequent configuration pro-

gram(s) are stored in EEPROM locations that follow the last

address for the previous configuration program. The user

must ensure that the serial EEPROMs address pointer is

not reset, causing the first device configuration to be

reloaded.

The master parallel configuration mode is generally used to

interface to industry-standard byte-wide memory such as

256K and larger EEPROMs. Figure 19 provides the inter-

face for master parallel mode. The XCR3320 outputs a

20-bit address on A[19:0] to memory and reads one byte of

configuration data every eighth cclk. The parallel bytes are

internally serialized starting with the least significant bit,

D0. The starting memory address is 00000 Hex and the

XCR3320 increments the address for each byte loaded.

The starting address is output when the device enters the

configuration state. The XCR3320 latches the data byte on

the second rising edge of cclk. This next data byte is

latched in the XCR3320 seven cclk cycles later.

Contention on the XCR3320’s din pin must be avoided.

During configuration, din receives configuration data. After

configuration, it is a user I/O.

DESIGN COMPILATION AND FIT

jed

jed2mcs

download

PROM PROGRAMMER

SLAVE SERIAL CONFIGURATION

SP00676

Figure 19: Master

A[19:0]

t

S

t

H

D[7:0]

CCLK

DOUT

BYTE N

BYTE N + 1

t

CH

t

CL

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

t

D

BYTE N

BYTE N + 1

SP00585

Figure 20: Master Parallel Configuration Mode Timing Diagram

DS033 (v1.1) February 10, 2000

www.xilinx.com

18

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

.

Table 6: Master Parallel Configuration Mode Timing Characteristics

Symbol

t_AV

Parameter

Min.

0

Nom.

Max.

200

-

Unit

ns

cclk to address valid

-

t_S

D[7:0] setup time to cclk high

60

0

ns

t_H

D[7:0] hold time from cclk high

cclk low time

-

ns

t_CL

t_CH

t_D

M3 = 1

357

-

500

833

300

1.4

ns

cclk high time

ns

cclk to dout delay

cclk frequency

ns

f_C

M3 = 1

0.6

1.0

MHz

XCR3320 for daisy-chained devices. Note that the cclk fre-

quency for daisy-chained operation is limited to 1 MHz.

Synchronous Peripheral Mode

In the synchronous peripheral mode, byte-wide data is

input into D[7:0] on the rising edge of the cclk input. The

first data byte is clocked in on the second cclk after hdc

goes high. Subsequent data bytes are clocked in on every

eighth rising edge of cclk. The process repeats until all of

the data is loaded into the XCR3320. The serial data

begins shifting out on dout 0.5 cycles after the parallel data

was loaded. It requires additional cclks after the last byte is

loaded to complete the shifting. Figure 21 shows the inter-

face for synchronous peripheral mode. When configuring a

single device, the frequency of cclk can be up to 10 MHz.

As with master modes, this mode can be used for the lead

Also note that CS1 is a multi-function pin, which means that

it is available as a user I/O during normal device operation.

As with all user I/O on the XCR3320, CS1 has an internal

pull-down resistor that is automatically activated if the I/O

pin is not used (see “Terminations” on page 8 for more

information). If CS1 is left attached to V_CCafter configura-

tion, and it is not used as an I/O, the internal pull-down must

be disabled or a path from V_CCto ground is created. To dis-

able the pull-down, use the XPLA property statement

‘signal name:pin number tri-state’ to disable

the resistor.

TO DAISY-CHAINED

DEVICES

8

D[7:0]

dout

done

crcerrn

cclk

MICRO–

PROCESSOR

OR

V

prgmn

CC

V

SYSTEM

CC

XCR3320

cs1

EXTERNALLY CONTROLLED

IF DESIRED

resetn

cs0n

wrn

M3

M2

SPMI

SEE TABLE 9

M1

M0

SP00675

Figure 21: Synchronous Peripheral Configuration

19

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

t

CH

CCLK

CS0N

t

CL

CS1

hdc

t

H

t

S

D[7:0]

DOUT

BYTE 0

BYTE 1

D7

t

D

D0

D1

D2

D3

D4

D5

D6

D0

D1

SP00609

Figure 22: Synchronous Peripheral Configuration Mode Timing Diagram

Table 7: Synchronous Peripheral Configuration Mode Timing Characteristics

Symbol Parameter

t_S

Min.

20

0

Max.

Unit

ns

D[7:0] setup time

D[7:0] hold time

cclk high time

0

-

t_H

ns

t_CH

Single device

50

500

50

500

-

ns

Daisy-chain device

Single device

-

ns

t_CL

f_C

cclk low time

-

ns

Daisy-chain device

Single device

-

ns

cclk frequency

10

1

MHz

Daisy-chain device

-

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

20

R

XCR3320: 320 Macrocell SRAM CPLD

Slave Serial Mode

ation, cclk is routed into all slave serial mode devices in

parallel and the frequency is limited to 1 MHz. The dout pin

of the lead device is connected to the din pin of the next

device and so on. In daisy-chained operation, all down-

stream devices use slave serial mode regardless of the

configuration mode of the lead device.

Figure 23 shows the interface for the slave serial configura-

tion mode. The configuration data is provided into the

XCR3320’s din input synchronous with the cclk input. After

the XCR3320 has loaded its configuration data, it re-trans-

mits incoming configuration data on dout. When configur-

ing a single device, the frequency of cclk can be up to 10

MHz.

Multiple slave XCR3320s can be loaded with identical con-

figurations simultaneously. This is done by loading the con-

figuration data into the din inputs in parallel.

A device in slave serial mode can be used as the lead

device in a daisy-chain. When used in daisy-chained oper-

TO DAISY–CHAINED

DEVICES

dout

XCR3320

crcerrn

prgmn

done

cclk

MICRO–

PROCESSOR

OR

DOWNLOAD

CABLE

V

CC

din

EXTERNALLY CONTROLLED

IF DESIRED

V

CC

resetn

M3

M2

M1

M0

SP00668

Figure 23: Slave Serial Configuration Schematic

BIT N – 1

BIT N

BIT N + 1

DIN

t

S

t

H

CCLK

DOUT

t

D

t

CL

t

CH

BIT N

BIT N + 1

BIT N – 1

SP00610

Figure 24: Slave Serial Configuration Mode Timing Diagram

21

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Table 8: Slave Serial Configuration Mode Timing Characteristics

Symbol

t_S

Parameter

Min

20

0

Max.

Unit

ns

din setup time

din hold time

cclk high time

0

-

t_H

ns

t_CH

Single device

50

500

50

500

-

ns

Daisy-chain device

Single device

-

ns

t_CL

f_C

cclk low time

-

ns

Daisy-chain device

Single device

-

ns

cclk frequency

10

1

MHz

Daisy-chain device

-

cycles after the parallel data was loaded. It requires addi-

tional cclks after the last byte is loaded to complete the

shifting. Figure 25 shows the interface for slave parallel

mode. When configuring a single device, the frequency of

cclk can be up to 10 MHz.

Slave Parallel Mode

The slave parallel mode is essentially the same as the syn-

chronous peripheral mode, except that the chip select pins

(cs1 and cs0n) are not used. As in the synchronous periph-

eral mode, byte-wide data is input into D[7:0] on the rising

edge of the cclk input. The first data byte is clocked in on

the second cclk after hdc goes High. Subsequent data

bytes are clocked in on every eighth rising edge of cclk. The

process repeats until all of the data is loaded into the

XCR3320. The serial data begins shifting out on dout 0.5

As with synchronous peripheral mode, the slave parallel

mode can be used as the lead XCR3320 for daisy-chained

devices. Note that the cclk frequency for daisy-chain oper-

ation is limited to 1 MHz.

TO DAISY–CHAINED

DEVICES

dout

XCR3320

crcerrn

prgmn

MICRO–

PROCESSOR

done

V

cclk

CC

8

D[7:0]

EXTERNALLY CONTROLLED

IF DESIRED

V

CC

resetn

M3

CS1

M2

M1

M0

WRN

CS0N

SP00669

Figure 25: Slave Parallel Configuration Schematic

DS033 (v1.1) February 10, 2000

www.xilinx.com

22

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

t

CH

CCLK

t

CL

hdc

t

H

t

S

D[7:0]

DOUT

BYTE 1

D7

BYTE 0

t

D

D0

D1

D2

D3

D4

D5

D6

D0

D1

SP00654

Figure 26: Slave Parallel Configuration Mode Timing Diagram

Table 9: Slave Parallel Configuration Mode Timing Characteristics

Symbol

t_S

Parameter

Min.

20

0

Max.

Unit

ns

D[7:0] setup time

D[7:0] hold time

cclk high time

0

-

t_H

ns

t_CH

Single device

50

500

50

500

-

ns

Daisy-chain device

Single device

-

ns

t_CL

f_C

cclk low time

-

ns

Daisy-chain device

Single device

-

ns

cclk frequency

10

1

MHz

Daisy-chain device

-

23

www.xilinx.com

1-800-255-7778

DS033 (v1.1) February 10, 2000

R

XCR3320: 320 Macrocell SRAM CPLD

high when all devices in the daisy-chain have completed

configuration. All devices now move to the start-up state

simultaneously.

Daisy Chain Operation

Multiple XCR3320s can be configured by using a

daisy-chain of XCR3320s. Daisy-chaining uses a lead

XCR3320 and one or more XCR3320s configured in slave

serial mode. The lead XCR3320 can be configured in any

mode. Figure 27 shows the connections for loading multiple

XCR3320s in a daisy-chain configuration with the lead

devices configured in master parallel mode. Figure 28

shows the connections for loading multiple XCR3320’s with

the lead device configured in master serial mode.

The generation of cclk for the daisy-chained devices which

are in slave serial mode differs depending on the configura-

tion mode of the lead device. A master parallel mode device

uses its internal timing generator to produce an internal

cclk. If the lead device is configured in either synchronous

peripheral, slave serial mode, or slave parallel mode, cclk is

an input and is mated to the lead device and to all of the

daisy-chained devices in parallel. The configuration data is

read into din of slave devices on the positive edge of cclk,

and shifted out dout on the negative edge of cclk. Note that

daisy-chain operation is limited to a cclk frequency of

1 MHz. If a CRC error or an invalid preamble is detected by

a slave device, crcerrn will be pulled low and in turn pull

prgmn low, halting configuration for all devices. If a CRC

error is detected by the master device, hdc will be pulled

low, resetting the EEPROM to the first address and restart-

ing configuration.

Daisy-chained XCR3320s are connected in series. An

upstream XCR3320 which has received the preamble out-

puts a high on dout, ensuring that downstream XCR3320s

do not receive frame start bits. When the lead device

receives the postamble, its configuration is complete. At

this point, the configuration RAM of the lead device is full

and its done pin is released. The lead device continues to

load configuration data until the internal frame bit counter

reaches the length count or all the done pins of the chain

have gone high. Since the configuration RAM of the lead

device is full, this data is shifted out serially to the down-

stream devices on the dout pin. As the configuration is

completed for the downstream devices, each will release its

done pin. Because the done pins of each device in the

chain are wire-anded together, the done pin will be pulled

The development software can create a composite configu-

ration file for configuring daisy-chained XCR3320s. The

configuration data consists of multiple concatenated data

packets.

cclk

din

cclk

dout

din

A[19:0]

MASTER

A[19:0]

EEPROM

SLA

SLAVE #2

VE #1

PARALLEL/LEAD

D[7:0]

V

CC

done

OE

CE

prgmn

V

CC

V

CC

crcerrn

M3

M2

M1

M0

M3

M2

M1

M0

M3

M2

M1

M0

PROGRAM

V

CC

hdc

ldcn

hdc

ldcn

hdc

ldcn

SP00670

Figure 27: Daisy-Chain Schematic with Lead Device in Master Parallel

DS033 (v1.1) February 10, 2000

www.xilinx.com

24

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

V

CC

cclk

din

cclk

din

cclk

din

cclk

dout

V

CC

V

CC

MASTER SERIAL

LEAD

SLAVE #1

SLAVE #2

EEPROM

pgrmn

resetn

pgrmn

resetn

pgrmn

resetn

done

reset/OE

CE

V

CC

crcerrn

hdc

crcerrn

hdc

crcerrn

hdc

M3

M2

M1

M0

M3

M2

M1

M0

M3

M2

M1

M0

SP00665

Figure 28: Daisy Chain Schematic with Master Serial Lead Device

25

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

-

Reduces/eliminates the need for expensive test

equipment

JTAG Testing Capability

JTAG is the commonly-used acronym for the Boundary

Scan Test (BST) feature defined for integrated circuits by

IEEE Standard 1149.1. This standard defines input/output

pins, logic control functions, and commands which facilitate

both board and device level testing without the use of spe-

cialized test equipment. BST provides the ability to test the

external connections of a device, test the internal logic of

the device, and capture data from the device during normal

operation. BST provides a number of benefits in each of the

following areas:

-

Reduces test preparation time

Reduces spare board inventories

The Xilinx XCR3320's JTAG interface includes a TAP Port

and a TAP Controller, both of which are defined by the IEEE

1149.1 JTAG Specification. As implemented in the Xilinx

XCR3320, the TAP Port includes five pins (refer to

Table 10) described in the JTAG specification: t_CK, t_MS, t_DI,

_DO, and t_RSTN. These pins should be connected to an

external pull-up resistor to keep the JTAG signals from

floating when they are not being used.

t

•

Testability

Table 11 defines the dedicated pins used by the mandatory

JTAG signals for the XCR3320.

-

Allows testing of an unlimited number of

interconnects on the printed circuit board

Testability is designed in at the component level

Enables desired signal levels to be set at specific

pins (Preload)

Data from pin or core logic signals can be examined

during normal operation

-

The JTAG specifications define two sets of commands to

support boundary-scan testing: high-level commands and

low-level commands. High-level commands are executed

via board test software on an a user test station such as

automated test equipment, a PC, or an engineering work-

station (EWS). Each high-level command comprises a

sequence of low level commands. These low-level com-

mands are executed within the component under test, and

therefore must be implemented as part of the TAP Control-

ler design. The set of low-level boundary-scan commands

implemented in the XCR3320 is defined in Table 11. By

supporting this set of low-level commands, the XCR3320

allows execution of all high-level boundary-scan com-

mands.

-

•

Reliability

-

Eliminates physical contacts common to existing test

fixtures (e.g., “bed-of-nails”)

Degradation of test equipment is no longer a

concern

Facilitates the handling of smaller, surface-mount

components

Allows for testing when components exist on both

sides of the printed circuit board

•

Cost

Table 10: JTAG Pin Description

Name

Description

tck

Test Clock Output

Clock pin to shift the serial data and instructions in and out of the tdi and tdo pins,

respectively. tck is also used to clock the TAP Controller state machine.

tms

Test Mode Select

Serial input pin selects the JTAG instruction mode. tms should be driven high during

user mode operation.

tdi

Test Data Input

Serial input pin for instructions and test data. Data is shifted in on the rising edge of tck.

tdo

Test Data Output

Serial output pin for instructions and test data. Data is shifted out on the falling edge of

tck. The signal is tri-stated if data is not being shifted out of the device.

trstn

Test Reset

Forces TAP controller to test logic reset state. This signal is active low.

Table 11: XCR3320 JTAG Pinout by Package Type

Device: XCR3320

(Pin Number / Macrocell #)

t_CK

V4

41

t_MS

W4

43

t_DL

U5

42

t_DO

Y4

44

t_RSTN

L18

97

256-pin PBGA

160-pin LQFP

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

26

R

XCR3320: 320 Macrocell SRAM CPLD

Table 12: XCR3320 Low-Level JTAG Boundary-Scan Commands

Instruction

(Instruction Code)

Register Used

Description

The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal

operation of the component to be taken and examined. It also allows data values to be

loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to

selection of the other boundary-scan test instructions.

SAMPLE/PRELOAD

(00010)

Boundary-Scan Register

EXTEST

(00000)

Boundary-Scan Register

The mandatory EXTEST instruction allows testing of off-chip circuitry and board level

interconnections. Data would typically be loaded onto the latched parallel outputs of

Boundary-Scan Shift-Register using the SAMPLE/PRELOAD instruction prior to

selection of the EXTEST instruction.

BYPASS

(11111)

Bypass Register

Places the 1-bit bypass register between the tdi and tdo pins, which allows the BST

data to pass synchronously through the selected device to adjacent devices during

normal device operation. The BYPASS instruction can be entered by holding tdi at a

constant high value and completing an Instruction-Scan cycle.

IDCODE

(00001)

Boundary-Scan Register

Selects the IDCODE register and places it between tdi and tdo, allowing the IDCODE

to be serially shifted out of tdo. The IDCODE instruction permits blind interrogation of

the components assembled onto a printed circuit board. Thus, in circumstances where

the component population may vary, it is possible to determine what components exist

in a product.

HIGHZ

(00101)

Bypass Register

The HIGHZ instruction places the component in a state in which all of its system logic

outputs are placed in an inactive drive state (e.g., high impedance). In this state, an

in-circuit test system may drive signals onto the connections normally driven by a

component output without incurring the risk of damage to the component. The HIGHZ

instruction also forces the Bypass Register between tDI and tDO.

INTEST

(00011)

Boundary-Scan Register

The INTEST instruction allows testing of the on-chip system logic while the component

is assembled on the board. The boundary-scan register is connected between TDI and

TDO. Using the INTEST instruction, test stimuli are shifted in one at a time and applied

to the on-chip system logic. The test results are captured into the boundary-scan

register and are examined by subsequent shifting, Data would typically be loaded onto

the latched parallel outputs of boundary-scan shift-register stages using the

SAMPLE/PRELOAD instruction prior to selection of the INTEST instruction.

NOTE: Following use of the INTEST instruction, the on-chip system logic may be in an

indeterminate state that will persist until a system reset is applied. Therefore, the

on-chip system logic may need to be reset on return or normal (i.e., non-test)

operation.

27

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

TCK

TMS

t

S

t

H

t

CL

CH

TDI

t

D

TDO

SP00613

Figure 29: Boundary Scan Timing Diagram

Table 13: Boundary Scan Timing Characteristics

Symbol

t_S

Parameter

Min

20

0

Max.

-

Unit

ns

tdi/tms to tck setup time

tdi/tms from tck hold time

tck high time

t_H

ns

t_CH

t_CL

f_TCK

t_D

50

-

ns

tck low time

-

ns

tck frequency

10

35

MHz

ns

tck to tdo delay

-

DS033 (v1.1) February 10, 2000

www.xilinx.com

28

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

PC-ISP software. Table 14 shows the ISC commands sup-

ported by the XCR3320

Device Configuration Through JTAG

In addition to the normal configuration modes, the

XCR3320 can also be configured through the JTAG port.

This feature is very useful for design prototyping and debug

before the device is put into the final product. In System

Configuration of the XCR3320 is supported by Xilinx

To configure the device through the JTAG port, mode pins

M0, M1, and M2 should all be held low. M3, as always,

should be high and the JTAG pins should be terminated as

described in “Terminations” on page 8 of this data sheet.

Table 14: Low Level ISP Commands

Instruction

(Register Used)

Instruction

Code

Description

Enable

(ISP Shift Register)

1001

Enables the Erase, Program, and Verify commands. Using the ENABLE

instruction before the Erase, Program, and Verify instructions allows the user

to specify the outputs the device using the JTAG Boundary-Scan

SAMPLE/PRELOAD command.

Erase

(ISP Shift Register)

1010

1011

Erases the entire EEPROM array. The outputs during this operation can be

defined by user by using the JTAG SAMPLE/PRELOAD command.

Program

(ISP Shift Register)

Programs the data in the ISP Shift Register into the addressed EEPROM row.

The outputs during this operation can be defined by user by using the JTAG

SAMPLE/PRELOAD command.

Verify

(ISP Shift Register)

1100

Transfers the data from the addressed row to the ISP Shift Register. The data

can then be shifted out and compared with the JEDEC file. The outputs during

this operation can be defined by the user.

29

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Absolute Maximum Ratings¹

Symbol

Parameter

Min

-0.5

-1.2

-0.5

-30

Max.

4.6

Unit

V

V_CC

V_IN

Supply voltage

Input voltage

Output voltage

Input current

5.75

V_CC+0.5

30

V

V_OUT

I_IN

V

mA

°C

T_J

Junction temperature range

Storage temperature range

-40

150

T_STG

Note:

-65

150

1. Stresses above these listed may cause malfunction or permanent damage to the device. This is a stress rating only.

Functional operation at these or any other condition above those indicated in the operational and programming specification

is not implied.

Operating Range

Product Grade

Commercial

Industrial

Temperature

Voltage

0 to 70°C

-40 to 85°C

3.3V ±10%

DC Electrical Characteristics For Commercial Grade Devices

Commercial temperature range: V_CC= 3.0V to 3.6V; 0°C < T_AMB< 70°C

Symbol

V_IH

Parameter

Test Conditions

Min.

Max.

Unit

Input high voltage

2.0

-0.3

5.5

0.8

-

V

V_IL

Input low voltage

Output high voltage

Output low voltage

V_OH

V_OL

I_I

I_OH= -8 mA

I_OL= 8 mA

2.4

V

-

0.4

10

V

Input leakage current V_I= 0 or 5.5V

-10

µA

pF

kΩ

I_CCSB

C_IN

Standby current

Input capacitance

I/O capacitance

T_AMB= 25°C; no output loads, inputsatV_CCor V_SS

T_AMB= 25°C; V_CC= 3.3V; f = 1 MHz

.

-

100

10

-

C_IO

-

10

C_CLK

R_DONE

R_PD

Clock pin capacitance T_AMB= 25°C; V_CC= 3.3V; f = 1 MHz

done pull-up resistor V_CC= 3.0V; V_IN= 0V

12

5

20

Unused I/O pull-down V_CC= 3.6V; V_IN= V_CC

resistor

100

400

I_OZH

I_OZL

Input leakage

V_IN= 5.5V or 3.6V

V_IN= 0V

-10

10

mA

DS033 (v1.1) February 10, 2000

www.xilinx.com

30

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

AC Electrical Characteristics For Commercial Grade Devices

Commercial temperature range: V_CC= 3.0V to 3.6V; 0°C < T_AMB< 70°C

Symbol

Parameter

C7

C10

Unit

Min. Max. Min. Max.

Timing Requirements

t_CL

Clock LOW time

2.5

3.0

4.5

5.5

3.0

4.0

5.5

6.5

ns

t_CH

Clock HIGH time

t_{SU_PAL}

t_{SU_PLA}

t_{SU_XOR}

t_H

PAL setup time (Global clock)

PLA setup time (Global clock)

XOR setup time (Global clock)

Hold time (Global clock)

0

Output Characteristics

t_{PD_PAL}

t_{PD_PLA}

t_{PD_XOR}

Input to output delay through PAL

Input to output delay through PLA

Input to output delay through XOR

7.5

9.0

10.0

11.5

12.5

6.0

ns

10.0

4.5

t_{PDF_PAL}Input (or feedback node) to internal feedback node delay time through

PAL

t_{PDF_PLA}Input (or feedback node) to internal feedback node delay time through

PLA

6.0

7.0

7.5

8.5

ns

t_{PDF_XOR}Input (or feedback node) to internal feedback node delay time through

XOR

t_CF

Global clock to feedback delay

3.0

6.0

1.0

3.5

7.5

1.5

ns

t_CO

Global clock to out delay

t_CS

Clock skew (variance for switching outputs with common global clock)

Maximum flip-flop toggle rate:

ns

f_MAX1

200

166

MHz

1







-------------------

_CH

t

CL + t

f_MAX2

Maximum internal frequency:

166

111

133

87

MHz

1





-----------------------------



_CF

t

SU – PAL + t

f_MAX3

Maximum external frequency:

1





-----------------------------



_CO

t

SU – PAL + t

t_BUFF

t_SSR

t_EA

Output buffer delay (fast)

3.0

5.0

4.0

6.0

ns

Slow slew rate incremental delay

Output enable delay

10.0

10.5

9.5

12.0

11.0

12.0

2.5

ns

t_ER

Output disable delay¹

Global 3-state enable

Global 3-state disable

Input to register reset

Input to register preset

Global reset to register reset

Global ZIA delay

t_GTSA

t_GTSR

t_RR

t_RP

t_GRR

t_GZIA

Note:

10

2.0

1. Output C_L= 5.0 pF.

31

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

DC Electrical Characteristics For Industrial Grade Devices

Industrial temperature range: V_CC= 3.0V to 3.6V; -40°C < T_AMB< 85°C

Symbol

V_IH

Parameter

Input high voltage

Input low voltage

Output high voltage

Output low voltage

Test Conditions

Min.

2.0

-0.3

2.4

-

Max.

5.5

0.8

-

Unit

V

V_IL

V

V_OH

V_OL

I_I

I_OH= -8 mA

I_OL= 8 mA

V

0.4

10

V

Input leakage current V_I= 0 or 5.5V

-10

-

µA

pF

kΩ

I_CCSB

C_IN

Standby current

Input capacitance

I/O capacitance

T_amb= 25°C; no output loads, inputs at V_CCor V_SS

T_AMB= 25°C; V_CC= 3.3V; f = 1 MHz

.

100

10

-

C_IO

-

10

C_CLK

R_DONE

R_PD

Clock pin capacitance T_AMB= 25°C; V_CC= 3.3V; f = 1 MHz

done pull-up resistor V_CC= 3.0V; V_IN= 0V

-

12

5

20

Unused I/O pull-down V_CC= 3.6V; V_IN= V_CC

resistor

100

400

I_OZH

I_OZL

Input leakage

V_IN= 5.5V or 3.6V

V_IN= 0.0 V

-10

10

mA

DS033 (v1.1) February 10, 2000

www.xilinx.com

32

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

AC Electrical Characteristics For Industrial Grade Devices

Industrial temperature range: V_CC= 3.0V to 3.6V; -40°C < T_AMB< 85°C

N8

Symbol

Parameter

Unit

Min.

Max.

Timing Requirements

t_CL

Clock LOW time

Clock HIGH time

2.5

3.5

5.0

6.0

ns

t_CH

t_{SU_PAL}

t_{SU_PLA}

t_{SU_XOR}

t_H

PAL setup time (Global clock)

PLA setup time (Global clock)

XOR setup time (Global clock)

Hold time (Global clock)

0

Output Characteristics

t_{PD_PAL}

t_{PD_PLA}

t_{PD_XOR}

t_{PDF_PAL}

Input to output delay through PAL

8.5

10

ns

Input to output delay through PLA

Input to output delay through XOR

11

Input (or feedback node) to internal feedback node

delay time through PAL

5.0

t_{PDF_PLA}

t_{PDF_XOR}

Input (or feedback node) to internal feedback node

delay time through PLA

6.5

7.5

ns

Input (or feedback node) to internal feedback node

delay time through XOR

t_CF

t_CO

t_CS

Global clock to feedback delay

Global clock to out delay

3.5

7.0

1.0

ns

Clock skew (variance for switching outputs with

common global clock)

f_MAX1

Maximum flip-flop toggle rate:

200

MHz

1







-------------------

_CH

t

CL + t

f_MAX2

Maximum internal frequency:

143

95

MHz

1







-----------------------------

_CF

t

SU – PAL + t

f_MAX3

Maximum external frequency:

1







-----------------------------

_CO

t

SU – PAL + t

t_BUFF

t_SSR

t_EA

Output buffer delay (fast)

3.5

5.5

ns

Slow slew rate incremental delay

Output enable delay

11.0

11.5

10.0

11

t_ER

Output disable delay¹

Global 3-state enable

Global 3-state disable

Input to register reset

Input to register preset

Global reset to register reset

Global ZIA delay

t_GTSA

t_GTSR

t_RR

t_RP

t_GRR

t_GZIA

Note:

2.5

1. Output C_L= 5.0 pF.

33

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Thevenin Equivalent

V

L

= 0.5 V

DD

200Ω

DUT OUTPUT

25 pF

SP00629

Voltage Waveform

+3.0V

90%

10%

0V

t

R

t

F

2.0 ns

SP00630

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of

inputs and outputs, unless otherwise specified.

Input Pulses

DS033 (v1.1) February 10, 2000

www.xilinx.com

34

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Device Pin Diagrams

XCR3320 256-pin Plastic BGA

A1 BALL PAD CORNER

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

OM VIEW

BOTT

M

N

P

R

T

U

V

W

Y

SP00671

35

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Table 15: 230-pin Function Table

Function is Fast Module_Logic Block_Macrocell. For example, F1_0_56 means Fast Module 1, Logic Block 0, Macrocell 5.

Function Pkg Ball Function Pkg Ball Function Pkg Ball Function Pkg Ball Function Pkg Ball Function Pkg Ball

GND

A1

A2

F0_0_9

F0_0_10

F0_0_9

pgrm

C1

C2

F0_0_2*

F0_0_3

F0_0_4*

F0_0_5

F1_2_5

F1_2_4

F1_2_3

F1_2_2

E1

E2

clk_3

gts

L1

L2

F3_2_6*

F3_2_7

F3_2_8

GND

U1

U2

F3_2_11

GND

W1

W2

F0_2_11

F0_2_9

cclk

A3

C3

E3

GND

V_CC

L3

U3

F3_0_9

tms

W3

A4

C4

E4

L4

U4

W4

F0_2_5*

F0_2_2*

F0_3_0

F0_3_3

F0_3_6

F0_3_9

F0_3_10

F1_1_10

F1_1_7

F1_1_4

F1_1_1

F1_0_1

F1_0_4

F1_0_8

F1_0_10

F1_0_11

A5

F0_2_7

F0_2_4

F0_2_1

F0_3_1

FO_3_4

F0_3_7

F1_1_11

F1_1_8

F1_1_5*

F1_1_2

F1_0_0

F1_0_3

F1_0_7

GND

C5

E17

E18

E19

E20

V_CC

L17

L18

L19

L20

tdi

U5

F3_0_6

F3_0_3

F3_0_0*

F3_1_2

F3_1_5

F3_1_8

F3_1_11

F2_3_9

F2_3_6*

F2_3_3*

F2_3_0

F2_2_2*

F2_2_5*

F2_2_10

GND

W5

A6

C6

trstn

V_CC

U6

W6

A7

C7

GND

CLK_7

V_CC

U7

W7

A8

C8

V_CC

U8

W8

A9

C9

GND

U9

W9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

F0_1_1

F0_1_0*

F0_0_0*

F0_0_1

F1_2_1

F1_2_0

F1_3_0

F1_3_1

F1

F2

F3_3_11

F3_3_10

F3_3_9

GND

M1

M2

V_CC

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

V_CC

F3

M3

GND

F4

M4

V_CC

F17

F18

F19

F20

GND

M17

M18

M19

V_CC

F2_1_9

F2_1_10

F2_1_11

F2_2_6

F2_2_8

GND

F2_0_8

F2_0_7

F2_0_6*

F1_2_10

F1_2_9

F0_1_4*

F0_1_3*

F0_1_2*

V_CC

G1

G2

F3_3_8

F3_3_7

F3_3_6

F3_3_5

F2_1_5*

F2_1_6

F2_1_7

F2_1_8

N1

N2

F2_0_11

G3

N3

F0_0_11

GND

B1

B2

F0_0_6*

F0_0_7

F0_0_8

GND

D1

D2

G4

N4

F3_2_9

F3_2_10

GND

V1

V2

F3_0_11

F3_0_10

F3_0_8

tdo

Y1

Y2

V_CC

G17

G18

G19

G20

N17

N18

N19

N20

F0_2_10

resetn

B3

D3

F1_3_2*

F1_3_3

F1_3_4*

V3

Y3

B4

D4

tck

V4

Y4

F0_2_6

F0_2_3

F0_2_0*

F0_3_2

F0_3_5

F0_3_8

F0_3_11

F1_1_9

F1_1_6*

F1_1_3

F1_1_0

F1_0_2

F1_0_5*

F1_0_9

GND

B5

F0_2_8

done

D5

F3_0_7

F3_0_4*

F3_0_1

F3_1_1

F3_1_4*

F3_1_7

F2_3_11

F2_3_8

F2_3_5*

F2_3_2

F2_2_0*

F2_2_3

F2_2_7

GND

V5

F3_0_5*

F3_0_2*

F3_1_0*

F3_1_3

F3_1_6

F3_1_9

F3_1_10

F2_3_10

F2_3_7

F2_3_4

F2_3_1*

F2_2_1

F2_2_4

F2_2_9

F2_2_11

GND

Y5

B6

D6

V6

Y6

B7

V_CC

D7

F0_1_8

F0_1_7

F0_1_6

F0_1_5

F1_3_6

F1_3_7

F1_3_8

H1

H2

F3_3_4

F3_3_3*

F3_3_2

V_CC

P1

P2

V7

Y7

B8

V_CC

D8

V8

Y8

B9

GND

D9

H3

P3

V9

Y9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

V_CC

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H4

P4

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

V_CC

H17

H18

H19

H20

V_CC

P17

P18

P19

P20

GND

F2_1_2

F2_1_3

F2_1_4

V_CC

F1_0_6

GND

F0_1_11

F0_1_10

F0_1_9

GND

J1

J2

F3_3_1*

F3_3_0

F3_2_0

F3_2_1*

F2_0_1*

F2_0_0

F2_1_0

F2_1_1*

F3_2_2

F3_2_3*

F3_2_4

F3_2_5

F2_0_5

F2_0_4

F2_0_3*

F2_0_2

R1

R2

F1_2_8

F1_2_7

F1_2_6*

J3

R3

J4

R4

F2_0_10

F2_0_9

F1_2_11

GND

J17

J18

J19

J20

K1

R17

R18

R19

R20

T1

F1_3_9

F1_3_10

clk_2

clk_1

K2

T2

clk_0

K3

T3

V_CC

K4

T4

V_CC

K17

K18

K19

K20

T17

T18

T19

T20

clk_4

clk_5

clk_6

*Represents multi-function pin

DS033 (v1.1) February 10, 2000

www.xilinx.com

36

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

260-pin Description Table

Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.

Table 16: Pin Description

Symbol

Pin Numbers Type

Description

V_CC

D7, D8, D10,

D11, D13,

-

I

Positive power supply.

D14, D15, G4,

G17, K4, K17,

L4, L17, P4,

P17, U6, U7,

U8, U10, U11,

U13, U14

GND

A1, B2, B19,

C3, C18, D4,

D9, D12, D17,

J4, J17, L3,

L19, M4, M17,

U4, U9, U12,

U17, V3, V18,

W2, W19, Y20

Ground supply.

resetn

B4

During configuration, resetn forces the start of initialization. After configuration,

resetn is a direct input which can be used to asynchronously reset all the flip-flops. If

the global reset is not being used, this pin should be pulled high. If the rise time of the

prgmn signal is greater than 1 microsecond, this signal must be held low until prgmn

is high.

cclk

A4

D6

I/O In the master modes, cclk is an output which strobes configuration data in. In the

slave or synchronous peripheral mode, cclk is an input synchronous with the data on

din or D[7:0]. After configuration, this pin should be pulled low.

done

I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output,

done pulling high indicates configuration is complete. As an input, a low level on done

will delay the enabling of user I/O. If only one device is used, this pin can be left

floating. If multiple devices are daisy chained, an external pull-up should be used.

prgmn

C4

I

prgmn is an active-low input that forces the restart of configuration and initialization

and resets the boundary-scan circuitry. After configuration, the pin should be pulled

high. This signal must have a rise time less than 1 microsecond. If the rise time of this

signal is greater than 1 microsecond, resetn must be held low until prgmn is high.

spmi

mpmi

din

Y5

O

I

Special purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no

external termination is required. See “Terminations” on page 8 for more information.

W13

E1

Special purpose configuration pin that must be left floating during configuration for all

configuration modes. After configuration the pin is a user-programmable I/O, and no

external termination is required. See “Terminations” on page 8 for more information.

During slave serial or master serial configuration modes, din accepts serial

configuration data synchronous with cclk. During parallel configuration modes, din is

the D[0] input. After configuration, the pin is a user-programmable I/O, and no

external termination is required. See “Terminations” on page 8 for more information.

M2

M0

M1

M3

N17

G18

G20

A6

I

M2/M1/M0 are used to select the configuration mode. After configuration, the pins are

user-programmable I/O, and no external termination is required. See “Terminations”

on page 8 for more information.

M3 should be pulled high during configuration for all configuration modes. After

configuration, the pin is a user-programmable I/O, and no external termination is

required. See “Terminations” on page 8 for more information.

37

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Table 16: Pin Description (Continued)

Symbol

Pin Numbers Type

Description

tdi

tdo

tck

tms

trstn

U5

Y4

V4

W4

L18

I

O

I

Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are

dedicated pins for boundary-scan through the JTAG port. If JTAG is not being used,

tdi, tck, tms, and trstn should be terminated with a weak pull-up resistor. tdo can be

left unterminated. See “Terminations” on page 8 for more information.

hdc

B7

O

High During Configuration (hdc) is output high when the XCR3320 is in the

configuration state. hdc is used as a control output indicating that configuration is in

progress. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See “Terminations” on page 8 for more information.

ldcn

V9

O

Low During Configuration (ldcn) is output low when the XCR3320 is in the

configuration state. ldcnis used as a control output indicating that configuration is in

progress. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See “Terminations” on page 8 for more information.

crcerrn

C13

I/O crcerrn goes Low when the XCR3320 detects a CRC error or an invalid peramble

during configuration. The XCR3320 that detected the error will go into the initialization

state and will not resume configuration until prgmn and resetn are both high. Once

configuration has resumed crcerrn will go high. During configuration, an internal

pull-up is enabled. If only one device is used, this pin can be left floating. If multiple

devices are daisy chained, an external pull-up should be used. After configuration,

the pin is a user-programmable I/O, and no external termination is required. See

“Terminations” on page 8 for more information.

gts

L2

I

Global 3-state is an active-High dedicated input used to 3-state the I/Os and activate

the internal pull-down resistors. If this feature is not used, the pin should be pulled

Low.

cs0n

cs1

wrn

B17

W17

B13

I

cs0n/cs1/wrn are used in the peripheral configuration mode. The XCR3320 is

selected when cs0n and wrn are Low and cs1 is High. After configuration, these pins

are user-programmable I/O. cs0N and wrn require no external termination. See

“Terminations” on page 8 for more information. If cs1 is not used as an I/O after

configuration in synchronous peripheral mode, the 3-state property should be used

to disable the internal pull-down resistor. See the section on “Synchronous Peripheral

Mode” on page 19 for more information.

A[19:0]

N4, P2, R1,

R4, T2, P19,

U1, V6, Y6,

W7, Y7, V13,

W14, Y15,

V15, W16,

U20, T19,

O

In the master parallel configuration mode, A[19:0] address the configuration

EEPROM. After configuration, the pin is a user-programmable I/O, and no external

termination is required. See “Terminations” on page 8 for more information.

R17, R20

D[7:0]

dout

G1, A5, G3,

D1, F2, F3, E3,

E1

I

During master parallel, peripheral, and slave parallel configuration modes, D[7:0]

receive configuration data. After configuration, the pin is a user-programmable I/O,

and no external termination is required. See “Terminations” on page 8 for more

information.

D20

O

During configuration, dout is the serial data out that is used to drive the din of

daisy-chained slave devices. Data on dout changes on the falling edge of cclk. After

configuration, the pin is a user-programmable I/O, and no external termination is

required. See “Terminations” on page 8 for more information.

DS033 (v1.1) February 10, 2000

www.xilinx.com

38

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

XCR3320 - 160-Pin Plastic TQFP

160

121

120

1

TQFP

40

81

41

80

SP00672

39

www.xilinx.com

DS033 (v1.1) February 10, 2000

1-800-255-7778

R

XCR3320: 320 Macrocell SRAM CPLD

Table 17: 160-pin Function Table

Function is Fast Module_Logic Block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic Block 0, Macrocell 5.

Number

1

Function

F0_0_6*

F0_0_5

F0_0_4*

F0_0_3

F0_0_2*

F0_0_1

F0_0_0

GND

Number

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

Function

TCK

Number

Function

V_CC

Number

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

Function

V_CC

2

TDI

82

83

F2_0_6*

F2_0_5

F2_0_4

F2_0_3*

F2_0_2

F2_0_1*

F2_0_0

GND

F1_0_6

F1_0_5*

GND

3

TMS

4

TDO

84

5

F3_0_6

F3_0_5*

GND

85

F1_0_4

F1_0_3

F1_0_2

F1_0_1

F1_0_0

V_CC

6

86

7

87

8

F3_0_4*

F3_0_3

F3_0_2*

F3_0_1

F3_0_0*

V_CC

88

9

F0_1_0

F0_1_1

F0_1_2 *

F0_1_3

F0_1_4*

F0_1_5

V_CC

89

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

90

F2_1_0

F2_1_1*

F2_1_2

F2_1_3*

F2_1_4

F2_1_5*

F2_1_6

TRSTN

GND

91

F1_1_0

F1_1_1

F1_1_2

F1_1_3

F1_1_4

F1_1_5*

GND

92

93

F3_1_0*

F3_1_1

F3_1_2

F3_1_3

F3_1_4*

F3_1_5

GND

94

95

F0_1_6

GND

96

97

clk_0

98

F1_1_6*

V_CC

clk_1

99

V_CC

clk_2

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CLK_7

CLK_6

CLK_5

CLK_4

GND

F0_3_6

GND

clk_3

F3_1_6

V_CC

gts

F0_3_5

F0_3_4

F0_3_3

F0_3_2

F0_3_1

F0_3_0

V_CC

F2_3_6*

GND

F3_3_6

F3_3_5*

F3_3_4

F3_3_3*

F3_3_2

F3_3_1*

F3_3_0

GND

F2_3_5*

F2_3_4

F2_3_4*

F2_3_2

F2_3_1*

F2_3_0

V_CC

F1_3_6

V_CC

F1_3_5

F1_3_4*

F1_3_3

F1_3_2*

F1_3_1

F1_3_0

GND

F0_2_0*

F0_2_1

F0_2_2*

F0_2_3

F0_2_4

GND

F2_2_0*

F2_2_1

F2_2_2*

F2_2_3

F2_2_4

GND

F3_2_0

F3_2_1*

F3_2_2

F3_2_3*

F3_2_4

F3_2_5

F3_2_6*

V_CC

F1_2_0

F1_2_1

F1_2_2

F1_2_3

F1_2_4

F1_2_5

F1_2_6*

F0_2_5*

F0_2_6

CCLK

F2_2_5*

F2_2_6

V_CC

DONE

RESETN

PGRM

*Represents multi-function pins

DS033 (v1.1) February 10, 2000

www.xilinx.com

1-800-255-7778

40

R

XCR3320: 320 Macrocell SRAM CPLD

160 Pin Description Table

Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.

Table 18: Pin Function Description

Symbol

Pin Number Type

Description

V_CC

15, 23, 40, 53,

62, 71, 80, 81,

99, 106, 121,

130, 139, 148

-

Positive power supply.

Ground supply.

GND

8, 17, 24, 32,

47, 60, 64, 77,

89, 98, 104,

113, 124, 137,

141, 154

-

resetn

159

I

During configuration, resetn forces the start of initialization. After configuration,

resetn is a direct input which can be used to asynchronously reset all the flip-flops. If

the global reset is not being used, this pin should be pulled High. If the rise time of

the prgmn signal is greater than 1 µs, this signal must be held low until prgmn is High.

cclk

157

158

I/O In the master modes, cclk is an output which strobes configuration data in. In the

slave or synchronous peripheral mode, cclk is an input synchronous with the data on

din or D[7:0]. After configuration, this pin should be pulled Low.

done

I/O done is a bi-directional signal with a weak pull-up resistor attached. As an output,

done pulling High indicates configuration is complete. As an input, a Low level on

done will delay the enabling of user I/O. If only one device is used, this pin can be left