XC7Z020-2CLG484Q_技术文档

Kintex-7 FPGAs Data Sheet:

DC and AC Switching Characteristics

DS182 (v1.9) October 10, 2012

Preliminary Product Specification

Introduction

Kintex™-7 FPGAs are available in -3, -2, -1, and -2L speed

grades, with -3 having the highest performance. The -2L

characteristics of a -1 speed grade industrial device are the

same as for a -1 speed grade commercial device). However,

only selected speed grades and/or devices are available in

each temperature range.

devices can operate at either of two V

voltages, 0.9V

CCINT

and 1.0V and are screened for lower maximum static power.

When operated at V = 1.0V, the speed specification of

CCINT

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The

parameters included are common to popular designs and

typical applications.

a -2L device is the same as the -2 speed grade. When

operated at V = 0.9V, the -2L performance and static

CCINT

and dynamic power is reduced.

Kintex-7 FPGA DC and AC characteristics are specified in

commercial, extended, and industrial temperature ranges.

Except the operating temperature range or unless

otherwise noted, all the DC and AC electrical parameters

are the same for a particular speed grade (that is, the timing

This Kintex-7 FPGA data sheet, part of an overall set of

documentation on the 7 series FPGAs, is available on the

Xilinx website at www.xilinx.com/7.

All specifications are subject to change without notice.

DC Characteristics

Table 1: Absolute Maximum Ratings

(1)

Symbol

FPGA Logic

V_CCINT

Description

Min

Max

Units

Internal supply voltage

Auxiliary supply voltage

–0.5

1.1

2.0

V

V_CCAUX

Supply voltage for the block RAM memories

Output drivers supply voltage for 3.3V HR I/O banks

Output drivers supply voltage for 1.8V HP I/O banks

Auxiliary supply voltage

1.1

V_CCBRAM

3.6

V_CCO

2.0

2.06

2.0

V_{CCAUX_IO}

V_REF

Input reference voltage

I/O input voltage

V_CCO+ 0.5

2.625

2.0

(2)(3)(4)

V_IN

I/O input voltage for V_REFand differential I/O standards.

Key memory battery backup supply

V_CCBATT

GTX Transceiver

V_MGTAVCC

Analog supply voltage for the GTX transmitter and receiver circuits

Analog supply voltage for the GTX transmitter and receiver termination circuits

Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers

GTX transceiver reference clock absolute input voltage

–0.5

1.1

1.32

1.935

1.32

V

V_MGTAVTT

V_MGTVCCAUX

V_MGTREFCLK

Analog supply voltage for the resistor calibration circuit of the GTX transceiver

column

V_MGTAVTTRCAL

V_IN

Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage

–0.5

1.26

V

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Preliminary Product Specification

1

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

(1)

Table 1: Absolute Maximum Ratings

(Cont’d)

Description

Symbol

Min

–

Max

14

Units

mA

I_DCIN

DC input current for receiver input pins DC coupled V_MGTAVTT= 1.2V

DC output current for transmitter pins DC coupled V_MGTAVTT= 1.2V

–

I_DCOUT

XADC

14

mA

XADC supply relative to GNDADC

–0.5

2.0

V

V_CCADC

V_REFP

XADC reference input relative to GNDADC

Temperature

T_STG

Storage temperature (ambient)

–65

–

150

°C

Maximum soldering temperature for Pb/Sn component bodies ⁽⁶⁾

Maximum soldering temperature for Pb-free component bodies ⁽⁶⁾

Maximum junction temperature⁽⁶⁾

+220

+260

+125

T_SOL

–

T_j

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. The lower absolute voltage specification always applies.

3. For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide.

4. The maximum limit applied to DC and AC signals.

5. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.

6. For soldering guidelines and thermal considerations, see UG475: 7 Series FPGA Packaging and Pinout Specification.

(1)

Table 2: Recommended Operating Conditions

Symbol

Description

Min

Typ

Max

Units

FPGA Logic

Internal supply voltage

0.97

0.87

0.97

0.87

1.71

1.14

1.71

1.94

–0.20

–

1.00

0.90

1.00

0.90

1.80

–

1.03

0.93

V

(2)

V_CCINT

For -2L (0.9V) devices: internal supply voltage

Block RAM supply voltage

1.03

V

(2)

V_CCBRAM

For -2L (0.9V) devices: block RAM supply voltage

Auxiliary supply voltage

1.03

V

V_CCAUX

1.89

V

Supply voltage for 3.3V HR I/O banks

Supply voltage for 1.8V HP I/O banks

Auxiliary supply voltage when set to 1.8V

Auxiliary supply voltage when set to 2.0V

I/O input voltage

3.465

1.89

V

(3)(4)

V_CCO

–

V

1.80

2.00

–

1.89

V

V_{CCAUX_IO}

2.06

V

V_CCO+ 0.2

2.625

10

V

(5)

V_IN

I/O input voltage for V_REFand differential I/O standards

–

V

Maximum current through any pin in a powered or unpowered bank when

forward biasing the clamp diode.

–

mA

(6)

I_IN

(7)

V_CCBATT

Battery voltage

1.0

–

1.89

V

GTX Transceiver

Analog supply voltage for the GTX transceiver QPLL frequency range

0.97

1.02

1.0

1.08

V

≤ 10.3125 GHz^(9)(10)

(8)

V_MGTAVCC

Analog supply voltage for the GTX transceiver QPLL frequency range

> 10.3125 GHz

1.05

Analog supply voltage for the GTX transmitter and receiver termination

circuits

(8)

V_MGTAVTT

1.17

1.75

1.2

1.23

1.85

V

(8)

V_MGTVCCAUX

Auxiliary analog QPLL voltage supply for the transceivers

1.80

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Preliminary Product Specification

2

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

(1)

Table 2: Recommended Operating Conditions

(Cont’d)

Symbol

Description

Min

Typ

Max

Units

Analog supply voltage for the resistor calibration circuit of the GTX

transceiver column

(8)

V_MGTAVTTRCAL

1.17

1.2

1.23

V

XADC

V_CCADC

V_REFP

XADC supply relative to GNDADC

Externally supplied reference voltage

1.71

1.20

1.80

1.25

1.89

1.30

V

Temperature

Junction temperature operating range for commercial (C) temperature

devices

0

–

85

°C

T_j

Junction temperature operating range for extended (E) temperature

devices

100

Junction temperature operating range for industrial (I) temperature devices

–40

Notes:

1. All voltages are relative to ground.

2. and V should be connected to the same supply.

3. Configuration data is retained even if V

V

CCINT

CCBRAM

drops to 0V.

CCO

4. Includes V

of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.

CCO

5. The lower absolute voltage specification always applies.

6. A total of 200 mA per bank should not be exceeded.

7.

V

is required only when using bitstream encryption. If battery is not used, connect V

to either ground or V

.

CCAUX

CCBATT

8. Each voltage listed requires the filter circuit described in UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide.

9. For data rates ≤ 10.3125 Gb/s, V

10. For lower power consumption, V

should be 1.0V 3ꢀ for lower power consumption.

should be 1.0V 3ꢀ over the entire CPLL frequency range.

MGTAVCC

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol

V_DRINT

Description

Min

0.75

1.5

–

Typ⁽¹⁾

Max

–

Units

V

Data retention V_CCINTvoltage (below which configuration data might be lost)

Data retention V_CCAUXvoltage (below which configuration data might be lost)

V_REFleakage current per pin

–

V_DRI

I_REF

I_L

–

V

15

µA

pF

µA

mA

nA

Input or output leakage current per pin (sample-tested)

Die input capacitance at the pad

–

15

(2)

C_IN

–

8

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.3V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 2.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.2V

Pad pull-down (when selected) @ V_IN= 3.3V

90

68

34

23

12

68

45

–

330

250

220

150

120

330

180

25

I_RPU

I_RPD

Pad pull-down (when selected) @ V_IN= 1.8V

I_CCADC

Analog supply current, analog circuits in powered up state

Battery supply current

(3)

I_BATT

–

150

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Preliminary Product Specification

3

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)

Symbol

Description

Min

Typ⁽¹⁾

Max

Units

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E)

temperature devices

28

40

55

Ω

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E)

temperature devices

35

44

50

60

65

83

Ω

(4)

R_{IN_TERM}

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E)

temperature devices

n

r

Temperature diode ideality factor

–

1.010

2

–

Temperature diode series resistance

Ω

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. This measurement represents the die capacitance at the pad, not including the package.

3. Maximum value specified for worst case process at 25°C.

4. Termination resistance to a V

/2 level.

CCO

(1)

Table 4: Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks

AC Voltage Overshoot

V_CCO+ 0.40

% of UI @–40°C to 100°C

AC Voltage Undershoot

% of UI @–40°C to 100°C

100

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

100

61.7

25.8

11.0

4.77

2.10

0.94

0.43

0.20

0.09

0.04

0.02

V_CCO+ 0.45

V_CCO+ 0.50

100

V_CCO+ 0.55

V_CCO+ 0.60

100

46.6

21.2

9.75

4.55

2.15

1.02

0.49

0.24

V_CCO+ 0.65

V_CCO+ 0.70

V_CCO+ 0.75

V_CCO+ 0.80

V_CCO+ 0.85

V_CCO+ 0.90

V_CCO+ 0.95

Notes:

1. A total of 200 mA per bank should not be exceeded.

(1)(2)

Table 5: Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks

AC Voltage Overshoot

% of UI @–40°C to 100°C

AC Voltage Undershoot

% of UI @–40°C to 100°C

V_CCO+ 0.40

100

50.0

47.0

21.2

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

100

50.0

V_CCO+ 0.45

V_CCO+ 0.50

V_CCO+ 0.55

V_CCO+ 0.60

V_CCO+ 0.65

V

_CCO+ 0.70

_CCO+ 0.75

V

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Preliminary Product Specification

4

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

(1)(2)

Table 5: Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks

(Cont’d)

AC Voltage Overshoot

% of UI @–40°C to 100°C

AC Voltage Undershoot

% of UI @–40°C to 100°C

V_CCO+ 0.80

9.71

4.51

2.12

1.01

–0.80

–0.85

–0.90

–0.95

50.0

28.4

12.7

5.79

V_CCO+ 0.85

V_CCO+ 0.90

V_CCO+ 0.95

Notes:

1. A total of 200 mA per bank should not be exceeded.

2. For UI smaller than 20 µs.

Table 6: Typical Quiescent Supply Current

Speed Grade

Symbol

Description

Device

1.0V

-2/-2L

241

474

810

993

1080

1313

1

0.9V

-2L

187

368

629

771

838

1019

1

Units

-3

241

474

810

993

1080

1313

1

-1

241

474

810

993

1080

1313

1

I_CCINTQ

Quiescent V_CCINTsupply current

XC7K70T

mA

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

XC7K70T

I_CCOQ

Quiescent V_CCOsupply current

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

XC7K70T

1

I_CCAUXQ

Quiescent V_CCAUXsupply current

21

40

68

75

85

99

N/A

2

21

40

68

75

85

99

N/A

2

21

40

68

75

85

99

N/A

2

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

40

68

75

85

99

I_{CCAUX_IOQ}Quiescent V_{CCAUX_IO}supply current XC7K70T

N/A

2

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

2

N/A

2

N/A

2

N/A

2

N/A

2

N/A

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Preliminary Product Specification

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 6: Typical Quiescent Supply Current (Cont’d)

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

6

Units

-3

6

-2/-2L

6

-1

6

I_CCBRAMQQuiescent V_CCBRAMsupply current

XC7K70T

mA

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

14

19

31

34

41

14

19

31

34

41

14

19

31

34

41

19

31

34

41

Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ) with single-ended SelectIO resources.

j

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. Use the XPower™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for

conditions other than those specified.

Power-On/Off Power Supply Sequencing

The recommended power-on sequence is V

, V

, and V

to achieve minimum current

CCO

CCINT CCBRAM

CCAUX

CCAUX_IO

draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-

on sequence. If V and V have the same recommended voltage levels then both can be powered by the same

CCINT

CCBRAM

supply and ramped simultaneously. If V

, V

, and V

have the same recommended voltage levels then they

CCAUX CCAUX_IO

CCO

can be powered by the same supply and ramped simultaneously.

For V voltages of 3.3V in HR I/O banks and configuration bank 0:

CCO

•

The voltage difference between V

power-on/off cycle to maintain device reliability levels.

and V

must not exceed 2.625V for longer than T

for each

CCO

CCAUX

VCCO2VCCAUX

The T time can be allocated in any percentage between the power-on and power-off ramps.

VCCO2VCCAUX

The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is V

, V

,

CCINT MGTAVCC

V

OR V

, V

. There is no recommended sequencing for V

. Both V

and

MGTAVTT

MGTAVCC CCINT MGTAVTT

MGTVCCAUX

MGTAVCC

can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to

CCINT

achieve minimum current draw.

If these recommended sequences are not met, current drawn from V

power-up and power-down.

can be higher than specifications during

MGTAVTT

•

When V

is powered before V

and V

– V

> 150 mV and V

< 0.7V, the

MGTAVTT

MGTAVCC

MGTAVTT

MGTAVCC

V

current draw can increase by 460 mA per transceiver during V

ramp up. The duration of the current

MGTAVTT

MGTAVCC

draw can be up to 0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

MGTAVCC

•

When V

is powered before V

and V

– V

> 150 mV and V

< 0.7V, the V

current

MGTAVTT

CCINT

MGTAVTT

CCINT

draw can increase by 50 mA per transceiver during V

ramp up. The duration of the current draw can be up to

CCINT

0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

VCCINT

CCINT

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Preliminary Product Specification

6

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 7 shows the minimum current, in addition to I

, that are required by Kintex-7 devices for proper power-on and

CCQ

configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have

passed through their power-on reset threshold voltages. The FPGA must not be configured until after V

is applied.

CCINT

Once initialized and configured, use the XPower tools to estimate current drain on these supplies.

Table 7: Power-On Current for Kintex-7 Devices

I_CCINTMIN

Typ⁽¹⁾

I_CCAUXMIN

Typ⁽¹⁾

I_CCOMIN

Typ⁽¹⁾

I_{CCAUX_IOMIN}

Typ⁽¹⁾

I_CCBRAMMIN

Typ⁽¹⁾

Device

Units

XC7K70T

I_CCINTQ+ 450

I_CCINTQ+ 550

I_CCINTQ+ 600

I_CCAUXQ+ 40 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

I_CCAUXQ+ 50 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

I_CCAUXQ+ 80 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 40

mA

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

I

_CCINTQ+ 1450 I_CCAUXQ+ 109 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 81

I_CCINTQ+ 1500 I_CCAUXQ+ 125 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 90

I_CCINTQ+ 2200 I_CCAUXQ+ 180 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 108

I

_CCINTQ+ 2200 I_CCAUXQ+ 180 I_CCOQ+ 40 mA per bank I_CCOAUXIOQ+ 40 mA per bank I_CCBRAMQ+ 108

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. Use the XPower Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.

Table 8: Power Supply Ramp Time

Symbol

T_VCCINT

Description

Ramp time from GND to 90ꢀ of V_CCINT

Ramp time from GND to 90ꢀ of V_CCO

Ramp time from GND to 90ꢀ of V_CCAUX

Ramp time from GND to 90ꢀ of V_{CCAUX_IO}

Ramp time from GND to 90ꢀ of V_CCBRAM

Conditions

Min

0.2

–

Max

50

Units

ms

T_VCCO

50

ms

T_VCCAUX

T_{VCCAUX_IO}

T_VCCBRAM

50

ms

50

ms

50

ms

T_J= 100°C⁽¹⁾

T_J= 85°C⁽¹⁾

500

800

50

T_VCCO2VCCAUX

Allowed time per power cycle for V_CCO– V_CCAUX> 2.625V

ms

–

T_MGTAVCC

T_MGTAVTT

Ramp time from GND to 90ꢀ of V_MGTAVCC

Ramp time from GND to 90ꢀ of V_MGTAVTT

Ramp time from GND to 90ꢀ of V_MGTVCCAUX

0.2

ms

50

T_MGTVCCAUX

50

Notes:

1. Based on 240,000 power cycles with nominal V

of 3.3V or 36,500 power cycles with a worst case V

of 3.465V.

CCO

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Preliminary Product Specification

7

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

DC Input and Output Levels

Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended

IL

IH

OL

OH

operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that

OL

OH

all standards meet their specifications. The selected standards are tested at a minimum V

with the respective V and

CCO

OL

V

voltage levels shown. Other standards are sample tested.

OH

(1)(2)

Table 9: SelectIO DC Input and Output Levels

V_IL

V_IH

V_OL

V, Max

0.400

V_OH

I_OL

mA

8

I_OH

mA

–8

I/O Standard

V, Min

–0.300

V, Max

V, Min

V, Max

V, Min

HSTL_I

V_REF– 0.100

V_REF+ 0.100 V_CCO+ 0.300

V_REF+ 0.080 V_CCO+ 0.300

V_REF+ 0.100 V_CCO+ 0.300

V_REF+ 0.130 V_CCO+ 0.300

V_CCO– 0.400

75ꢀ V_CCO

HSTL_I_12

HSTL_I_18

HSTL_II

V

_REF– 0.080

25ꢀ V_CCO

0.400

6.3

8

–6.3

–8

V_REF– 0.100

V_CCO– 0.400

80ꢀ V_CCO

0.400

16

0.1

–16

–0.1

HSTL_II_18

HSUL_12

LVCMOS12

V

_REF– 0.100

0.400

V_REF– 0.130

35ꢀ V_CCO

20ꢀ V_CCO

0.400

65ꢀ V_CCO

V_CCO+ 0.300

V_CCO– 0.400 Note 3 Note 3

75ꢀ V_CCONote 4 Note 4

LVCMOS15,

LVDCI_15

25ꢀ V_CCO

LVCMOS18,

LVDCI_18

–0.300

35ꢀ V_CCO

65ꢀ V_CCO

V_CCO+ 0.300

0.450

V_CCO– 0.450 Note 5 Note 5

LVCMOS25

LVCMOS33

LVTTL

–0.300

–0.500

–0.300

0.700

0.800

1.700

2.000

V_CCO+ 0.300

3.450

0.400

V_CCO– 0.400 Note 6 Note 6

0.800

2.000

3.450

0.400

2.400

Note 7 Note 7

MOBILE_DDR

PCI33_3

20ꢀ V_CCO

30ꢀ V_CCO

80ꢀ V_CCO

50ꢀ V_CCO

V_CCO+ 0.300

V_CCO+ 0.500

10ꢀ V_CCO

90ꢀ V_CCO

0.1

1.5

–0.1

–0.5

SSTL12

V

_REF– 0.100

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 14.25

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 13.0

–14.25

–13.0

–8.9

SSTL135

SSTL135_R

SSTL15

V_REF– 0.090

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150

8.9

V

_REF– 0.100

V_REF– 0.100

_REF– 0.125

V_REF– 0.125

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175 13.0

–13.0

–8.9

SSTL15_R

SSTL18_I

SSTL18_II

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.470 V_CCO/2 + 0.470

8.9

8

V

–8

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.600 V_CCO/2 + 0.600 13.4

–13.4

Notes:

1. Tested according to relevant specifications.

2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks.

3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.

4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.

5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.

6. Supported drive strengths of 4, 8, 12, or 16 mA

7. Supported drive strengths of 4, 8, 12, 16, or 24 mA

8. For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

8

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 10: Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Min V, Typ V, Max V, Min V, Typ V, Max

0.300 1.200 1.425 0.100

V_ID

V_OCM

V_OD

I/O Standard

V, Min

–

V, Typ

1.250

1.200

0.950

1.200

V, Max

–

V, Min V, Typ V, Max

Note 5

BLVDS_25

–

MINI_LVDS_25 0.300 1.200 V_CCAUX0.200 0.400 0.600

1.000

0.500

1.000

1.400

0.300 0.450 0.600

0.100 0.250 0.400

0.100 0.350 0.600

PPDS_25

RSDS_25

TMDS_33

0.200 0.900 V_CCAUX0.100 0.250 0.400

0.300 0.900

2.700 2.965

1.500

3.230

0.100 0.350 0.600

0.150 0.675 1.200 V_CCO–0.405 V_CCO–0.300 V_CCO–0.190 0.400 0.600 0.800

Notes:

1.

2.

3.

4.

5.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

ICM

ID

is the output common mode voltage.

OCM

is the output differential voltage (Q – Q).

for BLVDS will vary significantly depending on topology and loading.

OD

6. LVDS_25 is specified in Table 12.

7. LVDS is specified in Table 13.

Table 11: Complementary Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Typ V, Max V, Min V, Max

V_ID

V_OL

V_OH

I_OL

I_OH

I/O Standard

V, Min

0.300

V, Max

0.400

V, Min

mA, Max mA, Min

DIFF_HSTL_I

0.750

0.900

0.750

0.900

0.600

0.900

0.600

0.675

0.750

0.900

1.125

1.425

1.125

1.425

0.850

1.425

0.850

1.000

1.125

1.425

0.100

–

V_CCO–0.400

8.00

16.00

0.100

14.25

13.0

8.9

–8.00

–16.00

–0.100

–14.25

–13.0

–8.9

DIFF_HSTL_I_18

DIFF_HSTL_II

0.400

V

_CCO–0.400

DIFF_HSTL_II_18

DIFF_HSUL_12

DIFF_MOBILE_DDR

DIFF_SSTL12

0.400

20ꢀ V_CCO

10ꢀ V_CCO

80ꢀ V_CCO

90ꢀ V_CCO

(V_CCO/2) – 0.150 (V_CCO/2) + 0.150

(V_CCO/2) – 0.175 (V_CCO/2) + 0.175

(V_CCO/2) – 0.470 (V_CCO/2) + 0.470

(V_CCO/2) – 0.600 (V_CCO/2) + 0.600

DIFF_SSTL135

DIFF_SSTL135_R

DIFF_SSTL15

13.0

8.9

–13.0

–8.9

DIFF_SSTL15_R

DIFF_SSTL18_I

DIFF_SSTL18_II

8.00

13.4

–8.00

–13.4

Notes:

1.

2.

3.

4.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

is the single-ended low-output voltage.

ICM

ID

OL

OH

is the single-ended high-output voltage.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

9

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

LVDS DC Specifications (LVDS_25)

The LVDS_25 standard is available in the HR I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for

more information.

Table 12: LVDS_25 DC Specifications

Symbol

V_CCO

V_OH

DC Parameter

Supply Voltage

Conditions

Min

2.375

–

Typ

2.500

–

Max

2.625

1.675

–

Units

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R_T= 100 Ω across Q and Q signals

V

V_OL

0.700

247

–

V

Differential Output Voltage (Q – Q),

Q = High (Q – Q), Q = High

350

600

mV

V_ODIFF

V_OCM

V_IDIFF

V_ICM

Output Common-Mode Voltage

R_T= 100 Ω across Q and Q signals

1.000

100

1.250

350

1.425

600

V

Differential Input Voltage (Q – Q),

Q = High (Q – Q), Q = High

mV

Input Common-Mode Voltage

0.300

1.200

1.425

V

LVDS DC Specifications (LVDS)

The LVDS standard is available in the HP I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for more

information.

Table 13: LVDS DC Specifications

Symbol

V_CCO

V_OH

DC Parameter

Supply Voltage

Conditions

Min

1.710

–

Typ

1.800

–

Max

1.890

1.675

–

Units

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R_T= 100 Ω across Q and Q signals

V

V_OL

0.825

247

–

V

Differential Output Voltage (Q – Q),

Q = High (Q – Q), Q = High

350

600

mV

V_ODIFF

V_OCM

V_IDIFF

V_ICM

Output Common-Mode Voltage

R_T= 100 Ω across Q and Q signals

1.000

100

1.250

350

1.425

600

V

Differential Input Voltage (Q – Q),

Q = High (Q – Q), Q = High

Common-mode input voltage = 1.25V

mV

Input Common-Mode Voltage

Differential input voltage = 350 mV

0.300

1.200

1.425

V

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

10

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

AC Switching Characteristics

All values represented in this data sheet are based on the speed specifications in ISE® software 14.2 v1.06 for the

-3, -2, -2L(1.0V), -1, and v1.05 for -2L(0.9V) speed grades.

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or

Production. Each designation is defined as follows:

Advance Product Specification

These specifications are based on simulations only and are typically available soon after device design specifications are

frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-

reporting might still occur.

Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades

with this designation are intended to give a better indication of the expected performance of production silicon. The

probability of under-reporting delays is greatly reduced as compared to Advance data.

Production Product Specification

These specifications are released once enough production silicon of a particular device family member has been

characterized to provide full correlation between specifications and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest

speed grades transition to Production before faster speed grades.

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are

representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and

back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs.

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another depends

completely on the status of the fabrication process for each device. Table 14 correlates the current status of each Kintex-7

device on a per speed grade basis.

Table 14: Kintex-7 Device Speed Grade Designations

Speed Grade Designations

Device

Advance

Preliminary

Production

XC7K70T

-3 (1.0V) and -2L (0.9V)

-2L (0.9V)

-2, -2L(1.0V), -1

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

-2, -2L(1.0V), -1

-3, -2, -2L(1.0V), -1

-3 (1.0V) and -2L (0.9V)

-2L (0.9V)

-2, -2L(1.0V), -1

-3, -2, -2L(1.0V), -1

-2, -2L(1.0V), -1

-3 (1.0V) and -2L (0.9V)

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

11

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Production Silicon and ISE Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is

released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent

speed specification releases.

Table 15 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed

specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases

required for production. All subsequent releases of software and speed specifications are valid.

Table 15: Kintex-7 Device Production Software and Speed Specification Release

Speed Grade Designations

Device

1.0V

0.9V

-2L

-3

-2/-2L

-1

XC7K70T

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

ISE 14.2 v1.06

Notes:

1. Blank entries indicate a device and/or speed grade in advance or preliminary status.

Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in Kintex-7

devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject

to the same guidelines as the AC Switching Characteristics, page 11. In each table, the I/O bank type is either High

Performance (HP) or High Range (HR).

Table 16: Networking Applications Interface Performances

Speed Grade

I/O

Description

Bank

Type

1.0V

-2/-2L

710

0.9V

-2L

Units

-3

-1

SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)

DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)

SDR LVDS receiver (SFI-4.1)⁽¹⁾

HR

HP

HR

HP

HR

HP

HR

HP

710

625

950

1250

625

950

1250

Mb/s

710

1250

1600

710

1250

1400

710

DDR LVDS receiver (SPI-4.2)⁽¹⁾

1250

1600

1250

1400

Notes:

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate

deterministic performance.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

12

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

(1)(2)

Table 17: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FFG Packages)

Speed Grade

1.0V

Memory

Standard

I/O Bank Type

V_{CCAUX_IO}

0.9V

-2L

Units

-3

-2/-2L

-1

4:1 Memory Controllers

HP

2.0V

1.8V

N/A

1866

1600

1066

1600

1333

800

1866

1333

1066

1600

1066

800

1600

1066

800

1333

800

667

800

667

450

1333

1066

800

1066

800

667

800

533

450

Mb/s

MHz

DDR3

HP

HR

HP

HR

HP

HR

HP

HR

2.0V

1.8V

N/A

DDR3L

2.0V

1.8V

N/A

800

DDR2

800

2.0V

1.8V

N/A

800

667

RLDRAM III⁽³⁾

550

500

N/A

2:1 Memory Controllers

HP

2.0V

1.8V

N/A

1066

800

1066

800

667

800

667

Mb/s

DDR3

HP

HR

HP

HR

HP

HR

HP

HR

HP

HR

HP

HR

2.0V

1.8V

N/A

DDR3L

2.0V

1.8V

N/A

DDR2

800

Mb/s

2.0V

1.8V

N/A

550

500

450

400

450

400

MHz

QDR II+⁽⁴⁾

RLDRAM II

2.0V

1.8V

N/A

533

500

450

MHz

2.0V

1.8V

N/A

800

667

800

667

800

667

Mb/s

LPDDR2⁽³⁾

Notes:

1.

V

tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide.

REF

2. When using the internal V , the maximum data rate is 800 Mb/s (400 MHz).

REF

3. RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP.

4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations

are limited to 333 MHz for all speed grades and I/O bank types.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

13

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

(1)(2)

Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FBG Packages)

Speed Grade

1.0V

Memory

Standard

(3)

I/O Bank Type

V_{CCAUX_IO}

0.9V

-2L

Units

-3

-2/-2L

-1

4:1 Memory Controllers

HP

N/A

1333

1066

800

1066

800

667

500

800

667

800

667

450

800

667

800

667

450

Mb/s

MHz

DDR3

HR

HP

DDR3L

HR

HP

800

DDR2

HR

800

HP

RLDRAM III⁽⁴⁾

HR

550

N/A

2:1 Memory Controllers

HP

N/A

1066

800

1066

800

667

500

400

800

667

800

667

450

350

800

667

800

667

450

350

Mb/s

MHz

DDR3

HR

HP

DDR3L

HR

HP

800

DDR2

HR

800

HP

550

QDR II+⁽⁵⁾

HR

450

HP

RLDRAM II

HR

533

500

450

MHz

HP

667

533

667

533

Mb/s

LPDDR2⁽⁴⁾

HR

Notes:

1.

V

tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide.

REF

2. When using the internal V , the maximum data rate is 800 Mb/s (400 MHz).

REF

3. FBG packages do not have separate V

supply pins to adjust the pre-driver voltage of the HP I/O banks.

CCAUX_IO

4. RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP.

5. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations

are limited to 333 MHz for all speed grades and I/O bank types.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

14

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

IOB Pad Input/Output/3-State

Table 19 (3.3V high-range IOB (HR)) and Table 20 (1.8V high-performance IOB (HP)) summarizes the values of standard-

specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

•

T

is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies

IOPI

depending on the capability of the SelectIO input buffer.

T

is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies

IOOP

depending on the capability of the SelectIO output buffer.

T

is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is

IOTP

disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI

termination turn-on time is always faster than T when the DCITERMDISABLE pin is used. In HR I/O banks, the

IOTP

IN_TERM termination turn-on time is always faster than T

when the INTERMDISABLE pin is used.

IOTP

Table 19: 3.3V IOB High Range (HR) Switching Characteristics

T_IOPI

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

Speed Grade

I/O Standard

Units

1.0V

-2/-2L

1.42

0.68

0.70

0.69

0.68

0.69

0.76

1.41

0.64

0.61

0.64

0.67

0.69

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

LVTTL_S4

1.31

0.64

0.68

0.65

0.63

0.65

0.72

1.28

0.63

0.58

0.61

0.64

0.63

0.65

1.64 1.49

5.27

4.45

3.47

3.58

4.70

3.66

2.57

2.41

1.36

1.83

1.36

1.43

2.71

2.06

1.83

1.55

1.21

1.28

1.18

1.42

1.15

1.27

1.14

5.63 6.05

4.83 5.30

4.83 5.29

3.88 4.40

3.99 4.51

4.98 5.29

4.06 4.56

2.85 3.15

2.64 2.89

1.47 1.55

2.02 2.20

1.48 1.55

1.49 1.58

1.54 1.60

3.08 3.52

2.31 2.59

2.04 2.26

1.69 1.80

1.34 1.43

1.39 1.45

1.31 1.40

1.54 1.61

1.24 1.27

1.38 1.43

1.23 1.26

6.52

5.78

4.85

4.94

5.88

4.99

4.97

3.76

3.55

2.16

2.74

2.16

2.22

3.64

3.07

2.77

2.40

2.06

2.14

2.06

2.24

2.13

2.07

2.08

6.03 6.49 7.04

5.21 5.69 6.29

5.21 5.69 6.28

4.23 4.74 5.39

4.34 4.85 5.50

5.46 5.84 6.28

4.42 4.92 5.55

3.33 3.71 4.14

3.17 3.50 3.88

2.12 2.33 2.54

2.59 2.88 3.19

2.12 2.34 2.54

2.12 2.35 2.57

2.19 2.40 2.59

3.47 3.94 4.51

2.82 3.17 3.58

2.59 2.90 3.25

2.31 2.55 2.79

1.97 2.20 2.42

2.04 2.25 2.44

1.94 2.17 2.39

2.18 2.40 2.60

1.91 2.10 2.26

2.03 2.24 2.42

1.90 2.09 2.25

7.75

7.01

6.08

6.18

7.12

6.22

6.21

5.00

4.79

3.40

3.97

3.40

3.46

4.88

4.31

4.01

3.64

3.29

3.37

3.29

3.48

3.37

3.31

ns

LVTTL_S8

LVTTL_S12

1.64

1.49

LVTTL_S16

LVTTL_S24

LVTTL_F4

1.64 1.49

LVTTL_F8

LVTTL_F12

1.64

1.49

LVTTL_F16

LVTTL_F24

LVDS_25⁽¹⁾

0.80 0.70

0.79 0.69

0.80 0.71

0.79 0.70

0.80 0.72

0.86 0.78

1.65 1.48

0.71 0.63

0.70 0.63

MINI_LVDS_25

BLVDS_25⁽¹⁾

RSDS_25 (point to point)⁽¹⁾

PPDS_25⁽¹⁾

TMDS_33⁽¹⁾

PCI33_3⁽¹⁾

HSUL_12

DIFF_HSUL_12

HSTL_I_S

0.73

0.64

HSTL_II_S

0.73 0.64

0.76 0.66

0.77 0.69

0.78 0.70

HSTL_I_18_S

HSTL_II_18_S

DIFF_HSTL_I_S

DIFF_HSTL_II_S

DIFF_HSTL_I_18_S

DIFF_HSTL_II_18_S

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Preliminary Product Specification

15

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 19: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.64

0.67

0.69

1.40

1.16

0.66

0.69

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

HSTL_I_F

0.61

0.64

0.63

0.65

1.31

1.08

0.64

0.66

0.73

0.64

1.10

1.05

1.03

1.09

1.02

1.08

1.01

5.23

4.46

3.46

3.06

4.70

3.62

2.57

2.44

4.49

3.66

2.77

3.24

3.96

2.43

2.23

1.92

3.24

2.58

1.82

1.74

3.12

1.91

1.52

1.34

3.48

2.37

1.83

1.19 1.23

1.18 1.28

1.14 1.23

1.18 1.22

1.11 1.14

1.17 1.21

1.10 1.13

5.61 6.09

4.85 5.33

3.89 4.42

3.43 3.88

5.01 5.36

4.04 4.56

2.85 3.15

2.69 2.96

4.80 5.16

4.04 4.49

3.10 3.49

3.62 4.09

4.31 4.72

2.87 3.42

2.63 3.13

2.17 2.45

3.45 3.66

2.91 3.31

2.03 2.24

1.92 2.08

3.31 3.49

2.13 2.36

1.68 1.81

1.46 1.55

3.74 4.03

2.67 3.01

2.03 2.23

1.94

1.85

1.92

1.83

1.88

1.85

1.86

6.51

5.78

4.84

4.37

5.87

4.97

3.76

3.60

5.54

4.79

3.86

4.36

5.05

3.67

3.41

2.92

4.18

3.66

2.77

2.66

4.05

2.87

2.41

2.19

4.54

3.40

2.78

1.86 2.05 2.22

1.81 2.04 2.27

1.79 2.00 2.22

1.85 2.04 2.21

1.78 1.97 2.13

1.84 2.03 2.20

1.77 1.96 2.12

5.99 6.47 7.08

5.22 5.71 6.32

4.22 4.75 5.41

3.82 4.29 4.87

5.46 5.87 6.35

4.38 4.90 5.55

3.33 3.71 4.14

3.20 3.55 3.95

5.25 5.66 6.15

4.42 4.90 5.48

3.53 3.96 4.48

4.00 4.48 5.08

4.72 5.17 5.71

3.19 3.73 4.41

2.99 3.49 4.12

2.68 3.03 3.44

4.00 4.31 4.65

3.34 3.77 4.30

2.58 2.89 3.23

2.50 2.78 3.07

3.88 4.17 4.48

2.67 2.99 3.35

2.28 2.54 2.80

2.10 2.32 2.54

4.24 4.60 5.02

3.13 3.53 4.00

2.59 2.89 3.22

3.18

3.08

3.16

3.07

3.11

3.09

3.10

7.75

7.02

6.07

5.61

7.10

6.20

4.99

4.83

6.77

6.02

5.10

5.60

6.29

4.90

4.65

4.16

5.41

4.89

4.01

3.90

5.28

4.11

3.65

3.43

5.78

4.63

4.02

ns

HSTL_II_F

0.73 0.64

0.76 0.66

0.77 0.69

0.78 0.70

1.60 1.49

1.32 1.25

0.74 0.75

0.81 0.78

HSTL_I_18_F

HSTL_II_18_F

DIFF_HSTL_I_F

DIFF_HSTL_II_F

DIFF_HSTL_I_18_F

DIFF_HSTL_II_18_F

LVCMOS33_S4

LVCMOS33_S8

LVCMOS33_S12

LVCMOS33_S16

LVCMOS33_F4

LVCMOS33_F8

LVCMOS33_F12

LVCMOS33_F16

LVCMOS25_S4

LVCMOS25_S8

LVCMOS25_S12

LVCMOS25_S16

LVCMOS25_F4

LVCMOS25_F8

LVCMOS25_F12

LVCMOS25_F16

LVCMOS18_S4

LVCMOS18_S8

LVCMOS18_S12

LVCMOS18_S16

LVCMOS18_S24⁽¹⁾

LVCMOS18_F4

LVCMOS18_F8

LVCMOS18_F12

LVCMOS18_F16

LVCMOS18_F24⁽¹⁾

LVCMOS15_S4

LVCMOS15_S8

LVCMOS15_S12

DS182 (v1.9) October 10, 2012

www.xilinx.com

Preliminary Product Specification

16

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 19: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.69

0.91

0.64

0.67

0.61

0.67

0.69

0.64

0.67

0.61

0.67

0.69

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

LVCMOS15_S16

0.66

0.88

0.61

0.64

0.59

0.63

0.65

0.61

0.64

0.59

0.63

0.65

0.81 0.78

1.00 0.89

0.73 0.61

0.73 0.64

0.76 0.66

0.73 0.63

0.77 0.69

0.78 0.70

0.73 0.61

0.73 0.64

0.76 0.66

0.73 0.63

0.77 0.69

0.78 0.70

1.76

3.39

1.79

1.40

1.37

3.85

2.52

2.06

3.44

1.72

1.54

1.27

1.24

1.59

1.27

1.24

1.50

1.13

1.04

1.12

1.05

1.04

1.10

1.02

1.95 2.13

3.60 3.80

1.99 2.18

1.54 1.65

1.51 1.61

4.22 4.69

2.96 3.52

2.31 2.59

3.73 4.06

2.04 2.40

1.71 1.87

1.40 1.50

1.37 1.47

1.74 1.85

1.40 1.50

1.37 1.47

1.63 1.72

1.22 1.25

1.17 1.26

1.22 1.26

1.18 1.28

1.17 1.26

1.19 1.23

1.10 1.14

2.69

4.37

2.69

2.27

2.24

4.99

3.73

3.07

4.49

2.82

2.45

2.00

1.96

2.43

1.96

2.00

1.96

2.33

2.02

1.84

1.85

1.94

1.83

1.84

1.85

1.89

1.87

2.52 2.81 3.12

4.15 4.46 4.79

2.55 2.85 3.17

2.16 2.40 2.64

2.13 2.37 2.60

4.61 5.08 5.68

3.28 3.82 4.51

2.82 3.17 3.58

4.20 4.59 5.05

2.48 2.90 3.39

2.30 2.57 2.86

2.03 2.26 2.49

2.00 2.23 2.46

2.35 2.60 2.84

2.03 2.26 2.49

2.00 2.23 2.46

2.26 2.49 2.71

1.89 2.08 2.24

1.80 2.03 2.25

1.88 2.08 2.25

1.81 2.04 2.27

1.80 2.03 2.25

1.86 2.05 2.22

1.78 1.96 2.13

3.93

5.61

3.93

3.51

3.48

6.23

4.97

4.31

5.72

4.06

3.69

3.24

3.20

3.67

3.20

3.24

3.20

3.57

3.25

3.08

3.09

3.18

3.07

3.08

3.09

3.12

3.11

ns

LVCMOS15_F4

LVCMOS15_F8

LVCMOS15_F12

LVCMOS15_F16

LVCMOS12_S4

LVCMOS12_S8

LVCMOS12_S12⁽¹⁾

LVCMOS12_F4

LVCMOS12_F8

LVCMOS12_F12⁽¹⁾

SSTL135_S

SSTL15_S

SSTL18_I_S

SSTL18_II_S

DIFF_SSTL135_S

DIFF_SSTL15_S

DIFF_SSTL18_I_S

DIFF_SSTL18_II_S

SSTL135_F

SSTL15_F

SSTL18_I_F

SSTL18_II_F

DIFF_SSTL135_F

DIFF_SSTL15_F

DIFF_SSTL18_I_F

DIFF_SSTL18_II_F

Notes:

1. This I/O standard is only available in the 3.3V high-range (HR) banks.

DS182 (v1.9) October 10, 2012

www.xilinx.com

Preliminary Product Specification

17

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 20: 1.8V IOB High Performance (HP) Switching Characteristics

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.79

0.72

0.79

0.72

0.79

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

LVDS

0.75

0.69

0.68

0.70

0.68

0.70

0.75

0.68

0.70

0.68

0.70

0.75

0.92 0.89

0.82 0.92

1.05

1.65

1.15

1.05

1.12

1.06

1.14

1.11

1.05

1.15

1.11

1.05

1.11

1.15

1.05

1.15

1.05

1.12

1.06

1.11

1.05

1.11

1.02

0.97

1.04

0.98

1.02

1.04

0.97

1.02

1.04

0.98

1.04

1.02

0.97

1.02

1.17

1.24

1.70

2.43

1.80

1.71

1.74

1.71

1.80

1.74

1.71

1.80

1.74

1.71

1.74

1.80

1.71

1.80

1.71

1.74

1.71

1.74

1.71

1.74

1.64

1.62

1.65

1.64

1.63

1.65

1.62

1.64

1.65

1.63

1.65

1.64

1.62

1.64

1.68 1.92 2.06

2.29 2.59 2.87

1.79 2.03 2.20

1.69 1.93 2.08

1.75 2.00 2.16

1.70 1.94 2.08

1.78 2.02 2.20

1.74 1.99 2.15

1.69 1.93 2.08

1.78 2.03 2.20

1.74 1.99 2.15

1.69 1.92 2.06

1.74 1.99 2.15

1.79 2.03 2.20

1.69 1.93 2.08

1.78 2.03 2.20

1.69 1.93 2.08

1.75 2.00 2.16

1.70 1.94 2.08

1.74 1.99 2.15

1.69 1.92 2.06

1.74 1.99 2.15

1.66 1.90 2.04

1.61 1.84 1.97

1.68 1.91 2.06

1.62 1.85 1.98

1.65 1.88 2.03

1.67 1.91 2.06

1.61 1.84 1.97

1.66 1.90 2.04

1.67 1.91 2.06

1.61 1.85 1.98

1.67 1.91 2.06

1.66 1.90 2.04

1.61 1.84 1.97

1.66 1.90 2.04

2.56

3.29

2.67

2.57

2.60

2.57

2.66

2.60

2.57

2.66

2.60

2.57

2.60

2.67

2.57

2.66

2.57

2.60

2.57

2.60

2.57

2.60

2.50

2.48

2.51

2.50

2.49

2.51

2.48

2.50

2.51

2.50

2.51

2.50

2.48

2.50

ns

HSUL_12

1.84 2.05

1.28 1.38

1.17 1.26

1.24 1.34

1.18 1.26

1.27 1.37

1.23 1.33

1.17 1.26

1.28 1.38

1.23 1.33

1.16 1.24

1.23 1.33

1.28 1.38

1.17 1.26

1.28 1.38

1.17 1.26

1.24 1.34

1.18 1.26

1.23 1.33

1.16 1.24

1.23 1.33

1.14 1.22

1.08 1.15

1.16 1.24

1.09 1.16

1.13 1.21

1.16 1.24

1.08 1.15

1.14 1.22

1.16 1.24

1.09 1.16

1.16 1.24

1.14 1.22

1.08 1.15

1.14 1.22

DIFF_HSUL_12

HSTL_I_S

0.82

0.90

HSTL_II_S

0.82 0.90

0.82 0.89

0.82 0.90

0.82 0.89

0.92 0.89

HSTL_I_18_S

HSTL_II_18_S

HSTL_I_12_S

HSTL_I_DCI_S

HSTL_II_DCI_S

HSTL_II_T_DCI_S

HSTL_I_DCI_18_S

HSTL_II_DCI_18_S

HSTL_II _T_DCI_18_S

DIFF_HSTL_I_S

DIFF_HSTL_II_S

DIFF_HSTL_I_DCI_S

DIFF_HSTL_II_DCI_S

DIFF_HSTL_I_18_S

DIFF_HSTL_II_18_S

DIFF_HSTL_I_DCI_18_S

DIFF_HSTL_II_DCI_18_S

DIFF_HSTL_II _T_DCI_18_S

HSTL_I_F

0.82

0.90

HSTL_II_F

0.82 0.90

0.82 0.89

0.82 0.90

0.82 0.89

0.92 0.89

HSTL_I_18_F

HSTL_II_18_F

HSTL_I_12_F

HSTL_I_DCI_F

HSTL_II_DCI_F

HSTL_II_T_DCI_F

HSTL_I_DCI_18_F

HSTL_II_DCI_18_F

HSTL_II _T_DCI_18_F

DIFF_HSTL_I_F

DIFF_HSTL_II_F

DIFF_HSTL_I_DCI_F

DS182 (v1.9) October 10, 2012

www.xilinx.com

Preliminary Product Specification

18

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.79

0.50

0.62

0.67

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

DIFF_HSTL_II_DCI_F

DIFF_HSTL_I_18_F

DIFF_HSTL_II_18_F

DIFF_HSTL_I_DCI_18_F

DIFF_HSTL_II_DCI_18_F

DIFF_HSTL_II _T_DCI_18_F

LVCMOS18_S2

LVCMOS18_S4

LVCMOS18_S6

LVCMOS18_S8

LVCMOS18_S12

LVCMOS18_S16

LVCMOS18_F2

0.75

0.47

0.59

0.64

0.92 0.89

0.60 0.88

0.73 0.88

0.78 0.96

0.97

1.04

0.98

1.04

0.98

1.04

3.95

2.67

2.14

1.98

1.70

1.57

3.50

2.23

1.80

1.46

1.26

1.19

3.55

2.45

2.24

1.91

1.77

1.62

3.38

2.04

1.47

1.31

1.21

1.18

3.38

2.62

2.05

1.94

2.84

1.97

1.33

1.08 1.15

1.16 1.24

1.09 1.16

1.16 1.24

1.09 1.16

1.16 1.24

4.28 4.85

2.98 3.43

2.38 2.72

2.21 2.52

1.91 2.17

1.75 1.97

3.87 4.48

2.50 2.87

2.00 2.26

1.72 2.04

1.40 1.53

1.33 1.44

3.89 4.45

2.70 3.06

2.51 2.88

2.16 2.49

1.98 2.23

1.81 2.02

3.69 4.18

2.21 2.44

1.74 2.09

1.46 1.61

1.34 1.45

1.31 1.41

3.80 4.48

2.94 3.43

2.33 2.72

2.18 2.51

3.15 3.62

2.18 2.44

1.51 1.70

1.62

1.65

1.64

1.65

1.63

1.65

4.84

3.51

2.90

2.74

2.50

2.33

4.49

2.97

2.48

2.24

1.97

1.90

4.42

3.29

3.11

2.75

2.57

2.39

4.19

2.78

2.34

2.04

1.92

1.89

4.43

3.55

2.93

2.78

3.75

2.76

2.09

1.61 1.84 1.97

1.68 1.91 2.06

1.62 1.85 1.98

1.67 1.91 2.06

1.61 1.85 1.98

1.67 1.91 2.06

4.59 5.04 5.67

3.31 3.73 4.26

2.77 3.14 3.54

2.61 2.97 3.35

2.34 2.67 2.99

2.20 2.51 2.79

4.14 4.63 5.30

2.87 3.25 3.69

2.43 2.76 3.08

2.10 2.47 2.86

1.89 2.16 2.35

1.83 2.08 2.26

4.19 4.65 5.27

3.08 3.45 3.89

2.88 3.26 3.71

2.55 2.91 3.31

2.41 2.73 3.05

2.26 2.56 2.84

4.02 4.44 5.00

2.68 2.97 3.26

2.10 2.50 2.91

1.95 2.22 2.43

1.84 2.10 2.27

1.82 2.07 2.23

4.02 4.55 5.30

3.26 3.70 4.25

2.69 3.08 3.54

2.58 2.94 3.33

3.48 3.90 4.44

2.61 2.93 3.26

1.96 2.26 2.52

2.48

2.51

2.50

2.51

2.50

2.51

5.70

4.37

3.76

3.60

3.36

3.19

5.35

3.83

3.34

3.10

2.83

2.76

5.28

4.15

3.97

3.61

3.43

3.25

5.05

3.64

3.20

2.90

2.78

2.75

5.29

4.41

3.79

3.64

4.62

3.62

2.95

ns

LVCMOS18_F4

LVCMOS18_F6

LVCMOS18_F8

LVCMOS18_F12

LVCMOS18_F16

LVCMOS15_S2

LVCMOS15_S4

LVCMOS15_S6

LVCMOS15_S8

LVCMOS15_S12

LVCMOS15_S16

LVCMOS15_F2

LVCMOS15_F4

LVCMOS15_F6

LVCMOS15_F8

LVCMOS15_F12

LVCMOS15_F16

LVCMOS12_S2

LVCMOS12_S4

LVCMOS12_S6

LVCMOS12_S8

LVCMOS12_F2

LVCMOS12_F4

LVCMOS12_F6

DS182 (v1.9) October 10, 2012

www.xilinx.com

Preliminary Product Specification

19

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.67

0.50

0.62

0.50

0.62

0.72

0.79

0.72

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

LVCMOS12_F8

0.64

0.47

0.59

0.47

0.59

0.68

0.69

0.75

0.68

0.69

0.78 0.96

0.60 0.88

0.73 0.88

0.60 0.88

0.73 0.88

1.27

1.99

1.98

1.99

1.98

1.99

1.98

1.02

1.17

0.92

0.88

0.92

0.94

0.97

0.96

1.03

1.02

1.17

0.92

0.88

0.92

0.94

0.97

0.96

1.03

1.42 1.55

2.15 2.35

2.23 2.58

2.15 2.34

2.23 2.58

2.15 2.35

2.23 2.58

1.15 1.24

1.29 1.37

1.06 1.17

0.98 1.08

1.06 1.17

1.06 1.15

1.10 1.19

1.09 1.19

1.09 1.18

1.17 1.27

1.15 1.24

1.29 1.37

1.06 1.17

0.98 1.08

2.00

2.86

2.95

2.86

2.96

2.86

2.95

1.79

1.84

1.73

1.71

1.73

1.69

1.74

1.73

1.79

1.84

1.73

1.71

1.73

1.69

1.74

1.73

1.91 2.18 2.37

2.62 2.91 3.17

2.62 2.99 3.40

2.62 2.90 3.17

2.62 2.99 3.40

2.62 2.91 3.17

2.62 2.99 3.40

1.66 1.90 2.07

1.81 2.05 2.19

1.56 1.82 1.99

1.51 1.74 1.90

1.56 1.82 1.99

1.58 1.82 1.97

1.57 1.82 1.97

1.60 1.85 2.01

1.60 1.84 2.00

1.66 1.92 2.09

1.66 1.90 2.07

1.81 2.05 2.19

1.56 1.82 1.99

1.51 1.74 1.90

1.56 1.82 1.99

1.58 1.82 1.97

1.57 1.82 1.97

1.60 1.85 2.01

1.60 1.84 2.00

1.66 1.92 2.09

2.86

3.72

3.81

3.72

3.82

3.72

3.81

2.65

2.70

2.59

2.57

2.59

2.55

2.60

2.59

2.65

2.70

2.59

2.57

2.59

2.55

2.60

2.59

ns

LVDCI_18

LVDCI_15

LVDCI_DV2_18

LVDCI_DV2_15

HSLVDCI_18

0.82

0.90

HSLVDCI_15

SSTL18_I_S

0.82 0.90

0.82 0.91

0.92 0.89

0.82 0.90

0.82 0.91

SSTL18_II_S

SSTL18_I_DCI_S

SSTL18_II_DCI_S

SSTL18_II_T_DCI_S

SSTL15_S

SSTL15_DCI_S

SSTL15_T_DCI_S

SSTL135_S

SSTL135_DCI_S

SSTL135_T_DCI_S

SSTL12_S

SSTL12_DCI_S

SSTL12_T_DCI_S

DIFF_SSTL18_I_S

DIFF_SSTL18_II_S

DIFF_SSTL18_I_DCI_S

DIFF_SSTL18_II_DCI_S

DIFF_SSTL18_II_T_DCI_S

DIFF_SSTL15_S

DIFF_SSTL15_DCI_S

DIFF_SSTL15_T_DCI_S

DIFF_SSTL135_S

DIFF_SSTL135_DCI_S

DIFF_SSTL135_T_DCI_S

DIFF_SSTL12_S

DIFF_SSTL12_DCI_S

DIFF_SSTL12_T_DCI_S

1.06

1.17

1.06 1.15

1.10 1.19

1.09 1.19

1.09 1.18

1.17 1.27

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

20

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

1.0V

T_IOOP

Speed Grade

1.0V

T_IOTP

Speed Grade

1.0V

I/O Standard

Units

0.9V

-2L

0.9V

-2L

0.9V

-2L

-3

-2/-2L

0.72

0.79

0.72

-1

-3

-2/-2L

-1

-3

-2/-2L

-1

SSTL18_I_F

0.68

0.69

0.75

0.68

0.69

0.82 0.90

0.82 0.91

0.92 0.89

0.82 0.90

0.82 0.91

0.94

0.97

0.89

0.88

0.89

0.88

0.91

0.94

0.97

0.89

0.88

0.89

0.88

0.91

1.06 1.15

1.09 1.16

1.02 1.10

1.01 1.09

1.00 1.08

1.03 1.11

1.06 1.15

1.09 1.16

1.02 1.10

1.69

1.65

1.74

1.67

1.74

1.64

1.65

1.64

1.63

1.69

1.65

1.74

1.67

1.74

1.64

1.65

1.64

1.63

1.69

1.58 1.82 1.97

1.61 1.84 1.99

1.53 1.77 1.92

1.53 1.77 1.91

1.52 1.76 1.90

1.54 1.79 1.93

1.58 1.82 1.97

1.61 1.84 1.99

1.53 1.77 1.92

1.53 1.77 1.91

1.52 1.76 1.90

1.54 1.79 1.93

2.55

2.51

2.60

2.53

2.60

2.50

2.51

2.50

2.55

2.51

2.60

2.53

2.60

2.50

2.51

2.50

2.55

ns

SSTL18_II_F

SSTL18_I_DCI_F

SSTL18_II_DCI_F

SSTL18_II_T_DCI_F

SSTL15_F

SSTL15_DCI_F

SSTL15_T_DCI_F

SSTL135_F

SSTL135_DCI_F

SSTL135_T_DCI_F

SSTL12_F

SSTL12_DCI_F

SSTL12_T_DCI_F

DIFF_SSTL18_I_F

DIFF_SSTL18_II_F

DIFF_SSTL18_I_DCI_F

DIFF_SSTL18_II_DCI_F

DIFF_SSTL18_II_T_DCI_F

DIFF_SSTL15_F

1.02

1.10

1.01 1.09

1.00 1.08

1.03 1.11

DIFF_SSTL15_DCI_F

DIFF_SSTL15_T_DCI_F

DIFF_SSTL135_F

DIFF_SSTL135_DCI_F

DIFF_SSTL135_T_DCI_F

DIFF_SSTL12_F

DIFF_SSTL12_DCI_F

DIFF_SSTL12_T_DCI_F

Notes:

1. This I/O standard is only available in the 1.8V high-performance (HP) banks.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

21

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 21 specifies the values of T

and T

. T

is described as the delay from the T pin to the IOB pad

IOTPHZ

IOIBUFDISABLE IOTPHZ

through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T

is described

IOIBUFDISABLE

as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster

than T when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is

IOTPHZ

always faster than T

when the INTERMDISABLE pin is used.

IOTPHZ

Table 21: IOB 3-state Output Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

0.86

-1

T_IOTPHZ

T input to pad high-impedance

0.76

1.72

0.99

2.14

1.24

2.17

ns

T_{IOIBUFDISABLE_HR}IBUF turn-on time from IBUFDISABLE to O output for HR

I/O banks

1.89

T_{IOIBUFDISABLE_HP}IBUF turn-on time from IBUFDISABLE to O output for HP

I/O banks

1.31

1.46

1.76

1.86

ns

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Preliminary Product Specification

22

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input/Output Logic Switching Characteristics

Table 22: ILOGIC Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Setup/Hold

T_ICE1CK/T_ICKCE1

T_ISRCK/T_ICKSR

CE1 pin Setup/Hold with respect to CLK

SR pin Setup/Hold with respect to CLK

0.42/0.00 0.48/0.00 0.67/0.00 0.48/0.00

0.53/0.01 0.61/0.01 0.99/0.01 0.88/0.01

0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.41

ns

T

_IDOCKE2/T_IOCKDE2

D pin Setup/Hold with respect to CLK without Delay

(HP I/O banks only)

T

_IDOCKDE2/T_IOCKDDE2DDLY pin Setup/Hold with respect to CLK (using IDELAY) 0.01/0.27 0.02/0.29 0.02/0.34 0.01/0.41

(HP I/O banks only)

ns

T_IDOCKE3/T_IOCKDE3

D pin Setup/Hold with respect to CLK without Delay

(HR I/O banks only)

0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.41

T_IDOCKDE3/T_IOCKDDE3DDLY pin Setup/Hold with respect to CLK (using IDELAY) 0.01/0.27 0.02/0.29 0.02/0.34 0.01/0.41

(HR I/O banks only)

Combinatorial

T_IDIE2

D pin to O pin propagation delay, no Delay

(HP I/O banks only)

0.09

0.10

0.09

0.10

0.11

0.10

0.11

0.12

0.13

0.12

0.13

0.14

0.15

0.14

0.15

ns

T_IDIDE2

T_IDIE3

DDLY pin to O pin propagation delay (using IDELAY)

(HP I/O banks only)

D pin to O pin propagation delay, no Delay

(HR I/O banks only)

T_IDIDE3

DDLY pin to O pin propagation delay (using IDELAY)

(HR I/O banks only)

Sequential Delays

T_IDLOE2

D pin to Q1 pin using flip-flop as a latch without Delay

(HP I/O banks only)

0.36

0.39

0.45

0.54

0.55

0.54

0.55

ns

T_IDLODE2

T_IDLOE3

DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)

(HP I/O banks only)

D pin to Q1 pin using flip-flop as a latch without Delay

(HR I/O banks only)

T_IDLODE3

DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)

(HR I/O banks only)

T_ICKQ

CLK to Q outputs

0.47

0.84

7.60

0.84

7.60

0.50

0.94

7.60

0.94

7.60

0.58

1.16

0.71

1.32

ns

T_{RQ_ILOGICE2}

T_{GSRQ_ILOGICE2}

T_{RQ_ILOGICE3}

T_{GSRQ_ILOGICE3}

Set/Reset

SR pin to OQ/TQ out (HP I/O banks only)

Global Set/Reset to Q outputs (HP I/O banks only)

SR pin to OQ/TQ out (HR I/O banks only)

Global Set/Reset to Q outputs (HR I/O banks only)

10.51

1.16

11.39

1.32

10.51

11.39

T_{RPW_ILOGICE2}

T_{RPW_ILOGICE3}

Minimum Pulse Width, SR inputs (HP I/O banks only)

Minimum Pulse Width, SR inputs (HR I/O banks only)

0.54

0.63

0.68

ns, Min

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

23

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade

Table 23: OLOGIC Switching Characteristics

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Setup/Hold

T_ODCK/T_OCKD

D1/D2 pins Setup/Hold with respect to CLK

OCE pin Setup/Hold with respect to CLK

SR pin Setup/Hold with respect to CLK

T1/T2 pins Setup/Hold with respect to CLK

TCE pin Setup/Hold with respect to CLK

0.59/–0.13 0.62/–0.13 0.74/–0.13 0.62/–0.13

0.28/0.03 0.29/0.03 0.45/0.03 0.29/0.03

0.32/0.18 0.38/0.18 0.70/0.18 0.62/0.18

0.60/–0.16 0.64/–0.16 0.78/–0.16 0.64/–0.16

0.28/0.01 0.30/0.01 0.45/0.01 0.30/0.01

ns

T_OOCECK/T_OCKOCE

T_OSRCK/T_OCKSR

_OTCK/T_OCKT

T

T_OTCECK/T_OCKTCE

Combinatorial

T_ODQ

D1 to OQ out or T1 to TQ out

0.73

0.81

0.97

1.23

ns

Sequential Delays

T_OCKQ

CLK to OQ/TQ out

0.41

0.63

7.60

0.63

7.60

0.43

0.70

7.60

0.70

7.60

0.49

0.83

0.63

1.12

ns

T_{RQ_OLOGICE2}

T_{GSRQ_OLOGICE2}

T_{RQ_OLOGICE3}

T_{GSRQ_OLOGICE3}

Set/Reset

SR pin to OQ/TQ out (HP I/O banks only)

Global Set/Reset to Q outputs (HP I/O banks only)

SR pin to OQ/TQ out (HR I/O banks only)

Global Set/Reset to Q outputs (HR I/O banks only)

10.51

0.83

11.39

1.12

10.51

11.39

T_{RPW_OLOGICE2}

T_{RPW_OLOGICE3}

Minimum Pulse Width, SR inputs (HP I/O banks only)

Minimum Pulse Width, SR inputs (HR I/O banks only)

0.54

0.63

0.68

ns, Min

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

24

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input Serializer/Deserializer Switching Characteristics

Table 24: ISERDES Switching Characteristics

Speed Grade

1.0V

-2/-2L

Symbol

Description

0.9V

-2L

Units

-3

-1

Setup/Hold for Control Lines

T_{ISCCK_BITSLIP}

/

BITSLIP pin Setup/Hold with respect to CLKDIV

0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.21

0.39/–0.02 0.44/–0.02 0.63/–0.02 0.44/–0.02

ns

T_{ISCKC_BITSLIP}

T_{ISCCK_CE}

/

CE pin Setup/Hold with respect to CLK (for CE1)

(2)

T_{ISCKC_CE}

T_{ISCCK_CE2}

/

CE pin Setup/Hold with respect to CLKDIV (for CE2) –0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.40

(2)

T_{ISCKC_CE2}

Setup/Hold for Data Lines

T_{ISDCK_D}/T_{ISCKD_D}D pin Setup/Hold with respect to CLK

T_{ISDCK_DDLY}

–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.19

ns

/

DDLY pin Setup/Hold with respect to CLK (using

IDELAY)⁽¹⁾

T_{ISCKD_DDLY}

T_{ISDCK_D_DDR}

/

D pin Setup/Hold with respect to CLK at DDR mode –0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.19

ns

T_{ISCKD_D_DDR}

T_{ISDCK_DDLY_DDR}

T_{ISCKD_DDLY_DDR}

/

D pin Setup/Hold with respect to CLK at DDR mode 0.11/0.11 0.12/0.12 0.15/0.15 0.19/0.19

(using IDELAY)⁽¹⁾

Sequential Delays

T_{ISCKO_Q}

CLKDIV to out at Q pin

D input to DO output pin

0.46

0.09

0.47

0.10

0.58

0.12

0.67

0.14

ns

Propagation Delays

T_{ISDO_DO}

Notes:

1. Recorded at 0 tap value.

2. and T

T

are reported as T

/T

in TRACE report.

ISCCK_CE2

ISCKC_CE2

ISCCK_CE ISCKC_CE

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25

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Output Serializer/Deserializer Switching Characteristics

Table 25: OSERDES Switching Characteristics

Speed Grade

1.0V

-2/-2L

Symbol

Description

0.9V

-2L

Units

-3

-1

Setup/Hold

T_{OSDCK_D}/T_{OSCKD_D}

D input Setup/Hold with respect to CLKDIV

T input Setup/Hold with respect to CLK

T input Setup/Hold with respect to CLKDIV

OCE input Setup/Hold with respect to CLK

SR (Reset) input Setup with respect to CLKDIV

TCE input Setup/Hold with respect to CLK

0.37/0.02 0.40/0.02 0.55/0.02 0.44/0.02

0.60/–0.15 0.64/–0.15 0.77/–0.15 0.64/–0.15

0.27/–0.15 0.30/–0.15 0.34/–0.15 0.46/–0.15

0.28/0.03 0.29/0.03 0.45/0.03 0.29/0.03

ns

(1)

T_{OSDCK_T}/T_{OSCKD_T}

(1)

T

_{OSDCK_T2}/T_{OSCKD_T2}

T_{OSCCK_OCE}/T_{OSCKC_OCE}

T_{OSCCK_S}

_{OSCCK_TCE}/T_{OSCKC_TCE}

0.41

0.46

0.75

0.70

T

0.28/0.01 0.30/0.01 0.45/0.01 0.30/0.01

Sequential Delays

T_{OSCKO_OQ}

Clock to out from CLK to OQ

Clock to out from CLK to TQ

0.35

0.41

0.37

0.43

0.42

0.49

0.54

0.63

ns

T_{OSCKO_TQ}

Combinatorial

T_{OSDO_TTQ}

T input to TQ Out

0.73

0.81

0.97

1.18

ns

Notes:

1.

T

and T

are reported as T

/T

in TRACE report.

OSDCK_T2

OSCKD_T2

OSDCK_T OSCKD_T

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26

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Input/Output Delay Switching Characteristics

Table 26: Input/Output Delay Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

IDELAYCTRL

T_{DLYCCO_RDY}

Reset to Ready for IDELAYCTRL

Attribute REFCLK frequency = 200.0⁽¹⁾

Attribute REFCLK frequency = 300.0⁽¹⁾

REFCLK precision

3.22

200

3.22

200

3.22

200

N/A

3.22

200

N/A

10

µs

F_{IDELAYCTRL_REF}

MHz

ns

300

IDELAYCTRL_REF_PRECISION

T_{IDELAYCTRL_RPW}

10

Minimum Reset pulse width

52.00

IDELAY/ODELAY

T_{IDELAYRESOLUTION}

IDELAY/ODELAY chain delay resolution

1/(32 x 2 x F_REF

)

ps

Pattern dependent period jitter in delay

chain for clock pattern.⁽²⁾

0

5

0

5

ps

per tap

Pattern dependent period jitter in delay

chain for random data pattern

(PRBS 23)⁽³⁾

5

ps

per tap

T

_{IDELAYPAT_JIT}and

T_{ODELAYPAT_JIT}

Pattern dependent period jitter in delay

chain for random data pattern

(PRBS 23)⁽⁴⁾

9

ps

per tap

T_{IDELAY_CLK_MAX}

T_{ODELAY_CLK_MAX}

/

Maximum frequency of CLK input to

IDELAY/ODELAY

800

710

MHz

ns

T_{IDCCK_CE}/ T_{IDCKC_CE}

CE pin Setup/Hold with respect to C for 0.11/0.10 0.14/0.12 0.18/0.14 0.14/0.16

IDELAY

T

_{ODCCK_CE}/ T_{ODCKC_CE}

T_{IDCCK_INC}/ T_{IDCKC_INC}

T_{ODCCK_INC}/ T_{ODCKC_INC}

_{IDCCK_RST}/ T_{IDCKC_RST}

CE pin Setup/Hold with respect to C for 0.14/0.03 0.16/0.04 0.19/0.05 0.28/0.06

ODELAY

ns

INC pin Setup/Hold with respect to C for 0.10/0.14 0.12/0.16 0.14/0.20 0.12/0.23

IDELAY

ns

INC pin Setup/Hold with respect to C for 0.10/0.07 0.12/0.08 0.13/0.09 0.19/0.16

ODELAY

ns

T

RST pin Setup/Hold with respect to C for 0.13/0.08 0.14/0.10 0.16/0.12 0.22/0.19

IDELAY

ns

T_{ODCCK_RST}/ T_{ODCKC_RST}

RST pin Setup/Hold with respect to C for 0.16/0.04 0.19/0.06 0.24/0.08 0.32/0.11

ODELAY

ns

T_{IDDO_IDATAIN}

Propagation delay through IDELAY

Propagation delay through ODELAY

Note 5

ps

T_{ODDO_ODATAIN}

Notes:

1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.

3. When HIGH_PERFORMANCE mode is set to TRUE.

4. When HIGH_PERFORMANCE mode is set to FALSE.

5. Delay depends on IDELAY/ODELAY tap setting. See TRACE report for actual values.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

27

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade

Table 27: IO_FIFO Switching Characteristics

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

IO_FIFO Clock to Out Delays

T_{OFFCKO_DO}

RDCLK to Q outputs

0.51

0.59

0.56

0.62

0.63

0.81

ns

T_{CKO_FLAGS}

Clock to IO_FIFO Flags

Setup/Hold

T

_{CCK_D}/T_{CKC_D}

D inputs to WRCLK

0.43/–0.01 0.47/–0.01 0.53/–0.01 0.76/–0.01

0.39/–0.01 0.43/–0.01 0.50/–0.01 0.70/–0.01

0.49/0.01 0.53/0.02 0.61/0.02 0.79/0.02

ns

T_{IFFCCK_WREN}/T_{IFFCKC_WREN}WREN to WRCLK

_{OFFCCK_RDEN}/T_{OFFCKC_RDEN}RDEN to RDCLK

T

Minimum Pulse Width

T_{PWH_IO_FIFO}

RESET, RDCLK, WRCLK

0.81

0.92

1.08

1.29

ns

T_{PWL_IO_FIFO}

Maximum Frequency

F_MAX

RDCLK and WRCLK

533

470

400

333

MHz

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

28

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

CLB Switching Characteristics

Table 28: CLB Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Combinatorial Delays

T_ILO

An – Dn LUT address to A

An – Dn LUT address to AMUX/CMUX

An – Dn LUT address to BMUX_A

An – Dn inputs to A – D Q outputs

AX inputs to AMUX output

AX inputs to BMUX output

AX inputs to CMUX output

AX inputs to DMUX output

BX inputs to BMUX output

BX inputs to DMUX output

CX inputs to CMUX output

CX inputs to DMUX output

DX inputs to DMUX output

0.05

0.15

0.24

0.58

0.38

0.40

0.39

0.43

0.31

0.38

0.27

0.33

0.32

0.05

0.16

0.25

0.61

0.40

0.42

0.41

0.44

0.33

0.39

0.28

0.34

0.33

0.06

0.19

0.30

0.74

0.49

0.52

0.50

0.52

0.40

0.47

0.34

0.41

0.40

0.07

0.22

0.37

0.91

0.62

0.66

0.62

0.67

0.51

0.62

0.43

0.54

0.52

ns, Max

T_{ILO_2}

T_{ILO_3}

T_ITO

T_AXA

T_AXB

T_AXC

T_AXD

T_BXB

T_BXD

T_CXC

T_CXD

T_DXD

Sequential Delays

T_CKO

Clock to AQ – DQ outputs

0.26

0.32

0.27

0.32

0.39

0.40

0.46

ns, Max

T_SHCKO

Clock to AMUX – DMUX outputs

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

T

_AS/T_AH

A_N– D_Ninput to CLK on A – D Flip Flops

A_X– D_Xinput to CLK on A – D Flip Flops

0.01/0.12 0.02/0.13 0.03/0.18 0.02/0.18

0.04/0.14 0.04/0.14 0.05/0.20 0.05/0.21

0.36/0.10 0.37/0.11 0.46/0.16 0.56/0.15

ns, Min

T

_DICK/T_CKDI

A_X– D_Xinput through MUXs and/or carry logic to

CLK on A – D Flip Flops

T_{CECK_CLB}

/

CE input to CLK on A – D Flip Flops

0.19/0.05 0.20/0.05 0.25/0.05 0.24/0.05

0.30/0.05 0.31/0.07 0.37/0.09 0.48/0.07

ns, Min

T_{CKCE_CLB}

T_SRCK/T_CKSR

Set/Reset

T_SRMIN

T_RQ

SR input to CLK on A – D Flip Flops

SR input minimum pulse width

0.52

0.38

0.34

1818

0.78

0.38

0.35

1818

1.04

0.46

0.43

1818

0.95

0.59

0.54

1286

ns, Min

ns, Max

MHz

Delay from SR input to AQ – DQ flip-flops

Delay from CE input to AQ – DQ flip-flops

Toggle frequency (for export control)

T_CEO

F_TOG

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

29

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 29: CLB Distributed RAM Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Sequential Delays

T_SHCKO

Clock to A – B outputs

Clock to AMUX – BMUX outputs

0.68

0.91

0.70

0.95

0.85

1.15

1.08

1.44

ns, Max

T_{SHCKO_1}

Setup and Hold Times Before/After Clock CLK

_{DS_LRAM}/T_{DH_LRAM}A – D inputs to CLK

T

0.45/0.23 0.45/0.24 0.54/0.27 0.69/0.33

0.13/0.50 0.14/0.50 0.17/0.58 0.21/0.63

0.40/0.16 0.42/0.17 0.52/0.23 0.63/0.23

ns, Min

T_{AS_LRAM}/T_{AH_LRAM}

Address An inputs to clock

Address An inputs through MUXs and/or carry

logic to clock

T_{WS_LRAM}/T_{WH_LRAM}WE input to clock

0.29/0.09 0.30/0.09 0.36/0.09 0.46/0.10

0.29/0.09 0.30/0.09 0.37/0.09 0.47/0.10

ns, Min

T_{CECK_LRAM}

/

CE input to CLK

T_{CKCE_LRAM}

Clock CLK

T_MPW

Minimum pulse width

Minimum clock period

0.68

1.35

0.77

1.54

0.91

1.82

0.82

1.64

ns, Min

T_MCP

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time.

2. also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.

T

SHCKO

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 30: CLB Shift Register Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Sequential Delays

T_REG

Clock to A – D outputs

0.96

1.19

0.89

0.98

1.23

0.91

1.20

1.50

1.10

1.35

1.72

1.20

ns, Max

T_{REG_MUX}

T_{REG_M31}

Clock to AMUX – DMUX output

Clock to DMUX output via M31 output

Setup and Hold Times Before/After Clock CLK

T_{WS_SHFREG}

/

WE input

0.26/0.09 0.27/0.09 0.33/0.09 0.41/0.10

0.27/0.09 0.28/0.09 0.33/0.09 0.42/0.10

0.28/0.26 0.28/0.26 0.33/0.30 0.41/0.36

ns, Min

T_{WH_SHFREG}

T_{CECK_SHFREG}

T_{CKCE_SHFREG}

/

CE input to CLK

A – D inputs to CLK

T_{DS_SHFREG}

/

T_{DH_SHFREG}

Clock CLK

T_{MPW_SHFREG}

Minimum pulse width

0.55

0.65

0.78

0.70

ns, Min

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

30

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Block RAM and FIFO Switching Characteristics

Table 31: Block RAM and FIFO Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Block RAM and FIFO Clock-to-Out Delays

T_{RCKO_DO}and

T_{RCKO_DO_REG}

Clock CLK to DOUT output (without output

register)⁽²⁾⁽³⁾

1.78

0.54

2.35

0.62

2.21

0.98

1.80

0.63

2.58

0.69

2.45

1.08

2.08

0.75

3.26

0.80

2.80

1.24

2.75

0.86

4.49

0.94

3.19

1.32

ns, Max

(1)

Clock CLK to DOUT output (with output

register)⁽⁴⁾⁽⁵⁾

T

_{RCKO_DO_ECC}and

Clock CLK to DOUT output with ECC

(without output register)⁽²⁾⁽³⁾

T_{RCKO_DO_ECC_REG}

Clock CLK to DOUT output with ECC (with

output register)⁽⁴⁾⁽⁵⁾

T_{RCKO_DO_CASCOUT}and

T_{RCKO_DO_CASCOUT_REG}

Clock CLK to DOUT output with Cascade

(without output register)⁽²⁾

Clock CLK to DOUT output with Cascade

(with output register)⁽⁴⁾

T_{RCKO_FLAGS}

Clock CLK to FIFO flags outputs⁽⁶⁾

Clock CLK to FIFO pointers outputs⁽⁷⁾

0.65

0.79

0.66

0.74

0.87

0.72

0.89

0.98

0.80

0.87

1.10

0.93

ns, Max

T_{RCKO_POINTERS}

T_{RCKO_PARITY_ECC}

Clock CLK to ECCPARITY in ECC encode

only mode

T

_{RCKO_SDBIT_ECC}and

Clock CLK to BITERR (without output

register)

2.17

0.57

0.64

0.71

2.38

0.65

0.74

0.79

3.01

0.76

0.90

0.92

4.15

0.89

0.98

1.10

ns, Max

T_{RCKO_SDBIT_ECC_REG}

Clock CLK to BITERR (with output

register)

T_{RCKO_RDADDR_ECC}and

T_{RCKO_RDADDR_ECC_REG}

Clock CLK to RDADDR output with ECC

(without output register)

Clock CLK to RDADDR output with ECC

(with output register)

Setup and Hold Times Before/After Clock CLK

T_{RCCK_ADDRA}/T_{RCKC_ADDRA}

ADDR inputs⁽⁸⁾

0.38/0.27 0.42/0.28 0.48/0.31 0.65/0.31 ns, Min

0.49/0.51 0.55/0.53 0.63/0.57 0.78/0.56 ns, Min

T_{RDCK_DI_WF_NC}

/

Data input setup/hold time when block

RAM is configured in WRITE_FIRST or

NO_CHANGE mode⁽⁹⁾

T_{RCKD_DI_WF_NC}

T_{RDCK_DI_RF}/T_{RCKD_DI_RF}

Data input setup/hold time when block

RAM is configured in READ_FIRST

mode⁽⁹⁾

0.17/0.25 0.19/0.29 0.21/0.35 0.25/0.32 ns, Min

T_{RDCK_DI_ECC}

T_{RCKD_DI_ECC}

/

DIN inputs with block RAM ECC in

standard mode⁽⁹⁾

0.42/0.37 0.47/0.39 0.53/0.43 0.66/0.46 ns, Min

0.79/0.37 0.87/0.39 0.99/0.43 1.17/0.41 ns, Min

0.89/0.47 0.98/0.50 1.12/0.54 1.32/0.65 ns, Min

T_{RDCK_DI_ECCW}

T_{RCKD_DI_ECCW}

/

DIN inputs with block RAM ECC encode

only⁽⁹⁾

T_{RDCK_DI_ECC_FIFO}

T_{RCKD_DI_ECC_FIFO}

/

DIN inputs with FIFO ECC in standard

mode⁽⁹⁾

T_{RCCK_INJECTBITERR}

/

Inject single/double bit error in ECC mode 0.49/0.30 0.55/0.31 0.63/0.34 0.78/0.41 ns, Min

T_{RCKC_INJECTBITERR}

T_{RCCK_EN}/T_{RCKC_EN}

Block RAM Enable (EN) input

CE input of output register

0.30/0.17 0.33/0.18 0.38/0.20 0.48/0.22 ns, Min

0.21/0.13 0.25/0.13 0.31/0.14 0.28/0.13 ns, Min

0.25/0.06 0.27/0.06 0.29/0.06 0.35/0.06 ns, Min

T_{RCCK_REGCE}/T_{RCKC_REGCE}

T

_{RCCK_RSTREG}/T_{RCKC_RSTREG}Synchronous RSTREG input

DS182 (v1.9) October 10, 2012

Preliminary Product Specification

www.xilinx.com

31

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 31: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade

1.0V

-2/-2L

Symbol

Description

0.9V

-2L

Units

-3

-1

T_{RCCK_RSTRAM}/T_{RCKC_RSTRAM}Synchronous RSTRAM input

0.27/0.35 0.29/0.37 0.31/0.39 0.34/0.38 ns, Min

T

_{RCCK_WEA}/T_{RCKC_WEA}

Write Enable (WE) input (Block RAM only) 0.38/0.15 0.41/0.16 0.46/0.17 0.54/0.19 ns, Min

_{RCCK_WREN}/T_{RCKC_WREN}

WREN FIFO inputs

RDEN FIFO inputs

0.39/0.25 0.39/0.30 0.40/0.37 0.65/0.32 ns, Min

0.36/0.26 0.36/0.30 0.37/0.37 0.60/0.32 ns, Min

T_{RCCK_RDEN}/T_{RCKC_RDEN}

Reset Delays

T_{RCO_FLAGS}

Reset RST to FIFO flags/pointers⁽¹⁰⁾

0.76

0.83

0.93

1.06

ns, Max

T_{RREC_RST}/T_{RREM_RST}

Maximum Frequency

F_{MAX_BRAM_WF_NC}

FIFO reset recovery and removal timing⁽¹¹⁾1.59/–0.68 1.76/–0.68 2.01/–0.68 1.97/–0.46 ns, Max

Block RAM

601

543

458

372

MHz

(Write first and No change modes)

When not in SDP RF mode

F_{MAX_BRAM_RF_PERFORMANCE}Block RAM

(Read first, Performance mode)

When in SDP RF mode but no address

overlap between port A and port B

F_{MAX_BRAM_RF_DELAYED_WRITE}Block RAM

528

477

400

317

MHz

(Read first, Delayed_write mode)

When in SDP RF mode and there is

possibility of overlap between port A and

port B addresses

F_{MAX_CAS_WF_NC}

Block RAM Cascade

(Write first, No change mode)

When cascade but not in RF mode

551

493

408

322

MHz

F_{MAX_CAS_RF_PERFORMANCE}

Block RAM Cascade

(Read first, Performance mode)

When in cascade with RF mode and no

possibility of address overlap/one port is

disabled

F_{MAX_CAS_RF_DELAYED_WRITE}When in cascade RF mode and there is a

possibility of address overlap between port

A and port B

478

427

350

267

MHz

F_{MAX_FIFO}

F_{MAX_ECC}

FIFO in all modes without ECC

601

484

543

430

458

351

372

254

MHz

Block RAM and FIFO in ECC configuration

Notes:

1. TRACE will report all of these parameters as T

.

RCKO_DO

2.

3. These parameters also apply to synchronous FIFO with DO_REG = 0.

4. includes T as well as the B port equivalent timing parameters.

5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.

T

includes T

, T

, and T

as well as the B port equivalent timing parameters.

RCKO_DOR

RCKO_DOW RCKO_DOPR

RCKO_DOPW

T

RCKO_DO

RCKO_DOP

6.

7.

T

includes the following parameters: T

, T , T , T , T , T

RCKO_FLAGS

RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.

includes both T

and T

RCKO_POINTERS

RCKO_RDCOUNT

RCKO_WRCOUNT.

8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is

possible.

9. These parameters include both A and B inputs as well as the parity inputs of A and B.

10. T

includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

RCO_FLAGS

11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the

slowest clock (WRCLK or RDCLK).

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

32

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

DSP48E1 Switching Characteristics

Table 32: DSP48E1 Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Setup and Hold Times of Data/Control Pins to the Input Register Clock

T_{DSPDCK_A_AREG}/ T_{DSPCKD_A_AREG}

T_{DSPDCK_B_BREG}/T_{DSPCKD_B_BREG}

_{DSPDCK_C_CREG}/T_{DSPCKD_C_CREG}

A input to A register CLK

B input to B register CLK

C input to C register CLK

D input to D register CLK

ACIN input to A register CLK

BCIN input to B register CLK

0.24/

0.12

0.27/

0.14

0.31/

0.16

0.38/

0.14

ns

0.28/

0.13

0.32/

0.14

0.39/

0.15

0.51/

0.16

T

0.15/

0.15

0.17/

0.17

0.20/

0.20

0.31/

0.21

T_{DSPDCK_D_DREG}/T_{DSPCKD_D_DREG}

0.21/

0.19

0.27/

0.22

0.35/

0.26

0.46/

0.20

T_{DSPDCK_ACIN_AREG}/T_{DSPCKD_ACIN_AREG}

0.21/

0.12

0.24/

0.14

0.27/

0.16

0.31/

0.12

T

_{DSPDCK_BCIN_BREG}/T_{DSPCKD_BCIN_BREG}

0.22/

0.13

0.25/

0.14

0.30/

0.15

0.34/

0.16

Setup and Hold Times of Data Pins to the Pipeline Register Clock

T_{DSPDCK_ A, B _MREG_MULT}

/

{A, B,} input to M register CLK using

multiplier

2.04/

–0.01

2.34/

–0.01

2.79/

–0.01

3.66/

–0.01

ns

{

}

T_{DSPCKD_B_MREG_MULT}

T_{DSPDCK_ A, B _ADREG}/ T_{DSPCKD_ D_ADREG}

{A, D} input to AD register CLK

1.09/

–0.02

1.25/

–0.02

1.49/

–0.02

1.94/

–0.02

{

}

Setup and Hold Times of Data/Control Pins to the Output Register Clock

{A, B,} input to P register CLK using

multiplier

3.41/

–0.24

3.90/

–0.24

4.64/

–0.24

5.89/

–0.24

ns

T

/

A, B

DSPDCK_{

DSPCKD_{

}_PREG_MULT

} _PREG_MULT

T_{DSPDCK_D_PREG_MULT}

/

D input to P register CLK using

multiplier

3.33/

–0.62

3.81/

–0.62

4.53/

–0.62

5.70/

–0.62

ns

T_{DSPCKD_D_PREG_MULT}

A or B input to P register CLK not using

multiplier

1.47/

–0.24

1.68/

–0.24

2.00/

–0.24

2.37/

–0.24

T

/

A, B

DSPDCK_{

DSPCKD_{

} _PREG

T

_{DSPDCK_C_PREG}/ T_{DSPCKD_C_PREG}

C input to P register CLK not using

multiplier

1.30/

–0.22

1.49/

–0.22

1.78/

–0.22

2.11/

–0.22

ns

T_{DSPDCK_PCIN_PREG}/ T_{DSPCKD_PCIN_PREG}

PCIN input to P register CLK

1.12/

–0.13

1.28/

–0.13

1.52/

–0.13

1.81/

–0.13

Setup and Hold Times of the CE Pins

{CEA; CEB} input to {A; B} register CLK 0.30/

0.05

0.36/

0.06

0.44/

0.09

0.37/

0.01

ns

T

/

DSPDCK_{CEA;CEB}_{AREG;BREG}

DSPCKD_{CEA;CEB}_{AREG;BREG}

T_{DSPDCK_CEC_CREG}/ T_{DSPCKD_CEC_CREG}

T_{DSPDCK_CED_DREG}/ T_{DSPCKD_CED_DREG}

_{DSPDCK_CEM_MREG}/ T_{DSPCKD_CEM_MREG}

CEC input to C register CLK

CED input to D register CLK

CEM input to M register CLK

CEP input to P register CLK

0.24/

0.08

0.29/

0.09

0.36/

0.11

0.43/

0.11

0.31/

–0.02

0.36/

–0.02

0.44/

–0.02

0.58/

0.12

T

0.26/

0.15

0.29/

0.17

0.33/

0.20

0.39/

0.25

T_{DSPDCK_CEP_PREG}/ T_{DSPCKD_CEP_PREG}

0.31/

0.01

0.36/

0.01

0.45/

0.01

0.54/

0.00

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

33

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 32: DSP48E1 Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Setup and Hold Times of the RST Pins

{RSTA, RSTB} input to {A, B} register

CLK

0.34/

0.10

0.39/

0.11

0.47/

0.13

0.53/

0.34

ns

T

/

DSPDCK_{RSTA; RSTB}_{AREG; BREG}

DSPCKD_{RSTA; RSTB}_{AREG; BREG}

T_{DSPDCK_RSTC_CREG}/ T_{DSPCKD_RSTC_CREG}RSTC input to C register CLK

T_{DSPDCK_RSTD_DREG}/ T_{DSPCKD_RSTD_DREG}RSTD input to D register CLK

T_{DSPDCK_RSTM_MREG}/ T_{DSPCKD_RSTM_MREG}RSTM input to M register CLK

0.06/

0.22

0.07/

0.24

0.08/

0.26

0.08/

0.31

0.37/

0.06

0.42/

0.06

0.50/

0.07

0.57/

0.07

0.18/

0.18

0.20/

0.21

0.23/

0.24

0.24/

0.29

T

_{DSPDCK_RSTP_PREG}/ T_{DSPCKD_RSTP_PREG}RSTP input to P register CLK

0.24/

0.01

0.26/

0.01

0.30/

0.01

0.37/

0.01

Combinatorial Delays from Input Pins to Output Pins

T_{DSPDO_A_CARRYOUT_MULT}

A input to CARRYOUT output using

multiplier

3.21

3.69

4.39

5.60

ns

T_{DSPDO_D_P_MULT}

T_{DSPDO_A_P}

D input to P output using multiplier

A input to P output not using multiplier

C input to P output

3.15

1.30

1.13

3.61

1.48

1.30

4.30

1.76

1.55

5.44

2.10

1.84

ns

T_{DSPDO_C_P}

Combinatorial Delays from Input Pins to Cascading Output Pins

T_{DSPDO_{A; B}_{ACOUT; BCOUT}}

{A, B} input to {ACOUT, BCOUT} output

0.47

3.44

0.53

3.94

0.63

4.69

0.75

5.96

ns

T_{DSPDO_{A, B}_CARRYCASCOUT_MULT}

{A, B} input to CARRYCASCOUT

output using multiplier

T_{DSPDO_D_CARRYCASCOUT_MULT}

T_{DSPDO_{A, B}_CARRYCASCOUT}

T_{DSPDO_C_CARRYCASCOUT}

D input to CARRYCASCOUT output

using multiplier

3.36

1.50

1.34

3.85

1.72

1.53

4.58

2.04

1.83

5.77

2.44

2.18

ns

{A, B} input to CARRYCASCOUT

output not using multiplier

C input to CARRYCASCOUT output

Combinatorial Delays from Cascading Input Pins to All Output Pins

T_{DSPDO_ACIN_P_MULT}ACIN input to P output using multiplier

T_{DSPDO_ACIN_P}

3.09

1.16

3.55

1.33

4.24

1.59

5.42

2.07

ns

ACIN input to P output not using

multiplier

T_{DSPDO_ACIN_ACOUT}

ACIN input to ACOUT output

0.32

3.30

0.37

3.79

0.45

4.52

0.53

5.76

ns

T_{DSPDO_ACIN_CARRYCASCOUT_MULT}

ACIN input to CARRYCASCOUT output

using multiplier

T_{DSPDO_ACIN_CARRYCASCOUT}

ACIN input to CARRYCASCOUT output

not using multiplier

1.37

1.57

1.87

2.40

ns

T_{DSPDO_PCIN_P}

PCIN input to P output

0.94

1.15

1.08

1.32

1.29

1.57

1.54

1.88

ns

T_{DSPDO_PCIN_CARRYCASCOUT}

PCIN input to CARRYCASCOUT output

Clock to Outs from Output Register Clock to Output Pins

T_{DSPCKO_P_PREG}

CLK PREG to P output

0.33

0.44

0.35

0.50

0.39

0.59

0.45

0.71

ns

T_{DSPCKO_CARRYCASCOUT_PREG}

CLK PREG to CARRYCASCOUT

output

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

34

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 32: DSP48E1 Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Clock to Outs from Pipeline Register Clock to Output Pins

T_{DSPCKO_P_MREG}

CLK MREG to P output

1.42

1.63

1.64

1.87

1.96

2.24

2.31

2.65

ns

T_{DSPCKO_CARRYCASCOUT_MREG}

CLK MREG to CARRYCASCOUT

output

T_{DSPCKO_P_ADREG_MULT}

CLK ADREG to P output using

multiplier

2.30

2.51

2.63

2.87

3.13

3.41

3.90

4.23

ns

T_{DSPCKO_CARRYCASCOUT_ADREG_MULT}

CLK ADREG to CARRYCASCOUT

output using multiplier

Clock to Outs from Input Register Clock to Output Pins

T_{DSPCKO_P_AREG_MULT}CLK AREG to P output using multiplier

T_{DSPCKO_P_BREG}

3.34

1.39

3.83

1.59

4.55

1.88

5.80

2.24

ns

CLK BREG to P output not using

multiplier

T_{DSPCKO_P_CREG}

CLK CREG to P output not using

multiplier

1.43

3.32

1.64

3.80

1.95

4.51

2.32

5.74

ns

T_{DSPCKO_P_DREG_MULT}

CLK DREG to P output using multiplier

Clock to Outs from Input Register Clock to Cascading Output Pins

T_{DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}}CLK (ACOUT, BCOUT) to {A,B} register

0.55

3.55

0.62

4.06

0.74

4.84

0.87

6.13

ns

output

T_{DSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT}CLK (AREG, BREG) to

CARRYCASCOUT output using

multiplier

T_{DSPCKO_CARRYCASCOUT_ BREG}

T_{DSPCKO_CARRYCASCOUT_ DREG_MULT}

T_{DSPCKO_CARRYCASCOUT_ CREG}

CLK BREG to CARRYCASCOUT

output not using multiplier

1.60

3.52

1.64

1.82

4.03

1.88

2.16

4.79

2.23

2.58

6.07

2.65

ns

CLK DREG to CARRYCASCOUT

output using multiplier

CLK CREG to CARRYCASCOUT

output

Maximum Frequency

F_MAX

With all registers used

741

627

412

374

650

549

360

327

547

463

303

276

429

365

248

225

MHz

F_{MAX_PATDET}

With pattern detector

F_{MAX_MULT_NOMREG}

F_{MAX_MULT_NOMREG_PATDET}

Two register multiply without MREG

with pattern detect

F_{MAX_PREADD_MULT_NOADREG}

F_{MAX_PREADD_MULT_NOADREG_PATDET}

F_{MAX_NOPIPELINEREG}

Without ADREG

468

306

408

267

342

225

263

177

MHz

Without ADREG with pattern detect

Without pipeline registers (MREG,

ADREG)

F_{MAX_NOPIPELINEREG_PATDET}

Without pipeline registers (MREG,

ADREG) with pattern detect

285

249

209

165

MHz

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

35

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Clock Buffers and Networks

Table 33: Global Clock Switching Characteristics (Including BUFGCTRL)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

(1)

T_{BCCCK_CE}/T_{BCCKC_CE}

CE pins Setup/Hold

0.12/0.30 0.14/0.38 0.26/0.38 0.27/0.38

ns

(1)

T_{BCCCK_S}/T_{BCCKC_S}

S pins Setup/Hold

(2)

T_{BCCKO_O}

BUFGCTRL delay from I0/I1 to O

0.08

0.10

0.12

0.13

Maximum Frequency

F_{MAX_BUFG}

Global clock tree (BUFG)

741

710

625

560

MHz

Notes:

1.

T

and T

must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These

BCCCK_CE

BCCKC_CE

parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are

optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between

clocks.

2.

T

(BUFG delay from I0 to O) values are the same as T

values.

BCCKO_O

BGCKO_O

Table 34: Input/Output Clock Switching Characteristics (BUFIO)

Speed Grade

1.0V

Symbol

Description

Clock to out delay from I to O

I/O clock tree (BUFIO)

0.9V

-2L

Units

ns

-3

-2/-2L

-1

T_{BIOCKO_O}

1.04

1.14

1.32

1.73

Maximum Frequency

F_{MAX_BUFIO}

800

710

MHz

Table 35: Regional Clock Buffer Switching Characteristics (BUFR)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Clock to out delay from

I to O

0.60

0.65

0.77

1.23

ns

T_{BRCKO_O}

Clock to out delay from I to O with Divide Bypass

attribute set

0.30

0.71

0.32

0.75

0.38

0.96

0.68

0.96

T_{BRCKO_O_BYP}

T_{BRDO_O}

Propagation delay from CLR to O

Maximum Frequency

(1)

F_{MAX_BUFR}

Regional clock tree (BUFR)

600

540

450

MHz

Notes:

1. The maximum input frequency to the BUFR is the BUFIO F

frequency.

MAX

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

36

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 36: Horizontal Clock Buffer Switching Characteristics (BUFH)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

T_{BHCKO_O}

BUFH delay from I to O

0.10

0.11

0.13

0.14

ns

T_{BHCCK_CE}/T_{BHCKC_CE}

Maximum Frequency

F_{MAX_BUFH}

CE pin Setup and Hold

0.20/0.16 0.23/0.20 0.38/0.21 0.32/0.20

Horizontal clock buffer (BUFH)

741

710

625

560

MHz

Table 37: Duty Cycle Distortion and Clock-Tree Skew

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

Units

-3

-2/-2L

-1

T_{DCD_CLK}

Global Clock Tree Duty Cycle

Distortion⁽¹⁾

All

0.20

0.25

ns

T_CKSKEW

Global Clock Tree Skew⁽²⁾

XC7K70T

0.29

0.42

0.59

0.45

0.60

0.12

0.02

0.40

0.53

0.74

0.57

0.74

0.12

0.02

0.40

0.57

0.79

0.59

0.79

0.12

0.02

0.48

0.70

0.95

0.72

0.95

0.12

0.03

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

All

T_{DCD_BUFIO}

T_BUFIOSKEW

I/O clock tree duty cycle distortion

I/O clock tree skew across one clock

region

All

T_{DCD_BUFR}

Regional clock tree duty cycle

distortion

All

0.15

ns

Notes:

1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to

calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.

2. The T

value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree

CKSKEW

skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer

tools to evaluate clock skew specific to your application.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

37

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

MMCM Switching Characteristics

Table 38: MMCM Specification

Speed Grade

Symbol

Description

1.0V

-2/-2L

933

0.9V

-2L

800

10

Units

-3

1066

10

-1

800

10

MMCM_F_INMAX

MMCM_F_INMIN

MMCM_F_INJITTER

MMCM_F_INDUTY

Maximum Input Clock Frequency

MHz

Minimum Input Clock Frequency

10

Maximum Input Clock Period Jitter

< 20ꢀ of clock input period or 1 ns Max

Allowable Input Duty Cycle: 10—49 MHz

Allowable Input Duty Cycle: 50—199 MHz

Allowable Input Duty Cycle: 200—399 MHz

Allowable Input Duty Cycle: 400—499 MHz

Allowable Input Duty Cycle: >500 MHz

Minimum Dynamic Phase Shift Clock Frequency

Maximum Dynamic Phase Shift Clock Frequency

Minimum MMCM VCO Frequency

25

30

25

30

25

30

25

30

ꢀ

35

ꢀ

40

ꢀ

45

ꢀ

MMCM_F_{MIN_PSCLK}

MMCM_F_{MAX_PSCLK}

MMCM_F_VCOMIN

0.01

550

600

1600

1.00

4.00

0.12

0.01

500

600

1440

1.00

4.00

0.12

0.01

450

600

1200

1.00

4.00

0.12

Note 3

0.20

100

800

4.69

0.01

450

600

1200

1.00

4.00

0.12

MHz

ns

MMCM_F_VCOMAX

MMCM_F_BANDWIDTH

Maximum MMCM VCO Frequency

Low MMCM Bandwidth at Typical⁽¹⁾

High MMCM Bandwidth at Typical⁽¹⁾

MMCM_T_{STATPHAOFFSET}Static Phase Offset of the MMCM Outputs⁽²⁾

MMCM_T_OUTJITTER

MMCM_T_OUTDUTY

MMCM_T_LOCKMAX

MMCM_F_OUTMAX

MMCM_F_OUTMIN

MMCM Output Jitter

MMCM Output Clock Duty Cycle Precision⁽⁴⁾

MMCM Maximum Lock Time

0.20

100

0.20

100

933

4.69

0.25

100

800

4.69

ns

µs

MMCM Maximum Output Frequency

MMCM Minimum Output Frequency⁽⁵⁾⁽⁶⁾

External Clock Feedback Variation

Minimum Reset Pulse Width

1066

4.69

MHz

MMCM_T_EXTFDVAR

MMCM_RST_MINPULSE

MMCM_F_PFDMAX

< 20ꢀ of clock input period or 1 ns Max

5.00

550

5.00

500

5.00

450

5.00

450

ns

Maximum Frequency at the Phase Frequency

Detector with Bandwidth Set to High or Optimized

MHz

Maximum Frequency at the Phase Frequency

Detector with Bandwidth Set to Low

300

10

300

10

300

10

300

10

MHz

MMCM_F_PFDMIN

MMCM_T_FBDELAY

Minimum Frequency at the Phase Frequency

Detector

Maximum Delay in the Feedback Path

3 ns Max or one CLKIN cycle

MMCM Switching Characteristics Setup and Hold

T_{MMCMDCK_PSEN}

/

Setup and Hold of Phase Shift Enable

1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00

ns

T_{MMCMCKD_PSEN}

T_{MMCMDCK_PSINCDEC}

T_{MMCMCKD_PSINCDEC}

/

Setup and Hold of Phase Shift

Increment/Decrement

T_{MMCMCKO_PSDONE}

Phase Shift Clock-to-Out of PSDONE

0.59

0.68

0.81

0.78

Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK

T_{MMCMDCK_DADDR}

/

DADDR Setup/Hold

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{MMCMCKD_DADDR}

T_{MMCMDCK_DI}

T_{MMCMCKD_DI}

/

DI Setup/Hold

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

38

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade

Table 38: MMCM Specification (Cont’d)

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

T_{MMCMDCK_DEN}

/

DEN Setup/Hold

DWE Setup/Hold

1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min

T_{MMCMCKD_DEN}

T_{MMCMDCK_DWE}

T_{MMCMCKD_DWE}

/

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{MMCMCKO_DRDY}

F_DCK

CLK to out of DRDY

DCLK frequency

0.65

200

0.72

200

0.99

200

0.70

100

ns, Max

MHz, Max

Notes:

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any MMCM outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50ꢀ.

VCO

6. When CLKOUT4_CASCADE = TRUE, MMCM_F

is 0.036 MHz.

OUTMIN

PLL Switching Characteristics

Table 39: PLL Specification

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

800

19

Units

-3

1066

19

-2/-2L

933

19

-1

800

19

PLL_F_INMAX

Maximum Input Clock Frequency

Minimum Input Clock Frequency

Maximum Input Clock Period Jitter

Allowable Input Duty Cycle: 19—49 MHz

Allowable Input Duty Cycle: 50—199 MHz

Allowable Input Duty Cycle: 200—399 MHz

Allowable Input Duty Cycle: 400—499 MHz

Allowable Input Duty Cycle: >500 MHz

Minimum PLL VCO Frequency

MHz

PLL_F_INMIN

PLL_F_INJITTER

PLL_F_INDUTY

< 20ꢀ of clock input period or 1 ns Max

25

30

25

30

25

30

25

30

ꢀ

35

ꢀ

40

ꢀ

45

ꢀ

PLL_F_VCOMIN

800

2133

1.00

4.00

0.12

800

1866

1.00

4.00

0.12

800

1600

1.00

4.00

0.12

Note 3

0.20

100

800

6.25

800

1600

1.00

4.00

0.12

MHz

ns

PLL_F_VCOMAX

PLL_F_BANDWIDTH

Maximum PLL VCO Frequency

Low PLL Bandwidth at Typical⁽¹⁾

High PLL Bandwidth at Typical⁽¹⁾

Static Phase Offset of the PLL Outputs⁽²⁾

PLL Output Jitter

PLL_T_{STATPHAOFFSET}

PLL_T_OUTJITTER

PLL_T_OUTDUTY

PLL_T_LOCKMAX

PLL_F_OUTMAX

PLL Output Clock Duty Cycle Precision⁽⁴⁾

PLL Maximum Lock Time

0.20

100

0.20

100

933

6.25

0.25

100

800

6.25

ns

µs

PLL Maximum Output Frequency

PLL Minimum Output Frequency⁽⁵⁾

External Clock Feedback Variation

Minimum Reset Pulse Width

1066

6.25

MHz

PLL_F_OUTMIN

PLL_T_EXTFDVAR

PLL_RST_MINPULSE

< 20ꢀ of clock input period or 1 ns Max

5.00 5.00 5.00

5.00

ns

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

39

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade

Table 39: PLL Specification (Cont’d)

Symbol

Description

1.0V

-2/-2L

500

0.9V

-2L

Units

-3

-1

PLL_F_PFDMAX

Maximum Frequency at the Phase Frequency

Detector with Bandwidth Set to High or Optimized

550

450

MHz

Maximum Frequency at the Phase Frequency

Detector with Bandwidth Set to Low

300

19

300

19

300

19

300

19

PLL_F_PFDMIN

PLL_T_FBDELAY

Minimum Frequency at the Phase Frequency

Detector

Maximum Delay in the Feedback Path

3 ns Max or one CLKIN cycle

Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK

T_{PLLCCK_DADDR}

/

Setup and hold of D address

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{PLLCKC_DADDR}

T_{PLLCCK_DI}

/

Setup and hold of D input

T_{PLLCKC_DI}

T_{PLLCCK_DEN}

/

Setup and hold of D enable

Setup and hold of D write enable

T_{PLLCKC_DEN}

T_{PLLCCK_DWE}

T_{PLLCKC_DWE}

/

T_{PLLCKO_DRDY}

F_DCK

CLK to out of DRDY

DCLK frequency

0.65

200

0.72

200

0.99

200

0.70

100

ns, Max

MHz, Max

Notes:

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any PLL outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50ꢀ.

VCO

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

40

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Device Pin-to-Pin Output Parameter Guidelines

All devices are 100ꢀ functionally tested. Values are expressed in nanoseconds unless otherwise noted.

Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

T_ICKOF

Clock-capable clock input and OUTFF

without MMCM/PLL (near clock region)

XC7K70T

4.98

5.23

5.72

5.34

5.84

5.50

5.49

5.77

6.31

5.87

6.44

6.04

6.17

6.48

7.09

6.57

7.22

6.77

7.94

8.31

9.05

8.27

9.21

8.51

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

Table 41: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

T_ICKOFFAR

Clock-capable clock input and OUTFF

without MMCM/PLL (far clock region)

XC7K70T

5.29

5.84

6.33

5.95

6.45

6.41

5.83

6.45

6.99

6.55

7.12

7.06

6.55

7.24

7.84

7.32

7.97

7.90

8.41

9.25

9.99

9.20

10.14

9.91

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

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Preliminary Product Specification

41

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 42: Clock-Capable Clock Input to Output Delay With MMCM

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

Units

-3

-2/-2L

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.

T_ICKOFMMCMCC

Clock-capable clock input and OUTFF

with MMCM

XC7K70T

0.95

0.96

1.00

1.07

0.95

0.96

1.00

1.07

0.95

0.96

1.00

1.07

2.09

2.13

1.88

2.15

1.95

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. MMCM output jitter is already included in the timing calculation.

Table 43: Clock-Capable Clock Input to Output Delay With PLL

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.

T_ICKOFPLLCC

Clock-capable clock input and OUTFF

with PLL

XC7K70T

0.84

0.89

0.96

0.84

0.89

0.96

0.84

0.89

0.96

1.69

1.76

1.74

1.49

1.76

1.55

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. PLL output jitter is already included in the timing calculation.

Table 44: Pin-to-Pin, Clock-to-Out using BUFIO

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.

T_ICKOFCS

Clock-to-Out of I/O clock for HR I/O banks

Clock-to-Out of I/O clock for HP I/O banks

4.93

4.85

5.52

5.44

6.20

6.11

7.70

7.75

ns

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

42

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Device Pin-to-Pin Input Parameter Guidelines

All devices are 100ꢀ functionally tested. Values are expressed in nanoseconds unless otherwise noted.

Table 45: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

-2/-2L

-1

T_PSFD/ T_PHFD

Full Delay (Legacy Delay or Default

Delay)

XC7K70T

2.83/–0.29 2.95/–0.29 3.15/–0.29 4.70/–0.79

3.17/–0.35 3.29/–0.35 3.55/–0.35 5.43/–0.97

2.83/–0.06 2.94/–0.06 3.15/–0.06 4.98/–0.68

3.26/–0.32 3.41/–0.32 3.67/–0.32 5.65/–1.02

3.43/–0.34 3.59/–0.34 3.88/–0.34 6.06/–1.09

3.37/–0.27 3.48/–0.27 3.76/–0.27 5.86/–1.10

ns

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Global Clock Input and IFF⁽²⁾without

MMCM/PLL with ZHOLD_DELAY on

HR I/O Banks

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global

Clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input Flip-Flop or Latch

3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time.

Table 46: Clock-Capable Clock Input Setup and Hold With MMCM

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

-2/-2L

-1

T_PSMMCMCC

/

No Delay clock-capable clock input and XC7K70T

2.39/–0.22 2.65/–0.22 2.94/–0.22 2.65/–0.62

2.49/–0.20 2.77/–0.20 3.07/–0.20 2.79/–0.58

2.55/–0.16 2.85/–0.16 3.14/–0.16 2.72/–0.58

2.43/–0.16 2.73/–0.16 3.00/–0.16 2.54/–0.69

2.55/–0.16 2.84/–0.16 3.14/–0.16 2.76/–0.56

2.47/–0.09 2.73/–0.09 3.02/–0.09 2.48/–0.75

ns

T_PHMMCMCC

IFF⁽²⁾with MMCM

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global

Clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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Preliminary Product Specification

43

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 47: Clock-Capable Clock Input Setup and Hold With PLL

Speed Grade

1.0V

-2/-2L

Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.⁽¹⁾

Symbol

Description

Device

0.9V

-2L

Units

-3

-1

T_PSPLLCC

T_PHPLLCC

/

No Delay clock-capable clock input and XC7K70T

2.75/–0.32 3.04/–0.32 3.33/–0.32 3.06/–0.71

2.85/–0.31 3.16/–0.31 3.46/–0.31 3.20/–0.78

2.91/–0.27 3.24/–0.27 3.54/–0.27 3.13/–0.78

2.79/–0.27 3.12/–0.27 3.40/–0.27 2.95/–0.78

2.91/–0.27 3.24/–0.27 3.53/–0.27 3.16/–0.77

2.83/–0.20 3.12/–0.20 3.41/–0.20 2.89/–0.84

ns

IFF⁽²⁾with PLL

XC7K160T

XC7K325T

XC7K355T

XC7K410T

XC7K420T

XC7K480T

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global

Clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Table 48: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.

T_PSCS/T_PHCS

Setup/Hold of I/O clock for HR I/O banks

Setup/Hold of I/O clock for HP I/O banks

–0.36/1.36 –0.36/1.50 –0.36/1.70 –0.46/2.01

–0.34/1.39 –0.34/1.53 –0.34/1.73 –0.47/1.99

ns

Table 49: Sample Window

Speed Grade

Symbol

Description

1.0V

-2/-2L

0.56

0.9V

-2L

Units

-3

-1

T_SAMP

Sampling Error at Receiver Pins⁽¹⁾

0.51

0.30

0.61

0.40

0.56

0.35

ns

T_{SAMP_BUFIO}

Sampling Error at Receiver Pins using BUFIO⁽²⁾

0.35

Notes:

1. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and

process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements

include:

- CLK0 MMCM jitter

- MMCM accuracy (phase offset)

- MMCM phase shift resolution

These measurements do not include package or clock tree skew.

2. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and

process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of

operation. These measurements do not include package or clock tree skew.

DS182 (v1.9) October 10, 2012

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Preliminary Product Specification

44

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Additional Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock

transmitter and receiver data-valid windows.

Table 50: Package Skew

Symbol

T_PKGSKEW

Description

Package Skew⁽¹⁾

Device

XC7K70T

Package

FBG484

FBG676

FBG484

FBG676

FFG676

FBG676

FFG676

FBG900

FFG900

FFG901

Value

Units

ps

118

136

161

146

154

163

161

ps

XC7K160T

XC7K325T

ps

XC7K355T

XC7K410T

FBG676

FFG676

FBG900

FFG900

FFG901

FFG1156

FFG901

FFG1156

165

168

151

146

149

145

149

145

ps

XC7K420T

XC7K480T

Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time

from Pad to Ball (7.0 ps per mm).

2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.

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Preliminary Product Specification

45

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

GTX Transceiver Specifications

GTX Transceiver DC Input and Output Levels

Table 51 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult UG476: 7 Series

FPGAs GTX/GTH Transceiver User Guide for further details.

Table 51: GTX Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

Differential peak-to-peak output Transmitter output swing is set to

–

1000

mV

DV_PPOUT

voltage⁽¹⁾

maximum setting

DC common mode output

voltage.

Equation based

V_MGTAVTT– DV_PPOUT/4

100

mV

V_CMOUTDC

R_OUT

Differential output resistance

–

Ω

T_OSKEW

Transmitter output pair (TXP and TXN) intra-pair skew

Differential peak-to-peak input >10.3125 Gb/s

2

12

1250

2000

V_MGTAVTT

–

ps

150

–200

–

mV

Ω

voltage (external AC coupled)

DV_PPIN

6.6 Gb/s to 10.3125 Gb/s

–

≤ 6.6 Gb/s

–

V_IN

Absolute input voltage

DC coupled V_MGTAVTT= 1.2V

–

2/3 V_MGTAVTT

100

V_CMIN

R_IN

Common mode input voltage

Differential input resistance

–

C_EXT

Recommended external AC coupling capacitor⁽²⁾

–

100

–

nF

Notes:

1. The output swing and preemphasis levels are programmable using the attributes discussed in UG476: 7 Series FPGAs GTX/GTH

Transceiver User Guide and can result in values lower than reported in this table.

2. Other values can be used as appropriate to conform to specific protocols and standards.

X-Ref Target - Figure 1

+V

0

P

N

Single-Ended

Voltage

ds182_01_041712

Figure 1: Single-Ended Peak-to-Peak Voltage

X-Ref Target - Figure 2

+V

0

Differential

Voltage

P–N

–V

ds182_02_042712

Figure 2: Differential Peak-to-Peak Voltage

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Preliminary Product Specification

46

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 52 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG476: 7 Series FPGAs

GTX/GTH Transceiver User Guide for further details.

Table 52: GTX Transceiver Clock DC Input Level Specification

Symbol

V_IDIFF

DC Parameter

Differential peak-to-peak input voltage

Min

250

–

Typ

–

Max

2000

–

Units

mV

Ω

R_IN

Differential input resistance

100

C_EXT

Required external AC coupling capacitor

–

nF

GTX Transceiver Switching Characteristics

Consult UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide for further information.

Table 53: GTX Transceiver Performance

Speed Grade

1.0V

0.9V

Output

Divider

Symbol

Description

-3

-2/-2L

Package Type

-1⁽¹⁾

-2L⁽²⁾

Units

FF

FB

6.6

FF

FB

6.6

FF

FB

FF

6.6

FB

6.6

(3)

F_GTXMAX

Maximum GTX transceiver data rate

12.5

0.500

10.3125

0.500

6.6

Gb/s

(3)

F_GTXMIN

Minimum GTX transceiver data rate

0.500

0.500 Gb/s

Gb/s

1

2

3.2–6.6

1.6–3.3

0.8–1.65

0.5–0.825

N/A

Gb/s

F_GTXCRANGE

CPLL line rate range

4

8

Gb/s

16

Gb/s

5.93–

8.0

5.93–

6.6

5.93–

8.0

5.93–

6.6

5.93–6.6

Gb/s

1

2

4

2.965–4.0

1.4825–2.0

0.74125–1.0

N/A

2.965–4.0

2.965–3.3

1.4825–1.65

Gb/s

F_GTXQRANGE1QPLL line rate range 1

1.4825–2.0

0.74125–1.0

N/A

1.4825–1.65

8

0.74125–0.825 0.74125–0.825 Gb/s

16

N/A

Gb/s

9.8–

12.5

N/A

9.8–

N/A

1

10.3125

2

4

8

4.9–6.25

2.45–3.125

4.9–5.15625

N/A

Gb/s

F_GTXQRANGE2QPLL line rate range 2⁽⁴⁾

2.45–2.578125

1.225–1.5625 1.225–1.2890625

0.6125–0.78125

0.6125–

0.64453125

16

F_GCPLLRANGEGTX transceiver CPLL frequency

range

1.6–3.3

GHz

F_GQPLLRANGE1GTX transceiver QPLL frequency

range 1

5.93–8.0

5.93–6.6

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Preliminary Product Specification

47

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Speed Grade

Table 53: GTX Transceiver Performance (Cont’d)

1.0V

0.9V

Output

Divider

Symbol

Description

-3

-2/-2L

-1⁽¹⁾

-2L⁽²⁾

Units

Package Type

FB FF

9.8–10.3125

FF

FB

FF

FB

FF

FB

F_GQPLLRANGE2GTX transceiver QPLL frequency

range 2

9.8–12.5

N/A

GHz

Notes:

1. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.

2. The -2L (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8 Gb/s.

3. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.

4. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s.

Table 54: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

Units

-3

-2/-2L

-1

-2L

F_GTXDRPCLK

GTXDRPCLK maximum frequency

175

156.25

125

MHz

Table 55: GTX Transceiver Reference Clock Switching Characteristics

All Speed Grades

Symbol

Description

Conditions

Units

Min

60

–

Typ

–

Max

-3 speed grade

700

670

–

MHz

ps

F_GCLK

Reference clock frequency range

All other speed grades

20ꢀ – 80ꢀ

–

T_RCLK

T_FCLK

T_DCREF

Reference clock rise time

Reference clock fall time

Reference clock duty cycle

200

50

80ꢀ – 20ꢀ

–

ps

Transceiver PLL only

40

60

ꢀ

X-Ref Target - Figure 3

T_RCLK

80%

20%

T_FCLK

ds182_03_042712

Figure 3: Reference Clock Timing Parameters

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Preliminary Product Specification

48

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 56: GTX Transceiver PLL /Lock Time Adaptation

All Speed Grades

Symbol

Description

Conditions

Units

Min

–

Typ

Max

T_LOCK

Initial PLL lock

–

1

ms

UI

Clock recovery phase acquisition and

adaptation time for decision feedback

equalizer (DFE).

–

50,000

37 x10⁶

After the PLL is locked to the

reference clock, this is the time it

takes to lock the clock data

recovery (CDR) to the data

present at the input.

T_DLOCK

Clock recovery phase acquisition and

adaptation time for low-power mode

(LPM) when the DFE is disabled.

–

2.3 x10⁶

UI

(1)(2)

Table 57: GTX Transceiver User Clock Switching Characteristics

Speed Grade

Symbol

Description

Conditions

1.0V

0.9V

-2L⁽⁵⁾

237.5

Units

-3⁽³⁾

412.5

-2/-2L⁽³⁾

-1⁽⁴⁾

312.5

F_TXOUTTXOUTCLK maximum frequency

F_RXOUTRXOUTCLK maximum frequency

412.5

MHz

412.5

16-bit data path

32-bit data path

16-bit data path

32-bit data path

16-bit data path

32-bit data path

64-bit data path

16-bit data path

32-bit data path

64-bit data path

412.5

391

412.5

322.5

412.5

322.5

412.5

322.5

161.5

412.5

322.5

161.5

312.5

206.5

312.5

206.5

312.5

206.5

103.5

312.5

206.5

103.5

237.5

206.5

237.5

206.5

237.5

206.5

103.5

237.5

206.5

103.5

MHz

F_TXIN

TXUSRCLK maximum frequency

RXUSRCLK maximum frequency

412.5

391

F_RXIN

412.5

391

F_TXIN2

TXUSRCLK2 maximum frequency

RXUSRCLK2 maximum frequency

195.5

412.5

391

F_RXIN2

195.5

Notes:

1. Clocking must be implemented as described in UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide.

2. These frequencies are not supported for all possible transceiver configurations.

3. For speed grades -3, -2, -2L (1.0V), a 16-bit data path can only be used for speeds less than 6.6 Gb/s.

4. For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s.

5. For speed grade -2L (0.9V), a 16-bit data path can only be used for speeds less than 3.8 Gb/s.

Table 58: GTX Transceiver Transmitter Switching Characteristics

Symbol

Description

Serial data rate range

Condition

Min

Typ

–

Max

F_GTXMAX

–

Units

Gb/s

ps

F_GTXTX

T_RTX

0.500

TX Rise time

20ꢀ–80ꢀ

80ꢀ–20ꢀ

–

40

–

T_FTX

TX Fall time

–

ps

T_LLSKEW

TX lane-to-lane skew⁽¹⁾

Electrical idle amplitude

Electrical idle transition time

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽²⁾⁽⁴⁾

500

ps

V_TXOOBVDPP

T_{TXOOBTRANSITION}

TJ_12.5

–

15

mV

ns

–

140

–

0.28

0.17

0.28

0.17

UI

12.5 Gb/s

DJ_12.5

–

UI

TJ_11.18

–

UI

11.18 Gb/s

DJ_11.18

Deterministic Jitter⁽²⁾⁽⁴⁾

–

UI

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 58: GTX Transceiver Transmitter Switching Characteristics (Cont’d)

Symbol

TJ_10.3125

Description

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽²⁾⁽⁴⁾

Deterministic Jitter⁽²⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Deterministic Jitter⁽³⁾⁽⁴⁾

Total Jitter⁽³⁾⁽⁴⁾

Condition

Min

–

Typ

–

Max

0.28

0.17

0.28

0.17

0.28

0.17

0.30

0.15

0.28

0.17

0.30

0.15

0.30

0.15

0.30

0.15

0.30

0.15

0.2

Units

UI

10.3125 Gb/s

DJ_10.3125

TJ_9.953

DJ_9.953

TJ_9.8

9.953 Gb/s

9.8 Gb/s

DJ_9.8

TJ_8.0

8.0 Gb/s

DJ_8.0

TJ_{6.6_QPLL}

DJ_{6.6_QPLL}

TJ_{6.6_CPLL}

DJ_{6.6_CPLL}

TJ_5.0

6.6 Gb/s

5.0 Gb/s

DJ_5.0

TJ_4.25

DJ_4.25

TJ_3.75

DJ_3.75

TJ_3.2

4.25 Gb/s

3.75 Gb/s

3.20 Gb/s⁽⁵⁾

3.20 Gb/s⁽⁶⁾

2.5 Gb/s⁽⁷⁾

1.25 Gb/s⁽⁸⁾

500 Mb/s

DJ_3.2

0.1

TJ_3.2L

DJ_3.2L

TJ_2.5

0.32

0.16

0.20

0.08

0.15

0.06

0.1

DJ_2.5

TJ_1.25

DJ_1.25

TJ₅₀₀

DJ₅₀₀

Deterministic Jitter⁽³⁾⁽⁴⁾

0.03

Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).

2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

-12

4. All jitter values are based on a bit-error ratio of 1e

5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.

6. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1.

7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.

8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.

.

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Preliminary Product Specification

50

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 59: GTX Transceiver Receiver Switching Characteristics

Symbol Description

RX oversampler not enabled

Min

0.500

–

Typ

–

Max

Units

Gb/s

ns

F_GTXRX

T_RXELECIDLE

RX_OOBVDPP

Serial data rate

F_GTXMAX

Time for RXELECIDLE to respond to loss or restoration of data

OOB detect threshold peak-to-peak

10

–

150

0

60

mV

Receiver spread-spectrum

Modulated @ 33 KHz

tracking⁽¹⁾

–5000

–

ppm

RX_SST

RX_RL

Run length (CID)

–

512

1250

700

UI

Data/REFCLK PPM offset

tolerance

Bit rates ≤ 6.6 Gb/s

–1250

–700

ppm

Bit rates > 6.6 Gb/s and

≤ 8.0 Gb/s

RX_PPMTOL

Bit rates > 8.0 Gb/s

–200

–

200

ppm

SJ Jitter Tolerance⁽²⁾

JT_SJ_12.5

Sinusoidal Jitter (QPLL)⁽³⁾

Sinusoidal Jitter (CPLL)⁽³⁾

12.5 Gb/s

11.18 Gb/s

10.32 Gb/s

9.95 Gb/s

9.8 Gb/s

0.3

–

UI

JT_SJ_11.18

JT_SJ_10.32

JT_SJ_9.95

0.3

JT_SJ_9.8

0.3

JT_SJ_8.0

8.0 Gb/s

0.44

0.48

0.44

0.45

0.5

JT_SJ_{6.6_QPLL}

JT_SJ_{6.6_CPLL}

JT_SJ_5.0

6.6 Gb/s

5.0 Gb/s

JT_SJ_4.25

4.25 Gb/s

3.75 Gb/s

3.2 Gb/s⁽⁴⁾

3.2 Gb/s⁽⁵⁾

2.5 Gb/s⁽⁶⁾

1.25 Gb/s⁽⁷⁾

500 Mb/s

JT_SJ_3.75

JT_SJ_3.2

JT_SJ_3.2L

JT_SJ_2.5

JT_SJ_1.25

0.5

JT_SJ₅₀₀

0.4

SJ Jitter Tolerance with Stressed Eye⁽²⁾

JT_TJSE_3.2

3.2 Gb/s

6.6 Gb/s

3.2 Gb/s

6.6 Gb/s

0.70

0.1

–

UI

Total Jitter with Stressed Eye⁽⁸⁾

JT_TJSE_6.6

JT_SJSE_3.2

JT_SJSE_6.6

Sinusoidal Jitter with Stressed

Eye⁽⁸⁾

0.1

Notes:

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 1e

–12

.

3. The frequency of the injected sinusoidal jitter is 10 MHz.

4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.

5. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1.

6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.

7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.

8. Composite jitter with RX and LPM or DFE mode.

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51

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

GTX Transceiver Protocol Jitter Characteristics

For Table 60 through Table 65, the UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide contains recommended

settings for optimal usage of protocol specific characteristics.

Table 60: Gigabit Ethernet Protocol Characteristics

Description

Line Rate (Mb/s)

Min

–

Max

0.24

–

Units

UI

Gigabit Ethernet Transmitter Jitter Generation

Total transmitter jitter (T_TJ)

1250

Gigabit Ethernet Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance

1250

0.749

UI

Table 61: XAUI Protocol Characteristics

Description

Line Rate (Mb/s)

3125

Min

–

Max

0.35

–

Units

UI

XAUI Transmitter Jitter Generation

Total transmitter jitter (T_TJ)

XAUI Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance

3125

0.65

UI

(1)

Table 62: PCI Express Protocol Characteristics

Standard

Description

Line Rate (Mb/s)

Min

Max

Units

PCI Express Transmitter Jitter Generation

PCI Express Gen 1

PCI Express Gen 2

Total transmitter jitter

2500

5000

–

0.25

31.25

12

UI

ps

Total transmitter jitter uncorrelated

PCI Express Gen 3⁽²⁾

8000

Deterministic transmitter jitter uncorrelated

PCI Express Receiver High Frequency Jitter Tolerance

PCI Express Gen 1

Total receiver jitter tolerance

Receiver inherent timing error

Receiver inherent deterministic timing error

0.03 MHz–1.0 MHz

2500

5000

0.65

0.40

–

UI

PCI Express Gen 2⁽³⁾

0.30

1.00

Receiver sinusoidal jitter

1.0 MHz–10 MHz

tolerance

PCI Express Gen 3⁽²⁾

8000

Note 4

0.10

10 MHz–100 MHz

Notes:

1. Tested per card electromechanical (CEM) methodology.

2. PCI-SIG 3.0 certification and compliance test boards are currently not available.

3. Using common REFCLK.

4. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.

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Preliminary Product Specification

52

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 63: CEI-6G and CEI-11G Protocol Characteristics

Description Line Rate (Mb/s)

Interface

Min

Max

Units

CEI-6G Transmitter Jitter Generation

CEI-6G-SR

CEI-6G-LR

–

0.3

UI

Total transmitter jitter⁽¹⁾

4976–6375

CEI-6G Receiver High Frequency Jitter Tolerance

CEI-6G-SR

CEI-6G-LR

0.6

–

UI

Total receiver jitter tolerance⁽¹⁾

CEI-11G Transmitter Jitter Generation

Total transmitter jitter⁽²⁾

4976–6375

0.95

CEI-11G-SR

–

0.3

UI

9950–11100

CEI-11G-LR/MR

CEI-11G Receiver High Frequency Jitter Tolerance

CEI-11G-SR

CEI-11G-MR

CEI-11G-LR

0.65

–

UI

Total receiver jitter tolerance⁽²⁾

9950–11100

0.825

Notes:

1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.

2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.

Table 64: SFP+ Protocol Characteristics

Description

Line Rate (Mb/s)

Min

Max

Units

SFP+ Transmitter Jitter Generation

9830.40⁽¹⁾

9953.00

Total transmitter jitter

10312.50

10518.75

11100.00

–

0.28

UI

SFP+ Receiver Frequency Jitter Tolerance

Total receiver jitter tolerance

9830.40⁽¹⁾

9953.00

10312.50

10518.75

11100.00

0.7

–

UI

Notes:

1. Line rated used for CPRI over SFP+ applications.

DS182 (v1.9) October 10, 2012

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53

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 65: CPRI Protocol Characteristics

Description

Line Rate (Mb/s)

Min

Max

Units

CPRI Transmitter Jitter Generation

614.4

1228.8

2457.6

3072.0

4915.2

6144.0

9830.4

–

0.35

0.3

UI

Total transmitter jitter

0.3

Note 1

CPRI Receiver Frequency Jitter Tolerance

Total receiver jitter tolerance

614.4

1228.8

2457.6

3072.0

4915.2

6144.0

9830.4

0.65

–

UI

0.65

0.95

Note 1

Notes:

1. Tested per SFP+ specification, see Table 64.

Integrated Interface Block for PCI Express Designs Switching Characteristics

More information and documentation on solutions for PCI Express designs can be found at:

http://www.xilinx.com/technology/protocols/pciexpress.htm

Table 66: Maximum Performance for PCI Express Designs

Speed Grade

Symbol

Description

1.0V

-2/-2L

250

0.9V

-2L

Units

-3

-1

F_PIPECLK

Pipe clock maximum frequency

User clock maximum frequency

User clock 2 maximum frequency

DRP clock maximum frequency

250

500

250

MHz

F_USERCLK

F_USERCLK2

F_DRPCLK

500

250

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54

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

XADC Specifications

Table 67: XADC Specifications

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

V_CCADC= 1.8V 5ꢀ, V_REFP= 1.25V, V_REFN= 0V, ADCCLK = 26 MHz, T_j= –40°C to 100°C, Typical values at T_j=+40°C

ADC Accuracy⁽¹⁾

Resolution

12

–

Bits

LSBs

ꢀ

Integral Nonlinearity⁽²⁾

Differential Nonlinearity

Offset Error

INL

3

DNL

No missing codes, guaranteed monotonic

Offset calibration enabled

–

1

6

–

Gain Error

Gain calibration disabled

–

0.5

4

Offset Matching

Gain Matching

Offset calibration enabled

–

LSBs

ꢀ

Gain calibration disabled

–

0.3

1

Sample Rate

0.1

60

–

MS/s

dB

Signal to Noise Ratio⁽²⁾

RMS Code Noise

SNR

THD

F_SAMPLE= 500KS/s, F_IN= 20KHz

External 1.25V reference

–

2

LSBs

dB

On-chip reference

–

3

–

Total Harmonic Distortion⁽²⁾

F_SAMPLE= 500KS/s, F_IN= 20KHz

–

70

–

ADC Accuracy at Extended Temperatures (-55°C to 125°C)

Resolution

10

–

1

Bits

Integral Nonlinearity⁽²⁾

Differential Nonlinearity

Analog Inputs⁽³⁾

INL

LSB

(at 10 bits)

DNL

No missing codes, guaranteed monotonic

–

ADC Input Ranges

Unipolar operation

0

–

1

V

Bipolar operation

–0.5

0

+0.5

Unipolar common mode range (FS input)

Bipolar common mode range (FS input)

+0.5

–0.1

+0.6

Maximum External Channel Input Ranges

Adjacent channels set within these ranges

should not corrupt measurements on adjacent

channels

V_CCADC

Auxiliary Channel Full

Resolution Bandwidth

FRBW

250

–

KHz

On-Chip Sensors

Temperature Sensor Error⁽⁴⁾

T_j= –40°C to 100°C.

T_j= –55°C to +125°C

–

4

6

1

°C

ꢀ

Supply Sensor Error

Measurement range of V_CCAUX1.8V 5ꢀ

T_j= –40°C to +100°C

Measurement range of V_CCAUX1.8V 5ꢀ

T_j= –55°C to +125°C

–

2

ꢀ

Conversion Rate⁽⁵⁾

Conversion Time - Continuous t_CONV

Number of ADCCLK cycles

Number of CLK cycles

DRP clock frequency

Derived from DCLK

26

–

32

21

Cycles

MHz

ꢀ

Conversion Time - Event

DRP Clock Frequency

ADC Clock Frequency

DCLK Duty Cycle

t_CONV

DCLK

8

250

26

ADCCLK

1

40

60

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 67: XADC Specifications (Cont’d)

Parameter

XADC Reference⁽⁶⁾

External Reference

On-Chip Reference

Symbol

Comments/Conditions

Min

Typ

Max

Units

V_REFP

Externally supplied reference voltage

1.20

1.25

1.30

V

Ground V_REFPpin to AGND,

T_j= –40°C to 100°C

1.2375 1.25

1.2625

Notes:

1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature

is enabled.

2. Only specified for new BitGen option XADCEnhancedLinearity = ON.

3. See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.

4. Accuracy of temperature sensor error data is based on characterization at T = 0°C to 125°C.

j

5. See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.

6. Any variation in the reference voltage from the nominal V

= 1.25V and V

= 0V will result in a deviation from the ideal transfer

REFP

REFN

function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external

ratiometric type applications allowing reference to vary by 4ꢀ is permitted. On-chip reference variation is 1ꢀ.

Configuration Switching Characteristics

Table 68: Configuration Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Power-up Timing Characteristics

(1)

T_PL

Program latency

5

ms, Max

(1)

T_POR

Power-on reset (50 ms ramp rate time)

Power-on reset (1 ms ramp rate time)

Program pulse width

10/50

10/35

250

10/50

10/35

250

10/50

10/35

250

10/50 ms, Min/Max

10/35 ms, Min/Max

T_PROGRAM

CCLK Output (Master Mode)

250

ns, Min

T_ICCK

Master CCLK output delay

150

40/60

100

50

150

40/60

100

50

150

40/60

100

50

150

40/60

70

ns, Min

ꢀ, Min/Max

MHz, Max

MHz, Typ

ꢀ, Max

T_MCCKL

T_MCCKH

F_MCCK

Master CCLK clock Low time duty cycle

Master CCLK clock High time duty cycle

Master CCLK frequency

Master CCLK frequency for AES encrypted x16

Master CCLK frequency at start of configuration

50

F_{MCCK_START}

F_MCCKTOL

3

Frequency tolerance, master mode with respect to

nominal CCLK

50

CCLK Input (Slave Modes)

T_SCCKL

T_SCCKH

F_SCCK

Slave CCLK clock minimum Low time

2.50

100

2.50

100

2.50

100

2.50

70

ns, Min

Slave CCLK clock minimum High time

Slave CCLK frequency

MHz, Max

EMCCLK Input (Master Mode)

T_EMCCKL

T_EMCCKH

F_EMCCK

External master CCLK Low time

2.50

100

2.50

100

2.50

100

2.50

70

ns, Min

External master CCLK High time

External master CCLK frequency

MHz, Max

Master/Slave Serial Mode Programming Switching

T_DCCK/T_CCKDDIN Setup/Hold

4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00

ns, Min

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 68: Configuration Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

T_CCO

SelectMAP Mode Programming Switching

T_SMDCCK/T_SMCCKDD[31:00] Setup/Hold

_SMCSCCK/T_SMCCKCSCSI_B Setup/Hold

DOUT clock to out

8.00

9.00

ns, Max

4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00

4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00

10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00

ns, Min

ns, Max

T

T_SMWCCK/T_SMCCKW

T_SMCKCSO

RDWR_B Setup/Hold

CSO_B clock to out (330 Ω pull-up resistor

required)

7.00

8.00

T_SMCO

D[31:00] clock to out in readback

Readback frequency

8.00

100

8.00

100

8.00

100

10.00

70

ns, Max

F_RBCCK

MHz, Max

Boundary-Scan Port Timing Specifications

T_TAPTCK/T_TCKTAP

T_TCKTDO

TMS and TDI Setup/Hold

TCK falling edge to TDO output

TCK frequency

3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00

ns, Min

ns, Max

7.00

66

7.00

66

7.00

66

8.50

50

F_TCK

MHz, Max

BPI Master Flash Mode Programming Switching

(2)

T_BPICCO

A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,

ADV_B clock to out

8.50

10.00

ns, Max

ns, Min

T

_BPIDCC/T_BPICCD

D[15:00] Setup/Hold

4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00

SPI Master Flash Mode Programming Switching

T_SPIDCC/T_SPICCD

T_SPICCM

D[03:00] Setup/Hold

MOSI clock to out

FCS_B clock to out

3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00

ns, Min

ns, Max

8.00

9.00

T_SPICCFC

Notes:

1. To support longer delays in configuration, use the design solutions described in UG470: 7 Series FPGA Configuration User Guide.

2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.

eFUSE Programming Conditions

Table 69 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA

Configuration User Guide.

(1)

Table 69: eFUSE Programming Conditions

Symbol

Description

Min

–

Typ

–

Max

115

125

Units

mA

I_FS

t _j

Notes:

1. The FPGA must not be configured during eFUSE programming.

V_CCAUXsupply current

Temperature range

15

–

°C

DS182 (v1.9) October 10, 2012

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57

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Revision History

The following table shows the revision history for this document:

Date

Version

1.0

Description

03/01/11

04/01/11

Initial Xilinx release.

1.1

Added the XC7K355T, XC7K420T, and XC7K480T devices throughout data sheet. Added the

extended temperature range discussion to page 1. Updated V_{CCAUX_IO}in Table 2. Edits to clarify

Power-On/Off Power Supply Sequencing power sequencing discussion. Added I_{CCAUX_IO}and I_CCBRAM

to Table 6 and Table 7. Updated MMCM_F_INDUTYand added F_INJITTER, T_OUTJITTER, T_EXTFDVAR, and

Note 3 to Table 38. Removed the SBG324 package from Table 50. Updated the Notice of Disclaimer.

10/04/11

1.2

Replaced -1L with -2L throughout this data sheet. Updated Min/Max values and removed Note 5 from

Table 2. Clarified Power-On/Off Power Supply Sequencing power sequencing discussion including

adding T_VCCO2VCCAUXto Table 8. Updated V_ICMin Table 12 and Table 13. Added Note 1 to table 12.

Updated Table 69 including adding Note 1. Added Absolute Maximum Ratings for GTX Transceivers.

Revised the reference clock maximum frequency (F_GCLK) in Table 55. Added Table 57. Added LVTTL

and removed SSTL135_II and SSTL15_II specifications from Table 19. Removed HSTL_III from

Table 20. Removed the I/O Standard Adjustment Measurement Methodology section. Use IBIS for

more accurate information and measurements. Updated T_{IDELAYPAT_JIT}in Table 26. Added T_AS/T_AHto

Table 28. Added T_{RDCK_DI_WF_NC}/T_{RCKD_DI_WF_NC}and T_{RDCK_DI_RF}/T_{RCKD_DI_RF}to Table 31.

Completely updated Table 68. Updated the AC Switching Characteristics in Table 19, Table 20,

Table 21, Table 22, Table 23, Table 24, Table 26 through Table 38, Table 40 though Table 37, and Table

67.

11/03/11

02/13/12

1.3

1.4

Revised the V_OCMspecification in Table 12. Updated the AC Switching Characteristics based upon the

ISE 13.3 v1.02 speed specification throughout document including Table 19 and Table 20. Added

MMCM_T_FBDELAYwhile adding MMCM_ to the symbol names of a few specifications in Table 38 and

PLL to the symbol names in Table 39. In Table 40 through Table 47, updated the pin-to-pin descriptions

with the SSTL15 standard. Updated units in Table 49.

Updated summary description on page 1. In Table 2, revised V_CCOfor the 3.3V HR I/O banks and

updated T_j. Added typical values to Table 3. Updated the notes in Table 6. Added MGTAVCC,

MGTAVTT, and MGTVCCAUX power supply ramp times to Table 8. Rearranged Table 9, added

Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and

removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II.

Added Table 10 and Table 11. Revised the specifications in Table 12 and Table 13. Updated the

eFUSE Programming Conditions section and removed the endurance table. Added the IO_FIFO

Switching Characteristics table. Revised I_CCADCand updated Note 1 in Table 67. Revised DDR LVDS

transmitter data width in Table 16. Updated the AC Switching Characteristics based upon the ISE 13.4

v1.03 speed specification throughout document. Removed notes from Table 28 as they are no longer

applicable. Updated specifications in Table 68. Updated Note 1 in Table 37.

In the GTX Transceiver DC Input and Output Levels section: Revised V_IN, and added I_DCINand I_DCOUT

to Table 51. Added Note 4 to Table 53. In Table 55, revised F_GCLK, removed T_PHASE, and added

T

_DLOCK. Revised specifications and added Note 2 to Table 57. Added Table 58 and Table 59 along with

GTX Transceiver Protocol Jitter Characteristics in Table 60 through Table 65.

05/23/12

1.5

Reorganized entire data sheet including adding Table 44 and Table 48.

Updated T_SOLin Table 1. Updated I_BATTand added R_{IN_TERM}to Table 3. Added values to Table 6 and

Table 7. Updated Power-On/Off Power Supply Sequencing, page 6 with regards to GTX transceivers.

Updated many parameters in Table 9 including SSTL135 and SSTL135_R. Removed V_OXcolumn and

added DIFF_HSUL_12 to Table 11. Updated V_OLin Table 12. Updated Table 16 and removed notes 2

and 3. Updated Table 17.

Updated the AC Switching Characteristics based upon the ISE 14.1 v1.04 for the -3, -2, -2L (1.0V), -1,

and -2L (0.9V) speed specifications throughout the document.

In Table 31, updated Reset Delays section including Note 10 and Note 11. Added data for T_LOCKand

T

_DLOCKin Table 55. Updated many of the XADC specifications in Table 67 and added Note 2. Updated

and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from

Table 68 to Table 38 and Table 39.

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58

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Description

Date

Version

07/25/12

1.6

Updated the descriptions, changed V_INand Note 2 and added Note 4 in Table 1. In Table 2, changed

descriptions and notes, removed Note 7, changed GTX transceiver parameters and values and added

Note 9. Updated parameters in Table 3. Added Table 4 and Table 5.

Changed the typical values for many of the devices in Table 7. Updated LVCMOS12 and the SSTLs in

Table 9. Updated many of the specifications in Table 10 and Table 11.

Updated speed specification to v1.06 (-3, -2, -2L(1.0V), -1) and v1.05 (-2L(0.9V)) with appropriate

changes to Table 14 and Table 15 including production release of the XC7K325T and the XC7K410T

in the -2, -2L(1.0V), and -1 speed designations.

Added notes and specifications to Table 17 and Table 18.

Updated the IOB Pad Input/Output/3-State discussion and changed Table 21 by adding

T_{IOIBUFDISABLE}

.

Removed many of the combinatorial delay specifications and T_CINCK/T_CKCINfrom Table 28.

Rearranged Table 51 including moving some parameters to Table 1. Added Table 56. Updated

Table 57. In Table 59, updated SJ Jitter Tolerance with Stressed Eye section, page 51 and Note 8.

Added Note 1, Note 2, and Note 3 to Table 62. Added Note 1 and Note 2 to Table 63, and line rate

ranges. Updated Table 64 including adding Note 1. Updated Table 65 including adding Note 1.

In Table 67 updated Note 1 and added Note 4. In Table 68, updated T_PORand F_EMCCK

.

09/04/12

09/26/12

1.7

1.8

Updated Table 14 and Table 15 for production release of the XC7K160T in the -2, -2L(1.0V), and -1

speed designations.

In Table 2, revised V_CCINTand V_CCBRAMand added Note 2. Updated Table 14 and Table 15 for

production release of the XC7K480T in the -2, -2L(1.0V), and -1 speed designations and the

XC7K325T and XC7K410T in the -3 speed designation.

10/10/12

1.9

Updated the I_CCINTMINvalue for the XC7K355T in Table 7. Updated Table 14 and Table 15 for

production release of the XC7K420T in the -2, -2L(1.0V), and -1 speed designations.

Notice of Disclaimer

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the

maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF

MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable

(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related

to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,

incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of

any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility

of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update.

You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to

the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to

warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or

for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical

Applications: http://www.xilinx.com/warranty.htm#critapps.

AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-

SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A

VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN

THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)

USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY

USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

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59


型号：	XC7Z020-2CLG484Q
厂家：	XILINX, INC
描述：	Multifunction Peripheral,
文件：	总59页 (文件大小：2245K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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