XC7Z020-3CLG484C_技术文档

Zynq-7000 All Programmable SoC

(XC7Z010 and XC7Z020):

DC and AC Switching Characteristics

Preliminary Product Specification

DS187 (v1.3) February 11, 2013

Introduction

The Zynq™-7000 All Programmable SoCs are available in

-3, -2, and -1 speed grades, with -3 having the highest

performance. Zynq-7000 device DC and AC characteristics

are specified in commercial, extended, and industrial

temperature ranges. Except the operating temperature

range or unless otherwise noted, all the DC and AC

electrical parameters are the same for a particular speed

grade (that is, the timing characteristics of a -1 speed grade

industrial device are the same as for a -1 speed grade

commercial device). However, only selected speed grades

and/or devices are available in the commercial, extended, or

industrial temperature range.

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The

parameters included are common to popular designs and

typical applications.

This Zynq-7000 AP SoC (XC7Z010 and XC7Z020) data

sheet, part of an overall set of documentation on the

Zynq-7000 AP SoCs, is available on the Xilinx website at

www.xilinx.com/zynq. All specifications are subject to

change without notice.

DC Characteristics

Table 1: Absolute Maximum Ratings

(1)

Symbol

Description

Min

Max

Units

Processing System (PS)

V_CCPINT

V_CCPAUX

V_CCPLL

PS internal logic supply

–0.5

1.1

V

PS auxiliary supply voltage

PS PLL supply

2.0

V_{CCO_DDR}

PS DDR I/O supply voltage

PS MIO I/O supply voltage

PS input reference voltage

2.0

(2)

V_{CCO_MIO}

V_PREF

3.6

2.0

(2)(3)(4)(5)(6)

V_{CCO_DDR}+ 0.5

V_PIN

PS DDR and MIO I/O input voltage

V_{CCO_MIO}+ 0.5

–0.5

2.625

PS DDR and MIO I/O input voltage for V_REFand differential I/O standards

V

Programmable Logic (PL)

1.1

2.0

V_CCINT

V_CCAUX

V_CCBRAM

V_CCO

PL internal supply voltage

–0.5

V

PL auxiliary supply voltage

1.1

PL supply voltage for the block RAM memories

PL supply voltage for 3.3V HR I/O banks

Input reference voltage

3.6

2.0

V_REF

(3)(4)(5)(6)

V_CCO+ 0.5

2.625

2.0

V_IN

I/O input voltage

I/O input voltage for V_REFand differential I/O standards

Key memory battery backup supply

V_CCBATT

in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks

of ARM Ltd. All other trademarks are the property of their respective owners.

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Preliminary Product Specification

1

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)

Table 1: Absolute Maximum Ratings (Cont’d)

Symbol

XADC

V_CCADC

V_REFP

Description

Min

Max

Units

–0.5

2.0

XADC supply relative to GNDADC

V

XADC reference input relative to GNDADC

Temperature

T_STG

Storage temperature (ambient)

–65

–

150

°C

T_SOL

Maximum soldering temperature for Pb/Sn component bodies⁽⁷⁾

Maximum soldering temperature for Pb-free component bodies⁽⁷⁾

Maximum junction temperature⁽⁷⁾

+220

+260

+125

–

T_j

–

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. Applies to both MIO supply banks V

and V

.

CCO_MIO0

CCO_MIO1

3. The lower absolute voltage specification always applies.

4. For I/O operation, refer to UG471, 7 Series FPGAs SelectIO Resources User Guide or UG585, Zynq-7000 All Programmable SoC Technical

Reference Manual.

5. The maximum limit applies to DC signals.

6. For maximum undershoot and overshoot AC specifications, see Table 4.

7. For soldering guidelines and thermal considerations, see UG865, Zynq-7000 All Programmable SoC Packaging and Pinout Specification.

(1)(2)

Table 2: Recommended Operating Conditions

Symbol

PS

Description

Min

Typ

Max

Units

V_CCPINT

V_CCPAUX

V_CCPLL

PS internal supply voltage

PS auxiliary supply voltage

PS PLL supply

0.95

1.71

1.14

1.71

–0.20

1.00

1.80

1.05

1.89

3.465

V

V_{CCO_DDR}

PS DDR I/O supply voltage

(3)

V_{CCO_MIO}

PS MIO I/O supply voltage for MIO banks

PS DDR and MIO I/O input voltage

–

(3)(4)

V_{CCO_DDR}+ 0.20

V_{CCO_MIO}+ 0.20

V_PIN

PS DDR and MIO I/O input voltage for V_REFand differential I/O

standards

–0.20

–

2.625

V

PL

V_CCINT

V_CCAUX

V_CCBRAM

PL internal supply voltage

0.95

1.71

0.95

1.14

–0.20

–

1.00

1.80

1.00

–

1.05

1.89

V

PL auxiliary supply voltage

PL block RAM supply voltage

1.05

V

(5)(6)

V_CCO

PL supply voltage for 3.3V HR I/O banks

I/O input voltage

3.465

V_CCO+ 0.20

2.625

10

V

–

V

(4)

V_IN

I/O input voltage for V_REFand differential I/O standards

–

V

Maximum current through any pin in a powered or unpowered bank

when forward biasing the clamp diode—PS or PL pins

–

mA

(7)

I_IN

(8)

V_CCBATT

XADC

Battery voltage

1.0

–

1.89

V

V_CCADC

V_REFP

XADC supply relative to GNDADC

Externally supplied reference voltage

1.71

1.20

1.80

1.25

1.89

1.30

V

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Preliminary Product Specification

2

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)(2)

Table 2: Recommended Operating Conditions

(Cont’d)

Symbol

Description

Min

Typ

Max

Units

Temperature

Junction temperature operating range for commercial (C) temperature

devices

0

–

85

°C

Junction temperature operating range for extended (E) temperature

devices

100

T_j

Junction temperature operating range for industrial (I) temperature

devices

–40

Notes:

1. All voltages are relative to ground. The PL and PS share a common ground.

2. For the design of the power distribution system consult UG933, Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide.

3. Applies to both MIO supply banks V and V

.

CCO_MIO1

CCO_MIO0

4. The lower absolute voltage specification always applies.

5. Configuration data is retained even if V drops to 0V.

CCO

6. Includes V

of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.

CCO

7. A total of 200 mA per PS or PL bank should not be exceeded.

8. is required only when using bitstream encryption. If battery is not used, connect V

V

to either ground or V

.

CCAUX

CCBATT

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol Description

V_DRINT

Min

0.75

1.5

–

Typ⁽¹⁾

Max

–

Units

V

Data retention V_CCINTvoltage (below which configuration data might be lost)

Data retention V_CCAUXvoltage (below which configuration data might be lost)

V_REFleakage current per pin

–

40

V_DRI

I_REF

I_L

–

V

15

µA

pF

µA

mA

nA

Ω

Input or output leakage current per pin (sample-tested)

PL die input capacitance at the pad

–

15

(2)

C_IN

–

8

(2)

C_PIN

PS die input capacitance at the pad

–

8

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.3V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 2.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.2V

Pad pull-down (when selected) @ V_IN= 3.3V

90

68

34

23

12

68

45

–

330

250

220

150

120

330

180

25

I_RPU

I_RPD

Pad pull-down (when selected) @ V_IN= 1.8V

I_CCADC

Analog supply current, analog circuits in powered up state

Battery supply current

(3)

I_BATT

–

150

55

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E)

temperature devices.

28

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E)

temperature devices.

35

44

50

60

65

83

Ω

(4)

R_{IN_TERM}

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E)

temperature devices.

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

3

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)

Symbol

Description

Min

–

Typ⁽¹⁾

1.010

2

Max

Units

n

r

Temperature diode ideality factor

Temperature diode series resistance

–

Ω

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. This measurement represents the die capacitance at the pad, not including the package.

3. Maximum value specified for worst case process at 25°C.

4. Termination resistance to a V

/2 level.

CCO

(1)

Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and 3.3V HR I/O Banks

IN

AC Voltage Overshoot

% of UI @–40°C to 100°C

AC Voltage Undershoot

% of UI @–40°C to 100°C

V_CCO+ 0.40

100

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

100

61.7

25.8

11.0

4.77

2.10

0.94

0.43

0.20

0.09

0.04

0.02

V

_CCO+ 0.45

_CCO+ 0.50

V

100

V_CCO+ 0.55

_CCO+ 0.60

V_CCO+ 0.65

100

V

46.6

21.2

9.75

4.55

2.15

1.02

0.49

0.24

V

_CCO+ 0.70

_CCO+ 0.75

V

V_CCO+ 0.80

V

_CCO+ 0.85

_CCO+ 0.90

V

V_CCO+ 0.95

Notes:

1. A total of 200 mA per bank should not be exceeded.

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

4

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

2

Table 5: Typical Quiescent Supply Current

Speed Grade

Symbol

I_CCPINTQ

I_CCPAUXQ

I_CCDDRQ

I_CCINTQ

Description

Device

XC7Z010

Units

-3

122

13

4

-2

122

13

4

-1

122

13

4

mA

PS quiescent V_CCPINTsupply current

PS quiescent V_CCPAUXsupply current

PS quiescent V_{CCO_DDR}supply current

PL quiescent V_CCINTsupply current

PL quiescent V_CCAUXsupply current

PL quiescent V_CCOsupply current

XC7Z020

XC7Z010

XC7Z020

XC7Z010

XC7Z020

XC7Z010

XC7Z020

XC7Z010

XC7Z020

XC7Z010

XC7Z020

XC7Z010

XC7Z020

4

34

78

18

38

3

34

78

18

38

3

34

78

18

38

3

I_CCAUXQ

I_CCOQ

3

I_CCBRAMQPL quiescent V_CCBRAMsupply current

6

Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ) with single-ended SelectIO resources.

j

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for

conditions other than those specified.

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

5

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

PS Power-On/Off Power Supply Requirements

The recommended power-on sequence is V

, V

and V

together, then the PS V

supplies (V

,

CCO_MIO0

CCPINT CCPAUX

CCPLL

CCO

V

, and V

) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The

CCO_MIO1

CCO_DDR

recommended power-off sequence is the reverse of the power-on sequence. If V

, V

and the PS V

supplies

CCPAUX CCPLL

CCO

(V

, V

, and V

) have the same recommended voltage levels, then they can be powered by the

CCO_MIO0

CCO_MIO1

CCO_DDR

same supply and ramped simultaneously. Xilinx recommends powering V

optional ferrite bead filter.

with the same supply as V

, with an

CCPAUX

CCPLL

For V

and V

voltages of 3.3V:

CCO_MIO1

CCO_MIO0

•

The voltage difference between V

/V

and V

must not exceed 2.625V for longer than

CCPAUX

CCO_MIO0

CCO_MIO1

T

for each power-on/off cycle to maintain device reliability levels.

VCCO2VCCAUX

•

The T

time can be allocated in any percentage between the power-on and power-off ramps.

VCCO2VCCAUX

PS Power-on Reset

The PS provides the power on reset (PS_POR_B) input signal which must be held Low until all PS power supplies are stable

and within operating limits. Additionally, PS_POR_B must be held Low until PS_CLK is stable for 2,000 clocks.

PL Power-On/Off Power Supply Sequencing

The recommended power-on sequence for the PL is V

, V

, and V

to achieve minimum current draw

CCO

CCINT CCBRAM CCAUX

and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on

sequence. If V and V have the same recommended voltage levels then both can be powered by the same

CCINT

CCBRAM

supply and ramped simultaneously. If V

and V

have the same recommended voltage levels then both can be

CCAUX

CCO

powered by the same supply and ramped simultaneously.

For V voltages of 3.3V in HR I/O banks and configuration bank 0:

CCO

•

The voltage difference between V

power-on/off cycle to maintain device reliability levels.

and V

must not exceed 2.625V for longer than T

for each

CCO

CCAUX

VCCO2VCCAUX

The T time can be allocated in any percentage between the power-on and power-off ramps.

VCCO2VCCAUX

PS—PL Power Sequencing

The PS and PL power supplies are fully independent. There are no sequencing requirements between the PS (V

,

CCPINT

V

, V

, and V

) and PL (V

, V

, and V

) power

CCPAUX

CCPLL

CCO_DDR

CCO_MIO0

CCO_MIO1

CCINT CCBRAM

CCAUX

CCO

CCADC

supplies.

DS187 (v1.3) February 11, 2013

Preliminary Product Specification

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6

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Power Supply Requirements

Table 6 shows the minimum current, in addition to I

, that is required by Zynq-7000 devices for proper power-on and

CCQ

configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four PL supplies

have passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after

V

is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on

CCINT

these supplies.

Table 6: Power-On Current for Zynq-7000 Devices⁽¹⁾

I_CCPINTMIN

Typ⁽²⁾

I_CCPAUXMIN

Typ⁽²⁾

I_CCDDRMIN

Typ⁽²⁾

I_CCINTMIN

Typ⁽²⁾

I_CCAUXMIN

Typ⁽²⁾

I_CCOMIN

Typ⁽²⁾

I_CCBRAMMIN

Typ⁽²⁾

Device

Units

I_CCPINTQ+70 I_CCPAUXQ+40 I_CCDDRQ+ 100 mA I_CCINTQ+40 I_CCAUXQ+60 I_CCOQ+ 90 mA I_CCBRAMQ+40 mA

per bank per bank

XC7Z010

I_CCPINTQ+70 I_CCPAUXQ+40 I_CCDDRQ+ 100 mA I_CCINTQ+70 I_CCAUXQ+60 I_CCOQ+ 90 mA I_CCBRAMQ+40 mA

per bank per bank

XC7Z020

Notes:

1. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.

2. Typical values are specified at nominal voltage, 25°C.

Table 7: Power Supply Ramp Time

Symbol

T_VCCPINT

Description

Ramp time from GND to 90% of V_CCPINT

Ramp time from GND to 90% of V_CCPAUX

Ramp time from GND to 90% of V_{CCO_DDR}

Ramp time from GND to 90% of V_{CCO_MIO}

Ramp time from GND to 90% of V_CCINT

Ramp time from GND to 90% of V_CCO

Ramp time from GND to 90% of V_CCAUX

Ramp time from GND to 90% of V_CCBRAM

Conditions

Min

0.2

–

Max Units

50

ms

T_VCCPAUX

T_{VCCO_DDR}

T_{VCCO_MIO}

T_VCCINT

50

T_VCCO

50

T_VCCAUX

T_VCCBRAM

50

T_j= 100°C⁽¹⁾

T_j= 85°C⁽¹⁾

500

800

Allowed time per power cycle for V_CCO– V_CCAUX> 2.625V

and V_{CCO_MIO}– V_CCPAUX> 2.625V

T_VCCO2VCCAUX

ms

–

Notes:

1. Based on 240,000 power cycles with nominal V

of 3.3V or 36,500 power cycles with worst case V

of 3.465V.

CCO

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Preliminary Product Specification

7

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

DC Input and Output Levels

Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended

IL

IH

OL

OH

operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that

OL

OH

all standards meet their specifications. The selected standards are tested at a minimum V

with the respective V and

CCO

OL

V

voltage levels shown. Other standards are sample tested.

OH

PS I/O Levels

(1)

Table 8: PS DC Input and Output Levels

V_IL

V, Max

V_IH

V_OL

V, Max

0.450

0.400

V_OH

I_OLI_OH

mA mA

I/O

Bank

Standard

V, Min

V, Max

V, Min

MIO LVCMOS18 –0.300 35% V_{CCO_MIO}65% V_{CCO_MIO}V_{CCO_MIO}+ 0.300

V_{CCO_MIO}– 0.450

V_{CCO_MIO}– 0.400

8

–8

MIO LVCMOS25 –0.300

MIO LVCMOS33 –0.300

0.700

0.800

1.700

2.000

V

_{CCO_MIO}+ 0.300

3.450

MIO HSTL_I_18 –0.300 V_PREF– 0.100 V_PREF+ 0.100 V_{CCO_MIO}+ 0.300

DDR SSTL18_I

DDR SSTL15

DDR SSTL135

DDR HSUL_12

–0.300 V_PREF– 0.125 V_PREF+ 0.125 V_{CCO_DDR}+ 0.300 V_{CCO_DDR}/2 – 0.470 V_{CCO_DDR}/2 + 0.470

–0.300 V_PREF– 0.100 V_PREF+ 0.100 V_{CCO_DDR}+ 0.300 V_{CCO_DDR}/2 – 0.175 V_{CCO_DDR}/2 + 0.175 13.0 –13.0

–0.300 V_PREF– 0.090 V_PREF+ 0.090 V_{CCO_DDR}+ 0.300 V_{CCO_DDR}/2 – 0.150 V_{CCO_DDR}/2 + 0.150 13.0 –13.0

–0.300 V_PREF– 0.130 V_PREF+ 0.130 V_{CCO_DDR}+ 0.300

20% V_{CCO_DDR}

80% V_{CCO_DDR}

0.1 –0.1

Notes:

1. Tested according to relevant specifications.

Table 9: PS Complementary Differential DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Min V,Typ V, Max V,Min V, Max

V_ID

V_OL

V_OH

I_OL

I_OH

Bank I/O Standard

V, Max

V, Min

mA, Max mA, Min

DDR DIFF_HSUL_12 0.300 0.600 0.850 0.100

–

20% V_CCO

80% V_CCO

0.100

13.0

8.00

–0.100

–13.0

–8.00

DDR DIFF_SSTL135

DDR DIFF_SSTL15

0.300 0.675 1.000 0.100

0.300 0.750 1.125 0.100

(V_{CCO_DDR}/2) – 0.150 (V_{CCO_DDR}/2) + 0.150

(V_{CCO_DDR}/2) – 0.175 (V_{CCO_DDR}/2) + 0.175

(V_{CCO_DDR}/2) – 0.470 (V_{CCO_DDR}/2) + 0.470

DDR DIFF_SSTL18_I 0.300 0.900 1.425 0.100

Notes:

1.

2.

3.

4.

V

is the input common mode voltage.

is the input differential voltage (Q–Q).

is the single-ended low-output voltage.

ICM

ID

OL

OH

is the single-ended high-output voltage.

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Preliminary Product Specification

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

PL I/O Levels

(1)(2)

Table 10: SelectIO DC Input and Output Levels

V_IL

V_IH

V_OL

V, Max

0.400

V_OH

I_OL

I_OH

I/O Standard

V, Min

–0.300

–0.500

–0.300

V, Max

V, Min

V, Max

V, Min

mA

HSTL_I

V_REF– 0.100

V_REF+ 0.100 V_CCO+ 0.300

V_REF+ 0.130 V_CCO+ 0.300

V_CCO– 0.400

80% V_CCO

V_CCO– 0.400

75% V_CCO

V_CCO– 0.450

V_CCO– 0.400

2.400

8.00

–8.00

–16.00

–0.10

Note 3

Note 4

Note 5

Note 4

Note 5

–0.10

–0.50

–13.00

–8.90

–13.00

–8.90

–8.00

–13.40

HSTL_I_18

HSTL_II

V

_REF– 0.100

0.400

8.00

0.400

16.00

0.10

HSTL_II_18

HSUL_12

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

V_REF– 0.100

V_REF– 0.130

35% V_CCO

0.7

0.400

20% V_CCO

0.400

65% V_CCO

1.700

V_CCO+ 0.300

Note 3

Note 4

Note 5

Note 4

Note 5

0.10

25% V_CCO

0.450

V

_CCO+ 0.300

3.450

0.400

0.8

2.000

0.400

0.8

2.000

3.450

0.400

MOBILE_DDR

PCI33_3

20% V_CCO

30% V_CCO

V_REF– 0.090

80% V_CCO

50% V_CCO

V_CCO+ 0.300

V_CCO+ 0.500

10% V_CCO

90% V_CCO

1.50

SSTL135

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 13.00

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 8.90

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175 13.00

SSTL135_R

SSTL15

V_REF– 0.090

V_REF– 0.100

SSTL15_R

SSTL18_I

SSTL18_II

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.470 V_CCO/2 + 0.470

8.90

8.00

V

_REF– 0.125

V_REF– 0.125

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.600 V_CCO/2 + 0.600 13.40

Notes:

1. Tested according to relevant specifications.

2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks.

3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.

4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.

5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.

6. For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.

Table 11: Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Min V, Typ V, Max V, Min V, Typ V, Max

0.300 1.200 1.425 0.100

V_ID

V_OCM

V_OD

I/O Standard

V, Min

–

V, Typ

1.250

1.200

0.950

1.200

V, Max

–

V, Min V, Typ V, Max

Note 5

BLVDS_25

–

MINI_LVDS_25 0.300 1.200 V_CCAUX0.200 0.400 0.600

1.000

0.500

1.000

1.400

0.300 0.450 0.600

0.100 0.250 0.400

0.100 0.350 0.600

PPDS_25

RSDS_25

TMDS_33

0.200 0.900 V_CCAUX0.100 0.250 0.400

0.300 0.900 1.500 0.100 0.350 0.600

2.700 2.965 3.230 0.150 0.675 1.200

V

_CCO–0.405 V_CCO–0.300 V_CCO–0.190 0.400 0.600 0.800

Notes:

1.

2.

3.

4.

5.

V

is the input common mode voltage.

is the input differential voltage (Q–Q).

ICM

ID

is the output common mode voltage.

OCM

is the output differential voltage (Q–Q).

for BLVDS will vary significantly depending on topology and loading.

OD

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 12: Complementary Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V_ID

V_OL

V_OH

I_OL

mA, Max

8.00

I_OH

mA, Min

–8.00

–16.00

–0.100

–13.0

–8.9

I/O Standard

V, Min V,Typ V, Max V,Min V, Max

V, Max

0.400

V, Min

DIFF_HSTL_I

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.600 0.850 0.100

–

V_CCO–0.400

DIFF_HSTL_I_18

DIFF_HSTL_II

0.400

8.00

0.400

V

_CCO–0.400

16.00

0.100

13.0

DIFF_HSTL_II_18

DIFF_HSUL_12

0.400

V_CCO–0.400

80% V_CCO

90% V_CCO

20% V_CCO

10% V_CCO

DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100

DIFF_SSTL135

DIFF_SSTL135_R

DIFF_SSTL15

0.300 0.675 1.000 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

(V_CCO/2) – 0.150 (V_CCO/2) + 0.150

(V_CCO/2) – 0.175 (V_CCO/2) + 0.175

(V_CCO/2) – 0.470 (V_CCO/2) + 0.470

(V_CCO/2) – 0.600 (V_CCO/2) + 0.600

8.9

13.0

–13.0

–8.9

DIFF_SSTL15_R

DIFF_SSTL18_I

DIFF_SSTL18_II

8.9

8.00

–8.00

–13.4

13.4

Notes:

1.

2.

3.

4.

V

is the input common mode voltage.

is the input differential voltage (Q–Q).

is the single-ended low-output voltage.

ICM

ID

OL

OH

is the single-ended high-output voltage.

(1)

Table 13: LVDS_25 DC Specifications

Symbol

V_CCO

V_OH

DC Parameter

Supply voltage

Conditions

Min

Typ

2.5

–

Max

Units

2.375

–

2.625

1.675

–

V

Output High voltage for Q and Q

Output Low voltage for Q and Q

R_T= 100 Ω across Q and Q signals

V_OL

0.700

247

–

V

Differential output voltage (Q – Q),

Q = High (Q – Q), Q = High

350

600

mV

V_ODIFF

V_OCM

V_IDIFF

V_ICM

Output common-mode voltage

R_T= 100 Ω across Q and Q signals

1.00

100

0.3

1.25

350

1.2

1.425

600

V

mV

V

Differential input voltage (Q – Q), Q = High (Q – Q), Q = High

Input common-mode voltage

1.425

Notes:

1. For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.

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Preliminary Product Specification

10

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

AC Switching Characteristics

All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.4 and the 14.4

device pack v1.05 for the -3, -2, and -1 speed grades.

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or

Production. Each designation is defined as follows:

Advance Product Specification

These specifications are based on simulations only and are typically available soon after device design specifications are

frozen. Although speed grades with this designation are considered relatively stable and conservative, some

under-reporting might still occur.

Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades

with this designation are intended to give a better indication of the expected performance of production silicon. The

probability of under-reporting delays is greatly reduced as compared to Advance data.

Production Product Specification

These specifications are released once enough production silicon of a particular device family member has been

characterized to provide full correlation between specifications and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest

speed grades transition to Production before faster speed grades.

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are

representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and

back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another depends

completely on the status of the fabrication process for each device. Table 14 correlates the current status of each Zynq-7000

device on a per speed grade basis.

Table 14: Zynq-7000 Device Speed Grade Designations

Speed Grade Designations

Device

Advance

Preliminary

-3, -2, -1

-3

Production

XC7Z010

XC7Z020

-2, -1

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Preliminary Product Specification

11

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Production Silicon and ISE Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is

released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent

speed specification releases.

Table 15 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed

specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases

required for production. All subsequent releases of software and speed specifications are valid.

Table 15: Zynq-7000 Device Production Software and Speed Specification Release

Speed Grade Designations

Device

-3

-2

-1

XC7Z010

XC7Z020

ISE 14.4 and the 14.4 device pack v1.05

Notes:

1. Blank entries indicate a device and/or speed grade in advance or preliminary status.

PS Performance Characteristics

For further design requirement details, refer to UG585, Zynq-7000 All Programmable SoC Technical Reference Manual.

Table 16: CPU Clock Domains Performance

Speed Grade

Symbol

Clock Ratio

Description

Units

-3

-2

-1

(1)

F_{CPU_6X4X_621_MAX}

F_{CPU_3X2X_621_MAX}

F_{CPU_2X_621_MAX}

F_{CPU_1X_621_MAX}

F_{CPU_6X4X_421_MAX}

F_{CPU_3X2X_421_MAX}

F_{CPU_2X_421_MAX}

F_{CPU_1X_421_MAX}

Maximum CPU clock frequency

Maximum CPU_3X clock frequency

Maximum CPU_2X clock frequency

Maximum CPU_1X clock frequency

Maximum CPU clock frequency

Maximum CPU_3X clock frequency

Maximum CPU_2X clock frequency

Maximum CPU_1X clock frequency

800

400

267

133

710

355

178

733

367

244

122

600

300

150

667

333

222

111

533

267

133

MHz

6:2:1

(1)

4:2:1

Notes:

1. The maximum frequency during BootROM execution is 500 MHz across all speed specifications.

Table 17: PS DDR Clock Domains Performance

Speed Grade

Symbol

Description

Units

-3

-2

-1

F_{DDR3_MAX}

F_{DDR3L_MAX}

F_{DDR2_MAX}

F_{LPDDR2_MAX}

F_{DDRCLK_2XMAX}

Maximum DDR3 interface performance

Maximum DDR3L interface performance

Maximum DDR2 interface performance

Maximum LPDDR2 interface performance

Maximum DDR_2X clock frequency

1066

800

444

1066

800

408

1066

800

355

Mb/s

MHz

Notes:

1. All performance numbers apply to both internal and external V

configurations.

REF

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Preliminary Product Specification

12

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

PS Switching Characteristics

Clocks

Table 18: System Reference Clock Requirements

Symbol

T_JTPSCLK

Description

PS_CLK RMS clock jitter tolerance

Min

–

Typ

–

Max

0.5

60

Units

%

T_DCPSCLK

T_RFPSCLK

F_PSCLK

PS_CLK duty cycle

40

–

%

PS_CLK rise and fall time

PS_CLK frequency

4

–

ns

30

–

60

MHz

Table 19: PS PLL Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

60

-2

60

-1

60

T_{LOCK_PSPLL}

F_{PSPLL_MAX}

F_{PSPLL_MIN}

PLL maximum lock time

µs

PLL maximum output frequency

PLL minimum output frequency

2000

780

1800

780

1600

780

MHz

Resets

Table 20: PS Reset Requirements

Symbol

Description

Min

100

3

Typ

–

Max

Units

µs

T_PSPOR

T_PSRST

Required PS_POR_B assertion time⁽¹⁾

.

–

Required PS_SRST_B assertion time.

–

PS_CLK Clock Cycles

Notes:

1. PS_POR_B needs to be asserted low until PS supply voltages reach minimum levels.

PS Configuration

Table 21: Processor Configuration Access Port Switching Characteristics

Symbol

F_PCAPCK

Description

Min

Typ

Max

Units

Maximum processor configuration access port (PCAP)

frequency

–

100

MHz

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

DDR Memory Interfaces

(1)

Table 22: DDR3 Interface Switching Characteristics (1066 Mb/s)

Symbol Description

T_DQVALID

Min

500

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

131

ps

(3)

288

–

ps

–0.11

532

0.09

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

637

–

ps

Notes:

1. Recommended V

= 1.5V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses

IH

V (AC) to V

of CLK.

IL

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

(1)

Table 23: DDR3 Interface Switching Characteristics (800 Mb/s)

Symbol Description

T_DQVALID

Min

500

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

232

ps

(3)

401

–

ps

–0.10

722

0.06

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

882

–

ps

Notes:

1. Recommended V

= 1.5V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses

IH

V (AC) to V

of CLK.

IL

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)

Table 24: DDR3L Interface Switching Characteristics (800 Mb/s)

Symbol Description

T_DQVALID

Min

500

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

321

ps

(3)

380

–

ps

–0.12

636

0.04

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

853

–

ps

Notes:

1. Recommended V

= 1.35V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses

IH

V (AC) to V

of CLK.

IL

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

(1)

Table 25: LPDDR2 Interface Switching Characteristics (800 Mb/s)

Symbol Description

T_DQVALID

Min

500

196

328

0.90

202

353

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

ps

(3)

–

ps

1.06

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

–

ps

Notes:

1. Recommended V

= 1.2V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses V (AC)

IH

IL

to V

of CLK.

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)

Table 26: LPDDR2 Interface Switching Characteristics (400 Mb/s)

Symbol Description

T_DQVALID

Min

500

664

766

0.90

731

907

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

ps

(3)

–

ps

1.06

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

–

ps

Notes:

1. Recommended V

= 1.2V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses V (AC)

IH

IL

to V

of CLK.

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

(1)

Table 27: DDR2 Interface Switching Characteristics (800 Mb/s)

Symbol Description

T_DQVALID

Min

500

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

147

ps

(3)

376

–

ps

–0.07

732

0.08

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

938

–

ps

Notes:

1. Recommended V

= 1.8V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses

IH

V (AC) to V

of CLK.

IL

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

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Preliminary Product Specification

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)

Table 28: DDR2 Interface Switching Characteristics (400 Mb/s)

Symbol Description

T_DQVALID

Min

500

Max

Units

ps

Input data valid window

Output DQ to DQS skew

Output DQS to DQ skew

Output clock to DQS skew

–

(2)

T_DQDS

T_DQDH

T_DQSS

385

ps

(3)

662

–

ps

–0.11

1760

1739

0.06

–

T_CK

ps

(4)

T_CACK

T_CKCA

Command/address output setup time with respect to CLK

Command/address output hold time with respect to CLK

(5)

–

ps

Notes:

1. Recommended V

= 1.8V 5%.

CCO_DDR

2. Measurement is taken from either the rising edge of DQ that crosses V (AC) or the falling edge of DQ that crosses V (AC) to V

of DQS.

IH

IL

REF

3. Measurement is taken from either the rising edge of DQ that crosses V (DC) or the falling edge of DQ that crosses V (DC) to V

IL

IH

4. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (AC) or the falling edge of CMD/ADDR that crosses

IH

V (AC) to V

of CLK.

IL

REF

5. Measurement is taken from either the rising edge of CMD/ADDR that crosses V (DC) or the falling edge of CMD/ADDR that crosses

IL

V

(DC) to V

of CLK.

IH

REF

X-Ref Target - Figure 1

CLK

T

CKCA

T

CACK

Write

NOP

Command

T

CKCA

T

CACK

Bank, Col n

Address

DQS

T

DQSS

DQS

T

DQDH

T

DQDS

D0

D1

D2

D3

DQ

DS187_01_012213

Figure 1: DDR Output Timing Diagram

X-Ref Target - Figure 2

CLK

DQS

T

DQVALID

D1

DQ

D0

D2

D3

DS187_02_012213

Figure 2: DDR Input Timing Diagram

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Preliminary Product Specification

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17

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Static Memory Controller

(1)

Table 29: SMC Interface Delay Characteristics

Symbol

Description

Min

4.12

5.08

4.87

4.69

5.12

4.68

1.48

2.48

3.94

4.66

4.57

4.79

5.25

5.12

1.93

2.26

Max

6.45

6.33

6.40

5.89

6.44

5.89

3.09

3.33

5.73

6.45

5.95

6.13

6.74

6.48

3.05

3.15

Units

ns

T_NANDDOUT

T_NANDALE

T_NANDCLE

T_NANDWE

T_NANDRE

T_NANDCE

T_NANDDIN

T_NANDBUSY

T_SRAMA

NAND_IO output delay from last register to pad

NAND_ALE output delay from last register to pad

NAND_CLE output delay from last register to pad

NAND_WE_B output delay from last register to pad

NAND_RE_B output delay from last register to pad

NAND_CE_B output delay from last register to pad

NAND_IO setup time and input delay from pad to first register

NAND_BUSY setup time and input delay from pad to first register

SRAM_A output delay from last register to pad

T_SRAMDOUT

T_SRAMCE

T_SRAMOE

T_SRAMBLS

T_SRAMWE

T_SRAMDIN

T_SRAMWAIT

SRAM_DQ output delay from last register to pad

SRAM_CE output delay from last register to pad

SRAM_OE_B output delay from last register to pad

SRAM_BLS_B output delay from last register to pad

SRAM_WE_B output delay from last register to pad

SRAM_DQ setup time and input delay from pad to first register

SRAM_WAIT setup time and input delay from pad to first register

Notes:

1. All parameters do not include the package flight time and register controlled delays.

DS187 (v1.3) February 11, 2013

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18

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Quad-SPI Interfaces

Table 30: Quad-SPI Interface Switching Characteristics⁽¹⁾⁽²⁾

Symbol

Description

Min

Typical

Max

Units

Feedback Clock Enabled

T_DCQSPICLK1

T_QSPICKO1

T_QSPIDCK1

T_QSPICKD1

T_QSPISSCLK1

T_QSPICLKSS1

F_QSPICLK1

Quad-SPI clock duty cycle

44

–0.10

2.00

1.30

1

–

56

%

Data and slave select output delay

Input data setup time

3.40

ns

–

ns

Input data hold time

–

Slave select asserted to next clock edge

Clock edge to slave select deasserted

Quad-SPI device clock frequency

F_{QSPI_REF_CLK}cycle

MHz

1

–

100⁽³⁾

Feedback Clock Disabled

T_DCQSPICLK2Quad-SPI clock duty cycle

T_QSPICKO2

44

–

56

%

Data and slave select output delay

Input data setup time⁽⁴⁾

–0.10

3.80

ns

1

T_QSPIDCK2

11 – -------------------------------------------

–

ns

F

QSPI_REF_CLK

1

T_QSPICKD2

Input data hold time

--------------------------------------------------------

2 × F

QSPI_REF_CLK2

T_QSPISSCLK2

T_QSPICLKSS2

F_QSPICLK2

Slave select asserted to next clock edge

Clock edge to slave select deasserted

Quad-SPI device clock frequency

1

–

F_{QSPI_REF_CLK}cycle

MHz

40

Feedback Clock Enabled or Disabled

F_{QSPI_REF_CLK}Quad-SPI reference clock frequency

–

200

MHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, feedback clock pin has no load. Quad-SPI single slave select

4-bit I/O mode.

2. Dual slave select 4-bit stacked I/O configuration is not covered.

3. Requires appropriate component selection/board design.

4. Use 0 ns as the input data setup time when the calculated T

value is negative.

QSPIDCK2

X-Ref Target - Figure 3

QSPI{1,0}_SS_B

T

QSPISSCLKSS1

T

QSPISSCLK1

QSPI_SCLK_OUT

CPOL = 0

T

QSPISSCLKSS1

T

QSPISSCLK1

QSPI_SCLK_OUT

CPOL = 1

T

QSPICKD1

T

QSPICKO1

T

QSPIDCK1

QSPI{1,0}_IO_[3,0]

OUT1

INn-2

INn-1

INn

ds187_04_021013

Figure 3: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

X-Ref Target - Figure 4

QSPI{1,0}_SS_B

T

QSPISCLKSS2

QSPISSCLK2

QSPI_SCLK_OUT

(CPOL = 0)

T

QSPISCLKSS2

QSPISSCLK2

QSPI_SCLK_OUT

(CPOL = 1)

T

QSPICKD2

T

QSPIDCK2

QSPICKO2

QSPI{0,1}_IO_[3:0]

OUT0

OUT1

INn-1

INn

DS187_03_020713

Figure 4: Quad-SPI Interface (Feedback Clock Disabled) Timing Diagram

ULPI Interfaces

Table 31: ULPI Interface Clock Receiving Mode Switching Characteristics⁽¹⁾⁽⁶⁾

Symbol Description

T_ULPIDCKInput setup to ULPI clock, all inputs

Min

3.00

1.00

1.70

–

Typ

–

Max

Units

ns

–

T_ULPICKD

T_ULPICKO

F_ULPICLK

Input hold to ULPI clock, all inputs

ULPI clock to output valid, all outputs

ULPI device clock frequency

–

ns

–

8.86

–

ns

60

MHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, 60 MHz device clock frequency.

6. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.

X-Ref Target - Figure 5

USB{0,1}_ULPI_CLK

T

ULPIDCK

ULPICKD

USB{0,1}_ULPI_DATA[7:0] (Input)

ULPICKD

USB{0,1}_ULPI_DIR,

USB{0,1}_ULPI_NXT

T

ULPICKO

USB{0,1}_ULPI_STP

ULPICKO

USB{0,1}_ULPI_DATA[7:0] (Output)

DS187_05_021013

Figure 5: ULPI Interface Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

RGMII and MDIO Interfaces

(1)(2)(7)

Table 32: RGMII and MDIO Interface Switching Characteristics

Symbol

T_DCGETXCLK

T_GEMTXCKO

T_GEMRXDCK

T_GEMRXCKD

T_MDIOCLK

Description

Min

45

Typ

–

Max

55

0.50

–

Units

%

Transmit clock duty cycle

RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time

RGMII_RX_D[3:0], RGMII_RX_CTL input setup time

RGMII_RX_D[3:0], RGMII_RX_CTL input hold time

MDC output clock period

–0.50

0.80

400

160

80

–

ns

–

ns

–

ns

–

ns

T_MDIOCKH

T_MDIOCKL

MDC clock High time

–

ns

MDC clock Low time

–

ns

T_MDIODCK

T_MDIOCKD

T_MDIOCKO

F_GETXCLK

F_GERXCLK

MDIO input data setup time

–

ns

MDIO input data hold time

0

–

ns

MDIO data output delay

–

170

–

ns

RGMII_TX_CLK transmit clock frequency

RGMII_RX_CLK receive clock frequency

–

125

MHz

–

F_{ENET_REF_CLK}Ethernet reference clock frequency

–

Notes:

1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads. Values in this table are specified during 1000 Mb/s operation.

2. LVCMOS25 slow slew rate and LVCMOS33 are not supported.

7. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.

X-Ref Target - Figure 6

RGMII_TX_CLK

T

GEMTXCKO

RGMII_TX_D[3:0]

RGMII_TX_CTL

RGMII_RX_CLK

T

GEMRXCKD

GEMRXDCK

RGMII_RX_D[3:0]

RGMII_RX_CTL

T

MDIOCKL

MDIOCKH

MDIOCLK

MDIO_CLK

MDIO_IO (Input)

MDIO_IO (Output)

T

MDIOCKD

MDIODCK

T

MDIOCKO

DS187_06_021013

Figure 6: RGMII Interface Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

SD/SDIO Interfaces

(1)

Table 33: SD/SDIO Interface High Speed Mode Switching Characteristics

Symbol

T_DCSDHSCLK

T_SDHSCKO

T_SDHSDCK

T_SDHSCKD

F_{SD_REF_CLK}

F_SDHSCLK

Description

Min

–

Typ

50

–

Max

–

Units

%

SD device clock duty cycle

Clock to output delay, all outputs

Input setup time, all inputs

2.00

3.00

1.05

–

12.00

–

ns

–

ns

Input hold time, all inputs

–

ns

SD reference clock frequency

High speed mode SD device clock frequency

–

100

50

MHz

0

–

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

X-Ref Target - Figure 7

SD{0,1}_CLK

T

SDHSCKD

SDHSDCK

SD{0,1}_DATA[3:0],

SD{0,1}_CMD (input)

T

SDHSCKO

SD{0,1}_DATA[3:0],

SD{0,1}_CMD (output)

DS187_07_021013

Figure 7: SD/SDIO Interface High Speed Mode Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

I2C Interfaces

(1)

Table 34: I2C Fast Mode Interface Switching Characteristics

Symbol

T_DCI2CFCLK

T_I2CFCKO

Description

Min

–

Typ

50

–

Max

–

Units

%

I2C{0,1}SCL duty cycle

I2C{0,1}SDAO clock to out delay

I2C{0,1}SDAI setup time

–

900

–

ns

T_I2CFDCK

100

–

ns

F_I2CFCLK

I2C{0,1}SCL clock frequency

–

400

KHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

X-Ref Target - Figure 8

I2C{0,1}SCL

I2C{0,1}SDAI

T

I2CFDCK

T

I2CFCKO

I2C{0,1}SDAO

DS187_08_021013

Figure 8: I2C Fast Mode Interface Timing Diagram

(1)

Table 35: I2C Standard Mode Interface Switching Characteristics

Symbol

T_DCI2CSCLK

T_I2CSCKO

Description

Min

–

Typ

50

–

Max

–

Units

%

I2C{0,1}SCL duty cycle

I2C{0,1}SDAO clock to out delay

I2C{0,1}SDAI setup time

–

3450

–

ns

T_I2CSDCK

250

–

ns

F_I2CSCLK

I2C{0,1}SCL clock frequency

–

100

KHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

X-Ref Target - Figure 9

I2C{0,1}SCL

I2C{0,1}SDAI

T

I2CSDCK

T

I2CSCKO

I2C{0,1}SDAO

DS187_09_021013

Figure 9: I2C Standard Mode Interface Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

SPI Interfaces

(1)

Table 36: SPI Master Mode Interface Switching Characteristics

Symbol

T_DCMSPICLK

T_MSPIDCK

Description

Min

–

Typ

50

–

Max

Units

SPI master mode clock duty cycle

–

%

Input setup time for SPI{0,1}_MISO

2.00

8.20

–3.10

1

–

ns

T_MSPICKD

Input hold time for SPI{0,1}_MISO

–

ns

T_MSPICKO

Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS

Slave select asserted to first active clock edge

Last active clock edge to slave select deasserted

SPI master mode device clock frequency

SPI reference clock frequency

–

3.90

–

ns

F_{SPI_REF_CLK}cycles

MHz

T_MSPISSCLK

T_MSPICLKSS

F_MSPICLK

–

0.5

–

50.00

200.00

F_{SPI_REF_CLK}

–

MHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

X-Ref Target - Figure 10

SPI{0,1}_SS

SPI{0,1}_CLK (CPOL=0)

SPI{0,1}_CLK (CPOL=1)

SPI{0,1}_MOSI

T

MSPISSCLK

T

MSPICLKSS

T

MSPICKO

Dn

Dn–1

Dn–2

Dn–3

D0

T

MSPICKD

T

MSPIDCK

Dn

Dn–1

Dn–2

SPI{0,1}_MISO

DS187_10_021013

Figure 10: SPI Master (CPHA = 0) Interface Timing Diagram

X-Ref Target - Figure 11

SPI{0,1}_SS

SPI{0,1}_CLK (CPOL=0)

T

MSPICLKSS

MSPISSCLK

SPI{0,1}_CLK (CPOL=1)

SPI{0,1}_MOSI

T

MSPICKO

Dn

Dn–1

MSPICKD

Dn–2

Dn–3

D0

T

MSPIDCK

SPI{0,1}_MISO

Dn

Dn–1

Dn–2

Dn–3

D0

DS187_11_021013

Figure 11: SPI Master (CPHA = 1) Interface Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

(1)(2)

Table 37: SPI Slave Mode Interface Switching Characteristics

Symbol

T_SSPIDCK

Description

Min

1

Max

–

Units

Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS

Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS

Output delay for SPI{0,1}_MISO

F_{SPI_REF_CLK}cycles

MHz

T_SSPICKD

1

–

T_SSPICKO

0

2.6

–

T_SSPISSCLK

T_SSPICLKSS

F_SSPICLK

Slave select asserted to first active clock edge

Last active clock edge to slave select deasserted

SPI slave mode device clock frequency

SPI reference clock frequency

1

–

25

200

F_{SPI_REF_CLK}

–

MHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.

X-Ref Target - Figure 12

SPI{0,1}_SS

SPI{0,1}_CLK (CPOL=0)

SPI{0,1}_CLK (CPOL=1)

T

SSPISSCLK

T

SSPICLKSS

T

SSPICKD

Dn–1

T

SSPIDCK

Dn

Dn–2

T

Dn–3

D0

SPI{0,1}_MOSI

SPI{0,1}_MISO

SSPICKO

Dn

Dn–1

Dn–2

Dn–3

D0

DS187_12_021013

Figure 12: SPI Slave (CPHA = 0) Interface Timing Diagram

X-Ref Target - Figure 13

SPI{0,1}_SS

SPI{0,1}_CLK (CPOL=0)

T

SSPICLKSS

SSPISSCLK

SPI{0,1}_CLK (CPOL=1)

T

SSPICKD

T

SSPIDCK

Dn

Dn–1

Dn–2

T

Dn–3

D0

SPI{0,1}_MOSI

SPI{0,1}_MISO

SSPICKO

Dn

Dn–1

Dn–2

Dn–3

D0

DS187_13_021013

Figure 13: SPI Slave (CPHA = 1) Interface Timing Diagram

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

CAN Interfaces

(1)

Table 38: CAN Interface Switching Characteristics

Symbol

T_PWCANRX

T_PWCANTX

Description

Min

1

Max

–

Units

µs

Minimum receive pulse width

Minimum transmit pulse width

1

–

µs

Internally sourced CAN reference clock frequency

Externally sourced CAN reference clock frequency

–

100

40

MHz

F_{CAN_REF_CLK}

–

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

PJTAG Interfaces

(1)(2)

Table 39: PJTAG Interface

Symbol

T_PJTAGDCK

T_PJTAGCKD

T_PJTAGCKO

T_PJTAGCLK

Description

Min

2.4

2.0

–

Max

–

Units

ns

PJTAG input setup time

PJTAG input hold time

PJTAG clock to out delay

PJTAG clock frequency

–

ns

12.5

20

ns

–

MHz

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.

X-Ref Target - Figure 14

PJTAGCLK

T

PJTAGCKD

PJTAGDCK

PJTAGTMS, PJTAGTDI

T

PJTAGCKO

PJTAGTDO

DS187_14_021013

Figure 14: PJTAG Interface Timing Diagram

UART Interfaces

(1)

Table 40: UART Interface Switching Characteristics

Symbol

BAUD_TXMAX

BAUD_RXMAX

Description

Min

–

Max

Units

Mb/s

MHz

Maximum transmit baud rate

Maximum receive baud rate

1

–

F_{UART_REF_CLK}UART reference clock frequency

–

100

Notes:

1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

GPIO Interfaces

(1)

Table 41: GPIO Banks Switching Characteristics

Symbol Description

T_PWGPIOH

Min

Max

Units

µs

Input high pulse width

Input low pulse width

10 x 1/cpu1x

–

T_PWGPIOL

µs

Notes:

1. Pulse width requirement for interrupt.

X-Ref Target - Figure 15

T

PWGPIOL

PWGPIOH

GPIO

DS187_15_021013

Figure 15: GPIO Interface Timing Diagram

Trace Interface

(1)

Table 42: Trace Interface Switching Characteristics

Symbol

T_TCECKO

T_DCTCECLK

F_TCECLK

Description

Min

–1.4

40

Max

1.5

60

Units

ns

Trace clock to output delay, all outputs

Trace clock duty cycle

%

Trace clock frequency

–

80

MHz

Notes:

1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads.

Triple Timer Counter Interface

(1)

Table 43: Triple Timer Counter interface Switching Characteristics

Symbol

T_PWTTCOCLK

F_TTCOCLK

T_TTCICLKH

T_TTCICLKL

F_TTCICLK

Description

Triple time counter output clock pulse width

Triple time counter output clock frequency

Triple time counter input clock high pulse width

Triple time counter input clock low pulse width

Triple time counter input clock frequency

Min

Max

Units

ns

2 x 1/cpu1x

–

cpu1x/4

–

MHz

ns

1.5 x 1/cpu1x

–

ns

cpu1x/3

MHz

Notes:

1. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.

Watchdog Timer

Table 44: Watchdog Timer Switching Characteristics

Symbol

F_WDTCLK

Description

Watchdog timer input clock frequency

Min

Max

Units

–

10

MHz

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

PS-PL Interface

Table 45: PS-PL Interface Performance

Symbol

Description

Min

–

Typical

Max

125

25

Units

MHz

F_EMIOGEMCLK

F_EMIOSDCLK

F_EMIOSPICLK

F_EMIOJTAGCLK

F_EMIOTRACECLK

F_FTMCLK

EMIO gigabit Ethernet controller maximum frequency

EMIO SD controller maximum frequency

EMIO SPI controller maximum frequency

EMIO JTAG controller maximum frequency

EMIO trace controller maximum frequency

Fabric trace monitor maximum frequency

DMA maximum frequency

–

25

–

20

–

125

100

–

F_EMIODMACLK

–

PL Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in the PL. The

numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same

guidelines as the AC Switching Characteristics, page 11.

Table 46: PL Networking Applications Interface Performances

Speed Grade

Description

Units

-3

-2

-1

SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)

DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)

SDR LVDS receiver (SFI-4.1)⁽¹⁾

680

600

950

600

950

Mb/s

1250

680

1250

680

DDR LVDS receiver (SPI-4.2)⁽¹⁾

1250

Notes:

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate

deterministic performance.

(1)(2)

Table 47: PL Maximum Physical Interface (PHY) Rate for Memory Interfaces

Speed Grade

Memory Standard

Units

-3

-2

-1

4:1 Memory Controllers

DDR3

1066⁽³⁾

800

667

800

667

533

Mb/s

DDR3L

DDR2

800

LPDDR2

667

2:1 Memory Controllers

DDR3

DDR3L

DDR2

800

700

620

Mb/s

Notes:

1.

V

tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide.

REF

2. When using the internal V , the maximum data rate is 800 Mb/s (400 MHz).

REF

3. The maximum PHY rate is 800 Mb/s in bank 13 of the XC7Z020 device.

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28

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

PL Switching Characteristics

IOB Pad Input/Output/3-State

Table 48 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based

on standard), and 3-state delays.

•

T

is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies

IOPI

depending on the capability of the SelectIO input buffer.

T

is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies

IOOP

depending on the capability of the SelectIO output buffer.

T

is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is

IOTP

disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM

termination turn-on time is always faster than T when the INTERMDISABLE pin is used.

IOTP

Table 48: 3.3V IOB High Range (HR) Switching Characteristics

T_IOPI

T_IOOP

Speed Grade

-2

T_IOTP

Speed Grade

-2

I/O Standard

Speed Grade

-2

Units

-3

-1

-3

-1

-3

-1

LVTTL_S4

LVTTL_S8

LVTTL_S12

LVTTL_S16

LVTTL_S24

LVTTL_F4

LVTTL_F8

LVTTL_F12

LVTTL_F16

LVTTL_F24

LVDS_25

1.26

0.73

1.24

0.67

0.68

0.67

0.65

0.67

0.66

0.68

0.71

0.70

1.34

0.81

1.32

0.75

0.76

0.75

0.73

0.75

0.76

0.79

0.78

1.41

0.88

1.39

0.82

0.83

0.82

0.80

0.82

0.81

0.83

0.86

0.85

3.80

3.54

3.52

3.07

3.29

3.26

2.74

2.73

2.56

2.52

1.29

1.27

1.84

1.27

1.29

1.41

3.10

1.81

1.62

1.41

1.29

1.41

1.59

1.51

1.38

1.46

3.93

3.66

3.65

3.19

3.41

3.38

2.87

2.85

2.68

2.65

1.41

1.40

1.96

1.40

1.41

1.54

4.18

3.92

3.90

3.45

3.67

3.64

3.12

3.10

2.93

2.90

1.67

1.65

2.21

1.65

1.67

1.79

3.48

2.18

1.99

1.79

1.67

1.79

1.96

1.88

1.76

1.84

4.37

4.11

4.09

3.64

3.86

3.83

3.31

3.29

3.12

3.09

1.86

1.84

2.40

1.84

1.86

1.98

3.67

2.37

2.19

1.98

1.86

1.98

2.15

2.08

1.95

2.03

4.59

4.32

4.31

3.85

4.07

4.04

3.52

3.51

3.34

3.31

2.07

2.06

2.62

2.06

2.07

2.20

3.88

2.59

2.40

2.20

2.07

2.20

2.37

2.29

2.17

2.24

5.01

4.75

4.73

4.28

4.50

4.46

3.95

3.93

3.76

3.73

2.49

2.48

3.04

2.48

2.49

2.62

4.31

3.01

2.82

2.62

2.49

2.62

2.79

2.71

2.59

2.67

ns

MINI_LVDS_25

BLVDS_25

RSDS_25 (point to point)

PPDS_25

TMDS_33

PCI33_3

3.22

1.93

1.74

1.54

1.41

1.54

1.71

1.63

1.51

1.58

HSUL_12

DIFF_HSUL_12

HSTL_I_S

HSTL_II_S

HSTL_I_18_S

HSTL_II_18_S

DIFF_HSTL_I_S

DIFF_HSTL_II_S

DIFF_HSTL_I_18_S

DIFF_HSTL_II_18_S

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

29

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 48: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

-2

T_IOOP

Speed Grade

-2

T_IOTP

Speed Grade

-2

I/O Standard

Units

-3

-1

-3

-1

-3

-1

HSTL_I_F

0.67

0.65

0.67

0.66

0.68

0.71

0.70

1.26

1.12

0.74

0.77

0.75

0.73

0.75

0.76

0.79

0.78

1.34

1.20

0.83

0.86

0.82

0.80

0.82

0.81

0.83

0.86

0.85

1.41

1.27

0.89

0.93

1.10

1.12

1.13

1.12

1.18

1.21

3.80

3.52

3.09

3.40

3.26

2.74

2.56

3.13

2.88

2.48

2.82

2.74

2.18

2.16

2.01

1.62

2.18

1.52

1.60

1.45

1.68

1.40

1.34

2.05

2.09

1.59

1.22

1.24

1.26

1.24

1.30

1.33

3.93

3.65

3.21

3.52

3.38

2.87

2.68

3.26

3.01

2.60

2.94

2.87

2.30

2.29

2.13

1.74

2.30

1.65

1.72

1.57

1.80

1.52

1.46

2.18

2.21

1.71

1.48

1.49

1.51

1.49

1.56

1.59

4.18

3.90

3.46

3.77

3.64

3.12

2.93

3.51

3.26

2.85

3.20

3.12

2.56

2.54

2.39

1.99

2.56

1.90

1.98

1.82

2.06

1.77

1.71

2.43

2.46

1.96

1.67

1.69

1.70

1.69

1.75

1.78

4.37

4.09

3.65

3.97

3.83

3.31

3.12

3.70

3.45

3.05

3.39

3.31

2.75

2.73

2.58

2.19

2.75

2.09

2.17

2.01

2.25

1.97

1.90

2.62

2.65

2.15

1.88

1.90

1.92

1.90

1.96

1.99

4.59

4.31

3.87

4.18

4.04

3.52

3.34

3.91

3.67

3.26

3.60

3.52

2.96

2.95

2.79

2.40

2.96

2.31

2.38

2.23

2.46

2.18

2.12

2.84

2.87

2.37

2.31

2.32

2.34

2.32

2.39

2.42

5.01

4.73

4.29

4.60

4.46

3.95

3.76

4.34

4.09

3.68

4.03

3.95

3.39

3.37

3.21

2.82

3.39

2.73

2.81

2.65

2.89

2.60

2.54

3.26

3.29

2.79

ns

HSTL_II_F

HSTL_I_18_F

HSTL_II_18_F

DIFF_HSTL_I_F

DIFF_HSTL_II_F

DIFF_HSTL_I_18_F

DIFF_HSTL_II_18_F

LVCMOS33_S4

LVCMOS33_S8

LVCMOS33_S12

LVCMOS33_S16

LVCMOS33_F4

LVCMOS33_F8

LVCMOS33_F12

LVCMOS33_F16

LVCMOS25_S4

LVCMOS25_S8

LVCMOS25_S12

LVCMOS25_S16

LVCMOS25_F4

LVCMOS25_F8

LVCMOS25_F12

LVCMOS25_F16

LVCMOS18_S4

LVCMOS18_S8

LVCMOS18_S12

LVCMOS18_S16

LVCMOS18_S24

LVCMOS18_F4

LVCMOS18_F8

LVCMOS18_F12

LVCMOS18_F16

LVCMOS18_F24

LVCMOS15_S4

LVCMOS15_S8

LVCMOS15_S12

LVCMOS15_S16

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

30

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 48: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T_IOPI

Speed Grade

-2

T_IOOP

Speed Grade

-2

T_IOTP

Speed Grade

-2

I/O Standard

Units

-3

-1

-3

-1

-3

-1

LVCMOS15_F4

0.77

0.87

0.67

0.60

0.67

0.68

0.71

0.67

0.60

0.67

0.68

0.71

0.86

0.93

1.02

0.82

0.75

0.82

0.83

0.86

0.82

0.75

0.82

0.83

0.86

1.85

1.60

1.35

1.34

2.57

2.09

1.79

1.98

1.54

1.38

1.35

1.30

1.67

1.31

1.35

1.30

1.68

1.38

1.12

1.07

1.12

1.07

1.23

1.21

1.97

2.23

1.98

1.73

1.71

2.95

2.46

2.17

2.35

1.92

1.76

1.73

1.68

2.04

1.68

1.73

1.68

2.06

1.76

1.49

1.45

1.49

1.45

1.60

1.59

2.42

2.17

1.92

1.90

3.14

2.65

2.36

2.54

2.11

1.95

1.92

1.87

2.23

1.87

1.92

1.87

2.25

1.95

1.69

1.64

1.69

1.64

1.79

1.78

2.63

3.06

2.81

2.56

2.54

3.78

3.29

2.99

3.18

2.75

2.59

2.56

2.51

2.87

2.51

2.56

2.51

2.89

2.59

2.32

2.28

2.32

2.28

2.43

2.42

ns

LVCMOS15_F8

LVCMOS15_F12

LVCMOS15_F16

LVCMOS12_S4

LVCMOS12_S8

LVCMOS12_S12

LVCMOS12_F4

LVCMOS12_F8

LVCMOS12_F12

SSTL135_S

1.72

2.38

1.47

2.13

0.86

1.46

2.12

0.95

2.69

3.35

2.21

2.87

1.91

2.57

0.95

2.10

2.76

1.66

2.32

1.51

2.16

0.75

0.68

0.75

1.47

2.13

SSTL15_S

1.43

2.09

SSTL18_I_S

1.79

2.45

SSTL18_II_S

1.43

2.09

DIFF_SSTL135_S

DIFF_SSTL15_S

DIFF_SSTL18_I_S

DIFF_SSTL18_II_S

SSTL135_F

0.76

0.79

1.47

2.13

1.43

2.09

1.80

2.46

1.51

2.17

0.75

0.68

0.75

1.24

1.90

SSTL15_F

1.19

1.85

SSTL18_I_F

1.24

1.90

SSTL18_II_F

1.24

1.90

DIFF_SSTL135_F

DIFF_SSTL15_F

DIFF_SSTL18_I_F

DIFF_SSTL18_II_F

0.76

0.79

1.24

1.90

1.19

1.85

1.35

2.01

1.33

1.99

Table 49 specifies the values of T

and T

. T

is described as the delay from the T pin to the IOB pad

IOTPHZ

IOIBUFDISABLE IOTPHZ

through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T

is described

IOIBUFDISABLE

as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always

faster than T when the INTERMDISABLE pin is used.

IOTPHZ

Table 49: IOB 3-state Output Switching Characteristics

Symbol Description

Speed Grade

Units

-3

-2

-1

T_IOTPHZ

T_{IOIBUFDISABLE}

T input to pad high-impedance

IBUF turn-on time from IBUFDISABLE to O output

2.06

2.11

2.19

2.30

2.37

2.60

ns

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

31

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Input/Output Logic Switching Characteristics

Table 50: ILOGIC Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Setup/Hold

T_ICE1CK/T_ICKCE1

T_ISRCK/T_ICKSR

_IDOCK/T_IOCKD

CE1 pin setup/hold with respect to CLK

SR pin setup/hold with respect to CLK

0.48/0.02 0.54/0.02 0.76/0.02

0.60/0.01 0.70/0.01 1.13/0.01

0.01/0.27 0.01/0.29 0.01/0.33

0.02/0.27 0.02/0.29 0.02/0.33

ns

T

D pin setup/hold with respect to CLK without Delay

T_IDOCKD/T_IOCKDDDDLY pin setup/hold with respect to CLK (using IDELAY)

Combinatorial

T_IDI

D pin to O pin propagation delay, no Delay

0.11

0.12

0.13

0.14

ns

T_IDID

DDLY pin to O pin propagation delay (using IDELAY)

Sequential Delays

T_IDLO

D pin to Q1 pin using flip-flop as a latch without Delay

DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)

CLK to Q outputs

0.41

0.53

0.96

7.60

0.44

0.57

1.08

7.60

0.51

0.66

1.32

10.51

ns

T_IDLOD

T_ICKQ

T_{RQ_ILOGIC}

T_{GSRQ_ILOGIC}

Set/Reset

T_{RPW_ILOGIC}

SR pin to OQ/TQ out

Global set/reset to Q outputs

Minimum pulse width, SR inputs

0.61

0.72

ns, Min

Table 51: OLOGIC Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Setup/Hold

T

_ODCK/T_OCKD

D1/D2 pins setup/hold with respect to CLK

0.67/–0.11 0.71/–0.11 0.84/–0.11

0.32/0.58 0.34/0.58 0.51/0.58

0.37/0.21 0.44/0.21 0.80/0.21

0.69/–0.14 0.73/–0.14 0.89/–0.14

0.32/0.01 0.34/0.01 0.51/0.01

ns

T_OOCECK/T_OCKOCEOCE pin setup/hold with respect to CLK

T_OSRCK/T_OCKSR

_OTCK/T_OCKT

SR pin setup/hold with respect to CLK

T

T1/T2 pins setup/hold with respect to CLK

T_OTCECK/T_OCKTCETCE pin setup/hold with respect to CLK

Combinatorial

T_ODQ

D1 to OQ out or T1 to TQ out

0.83

0.96

1.16

ns

Sequential Delays

T_OCKQ

CLK to OQ/TQ out

0.47

0.72

7.60

0.49

0.80

7.60

0.56

0.95

ns

T_{RQ_OLOGIC}

T_{GSRQ_OLOGIC}

Set/Reset

SR pin to OQ/TQ out

Global set/reset to Q outputs

10.51

T_{RPW_OLOGIC}

Minimum pulse width, SR inputs

0.64

0.74

ns, Min

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

32

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Input Serializer/Deserializer Switching Characteristics

Table 52: ISERDES Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-2

-1

Setup/Hold for Control Lines

T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP}

BITSLIP pin setup/hold with respect to CLKDIV

CE pin setup/hold with respect to CLK (for CE1)

0.01/0.14 0.02/0.15 0.02/0.17

0.45/–0.01 0.50/–0.01 0.72/–0.01

–0.10/0.33 –0.10/0.36 –0.10/0.40

ns

(2)

T_{ISCCK_CE}/ T_{ISCKC_CE}

(2)

T

_{ISCCK_CE2}/ T_{ISCKC_CE2}

CE pin setup/hold with respect to CLKDIV (for

CE2)

Setup/Hold for Data Lines

_{ISDCK_D}/T_{ISCKD_D}

T

D pin setup/hold with respect to CLK

–0.02/0.12 –0.02/0.14 –0.02/0.17

ns

T_{ISDCK_DDLY}/T_{ISCKD_DDLY}

DDLY pin setup/hold with respect to CLK (using

IDELAY)⁽¹⁾

T_{ISDCK_D_DDR}/T_{ISCKD_D_DDR}

D pin setup/hold with respect to CLK at DDR

mode

–0.02/0.12 –0.02/0.14 –0.02/0.17

0.12/0.12 0.14/0.14 0.17/0.17

ns

T

_{ISDCK_DDLY_DDR}/ T_{ISCKD_DDLY_DDR}D pin setup/hold with respect to CLK at DDR

mode (using IDELAY)⁽¹⁾

Sequential Delays

T_{ISCKO_Q}

CLKDIV to out at Q pin

D input to DO output pin

0.53

0.11

0.54

0.11

0.66

0.13

ns

Propagation Delays

T_{ISDO_DO}

Notes:

1. Recorded at 0 tap value.

2.

T

and T

are reported as T

/T

in TRACE report.

ISCCK_CE2

ISCKC_CE2

ISCCK_CE ISCKC_CE

Output Serializer/Deserializer Switching Characteristics

Table 53: OSERDES Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Setup/Hold

_{OSDCK_D}/T_{OSCKD_D}

T

D input setup/hold with respect to CLKDIV

T input setup/hold with respect to CLK

T input setup/hold with respect to CLKDIV

OCE input setup/hold with respect to CLK

SR (reset) input setup with respect to CLKDIV

TCE input setup/hold with respect to CLK

0.42/0.03 0.45/0.03 0.63/0.03

0.69/–0.13 0.73/–0.13 0.88/–0.13

0.31/–0.13 0.34/–0.13 0.39/–0.13

0.32/0.58 0.34/0.58 0.51/0.58

ns

(1)

T_{OSDCK_T}/T_{OSCKD_T}

(1)

T_{OSDCK_T2}/T_{OSCKD_T2}

_{OSCCK_OCE}/T_{OSCKC_OCE}

T

T_{OSCCK_S}

0.47

0.52

0.85

T_{OSCCK_TCE}/T_{OSCKC_TCE}

Sequential Delays

T_{OSCKO_OQ}

0.32/0.01 0.34/0.01 0.51/0.01

Clock to out from CLK to OQ

Clock to out from CLK to TQ

0.40

0.47

0.42

0.49

0.48

0.56

ns

T_{OSCKO_TQ}

Combinatorial

T_{OSDO_TTQ}

T input to TQ out

0.83

0.92

1.11

ns

Notes:

1.

T

and T

are reported as T

/T

in TRACE report.

OSDCK_T2

OSCKD_T2

OSDCK_T OSCKD_T

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Preliminary Product Specification

33

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Input Delay Switching Characteristics

Table 54: Input Delay Switching Characteristics

Symbol Description

IDELAYCTRL

Speed Grade

-2

Units

-3

-1

T_{DLYCCO_RDY}

Reset to ready for IDELAYCTRL

Attribute REFCLK frequency = 200.0⁽¹⁾

Attribute REFCLK frequency = 300.0⁽¹⁾

REFCLK precision

3.67

200

3.67

200

3.67

200

N/A

µs

F_{IDELAYCTRL_REF}

MHz

ns

300

IDELAYCTRL_REF_PRECISION

T_{IDELAYCTRL_RPW}

IDELAY

10

Minimum reset pulse width

59.28

T_{IDELAYRESOLUTION}

IDELAY chain delay resolution

1/(32 x 2 x F_REF

)

ps

Pattern dependent period jitter in delay chain for

clock pattern.⁽²⁾

0

ps per tap

Pattern dependent period jitter in delay chain for

random data pattern (PRBS 23)⁽³⁾

5

9

5

9

5

9

ps per tap

T_{IDELAYPAT_JIT}

Pattern dependent period jitter in delay chain for

random data pattern (PRBS 23)⁽⁴⁾

T_{IDELAY_CLK_MAX}

Maximum frequency of CLK input to IDELAY

CE pin setup/hold with respect to C for IDELAY

INC pin setup/hold with respect to C for IDELAY

RST pin setup/hold with respect to C for IDELAY

Propagation delay through IDELAY

680.00

600.00

MHz

ns

T

_{IDCCK_CE}/ T_{IDCKC_CE}

T_{IDCCK_INC}/ T_{IDCKC_INC}

_{IDCCK_RST}/ T_{IDCKC_RST}

0.12/0.11 0.16/0.13 0.21/0.16

0.12/0.16 0.14/0.18 0.16/0.22

0.15/0.09 0.16/0.11 0.18/0.14

ns

T

ns

T_{IDDO_IDATAIN}

Note 5

ps

Notes:

1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.

3. When HIGH_PERFORMANCE mode is set to TRUE.

4. When HIGH_PERFORMANCE mode is set to FALSE.

5. Delay depends on IDELAY tap setting. See TRACE report for actual values.

Table 55: IO_FIFO Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

IO_FIFO Clock to Out Delays

T_{OFFCKO_DO}

RDCLK to Q outputs

0.55

0.60

0.61

0.68

0.77

ns

T_{CKO_FLAGS}

Clock to IO_FIFO flags

Setup/Hold

T_{CCK_D}/T_{CKC_D}

D inputs to WRCLK

WREN to WRCLK

RDEN to RDCLK

0.47/0.02 0.51/0.02 0.58/0.02

0.42/–0.01 0.47/–0.01 0.53/–0.01

0.53/0.02 0.58/0.02 0.66/0.02

ns

T

_{IFFCCK_WREN}/T_{IFFCKC_WREN}

T_{OFFCCK_RDEN}/T_{OFFCKC_RDEN}

Minimum Pulse Width

T_{PWH_IO_FIFO}

RESET, RDCLK, WRCLK

1.62

2.15

ns

T_{PWL_IO_FIFO}

Maximum Frequency

F_MAX

RDCLK and WRCLK

266.67

200.00

MHz

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Preliminary Product Specification

34

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

CLB Switching Characteristics

Table 56: CLB Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Combinatorial Delays

T_ILO

An – Dn LUT address to A

0.10

0.27

0.42

0.94

0.62

0.58

0.60

0.68

0.51

0.62

0.42

0.53

0.52

0.11

0.30

0.46

1.05

0.69

0.66

0.68

0.75

0.57

0.69

0.48

0.59

0.58

0.13

0.36

0.55

1.27

0.84

0.83

0.82

0.90

0.69

0.82

0.58

0.71

0.70

ns, Max

T_{ILO_2}

T_{ILO_3}

T_ITO

An – Dn LUT address to AMUX/CMUX

An – Dn LUT address to BMUX_A

An – Dn inputs to A – D Q outputs

AX inputs to AMUX output

AX inputs to BMUX output

AX inputs to CMUX output

AX inputs to DMUX output

BX inputs to BMUX output

BX inputs to DMUX output

CX inputs to CMUX output

CX inputs to DMUX output

DX inputs to DMUX output

T_AXA

T_AXB

T_AXC

T_AXD

T_BXB

T_BXD

T_CXC

T_CXD

T_DXD

Sequential Delays

T_CKO

Clock to AQ – DQ outputs

0.40

0.47

0.44

0.53

0.66

ns, Max

T_SHCKO

Clock to AMUX – DMUX outputs

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

T_AS/T_AH

A_N– D_Ninput to CLK on A – D flip-flops

A_X– D_Xinput to CLK on A – D flip-flops

0.07/0.12 0.09/0.14 0.11/0.18 ns, Min

0.06/0.19 0.07/0.21 0.09/0.26 ns, Min

0.59/0.08 0.66/0.09 0.81/0.11 ns, Min

T_DICK/T_CKDI

A_X– D_Xinput through MUXs and/or carry logic to CLK on

A – D flip-flops

T

_{CECK_CLB}/T_{CKCE_CLB}CE input to CLK on A – D flip-flops

0.15/0.00 0.17/0.00 0.21/0.01 ns, Min

0.38/0.03 0.43/0.04 0.53/0.05 ns, Min

T_SRCK/T_CKSR

Set/Reset

T_SRMIN

T_RQ

SR input to CLK on A – D flip-flops

SR input minimum pulse width

0.52

0.53

0.52

1412

0.78

0.59

0.58

1286

1.04

0.71

0.70

1098

ns, Min

ns, Max

MHz

Delay from SR input to AQ – DQ flip-flops

Delay from CE input to AQ – DQ flip-flops

Toggle frequency (for export control)

T_CEO

F_TOG

Notes:

1. A Zero “0” hold time listing indicates no hold time or a negative hold time.

2. These items are of interest for carry-chain applications.

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Preliminary Product Specification

35

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 57: CLB Distributed RAM Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-2

-1

Sequential Delays

T_SHCKO

Clock to A – B outputs

Clock to AMUX – BMUX outputs

0.98

1.37

1.09

1.53

1.32

1.86

ns, Max

T_{SHCKO_1}

Setup and Hold Times Before/After Clock CLK

T

_{DS_LRAM}/T_{DH_LRAM}

A – D inputs to CLK

0.54/0.28 0.60/0.30 0.72/0.35 ns, Min

0.27/0.55 0.30/0.60 0.37/0.70 ns, Min

T_{AS_LRAM}/T_{AH_LRAM}

Address An inputs to clock

Address An inputs through MUXs and/or carry logic to clock 0.69/0.18 0.77/0.21 0.94/0.26 ns, Min

T

_{WS_LRAM}/T_{WH_LRAM}

WE input to clock

0.38/0.10 0.43/0.12 0.53/0.17 ns, Min

0.39/0.10 0.44/0.11 0.53/0.17 ns, Min

T_{CECK_LRAM}/T_{CKCE_LRAM}CE input to CLK

Clock CLK

T_{MPW_LRAM}

T_MCP

Minimum pulse width

Minimum clock period

1.05

2.10

1.13

2.26

1.25

2.50

ns, Min

Notes:

1. A Zero “0” hold time listing indicates no hold time or a negative hold time.

2. also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.

T

SHCKO

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 58: CLB Shift Register Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Sequential Delays

T_REG

Clock to A – D outputs

ns, Max

1.19

1.58

1.12

1.33

1.77

1.23

1.61

2.15

1.46

T_{REG_MUX}

T_{REG_M31}

Clock to AMUX – DMUX output

Clock to DMUX output via M31 output

Setup and Hold Times Before/After Clock CLK

T_{WS_SHFREG}/T_{WH_SHFREG}WE input

T_{CECK_SHFREG}/T_{CKCE_SHFREG}CE input to CLK

0.37/0.10 0.41/0.12 0.51/0.17

0.37/0.10 0.42/0.11 0.52/0.17

0.33/0.34 0.37/0.37 0.44/0.43

ns, Min

T_{DS_SHFREG}/T_{DH_SHFREG}

Clock CLK

A – D inputs to CLK

T_{MPW_SHFREG}

Minimum pulse width

ns, Min

0.77

0.86

0.98

Notes:

1. A Zero “0” hold time listing indicates no hold time or a negative hold time.

DS187 (v1.3) February 11, 2013

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Preliminary Product Specification

36

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Block RAM and FIFO Switching Characteristics

Table 59: Block RAM and FIFO Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Block RAM and FIFO Clock to Out Delays

T_{RCKO_DO}and

T_{RCKO_DO_REG}

Clock CLK to DOUT output (without output

register)⁽²⁾⁽³⁾

1.85

0.64

2.77

0.73

2.61

1.16

2.13

0.74

3.04

0.81

2.88

1.28

2.46

0.89

3.84

0.94

3.30

1.46

ns, Max

(1)

Clock CLK to DOUT output (with output

register)⁽⁴⁾⁽⁵⁾

T

_{RCKO_DO_ECC}and

Clock CLK to DOUT output with ECC (without

output register)⁽²⁾⁽³⁾

T_{RCKO_DO_ECC_REG}

Clock CLK to DOUT output with ECC (with output

register)⁽⁴⁾⁽⁵⁾

T_{RCKO_DO_CASCOUT}and

T_{RCKO_DO_CASCOUT_REG}

Clock CLK to DOUT output with cascade (without

output register)⁽²⁾

Clock CLK to DOUT output with cascade (with

output register)⁽⁴⁾

T_{RCKO_FLAGS}

Clock CLK to FIFO flags outputs⁽⁶⁾

Clock CLK to FIFO pointers outputs⁽⁷⁾

0.76

0.94

0.78

0.87

1.02

0.85

1.05

1.15

0.94

ns, Max

T_{RCKO_POINTERS}

T_{RCKO_PARITY_ECC}

Clock CLK to ECCPARITY in ECC encode only

mode

T

_{RCKO_SDBIT_ECC}and

Clock CLK to BITERR (without output register)

Clock CLK to BITERR (with output register)

2.56

0.68

0.75

2.81

0.76

0.88

3.55

0.89

1.07

ns, Max

T_{RCKO_SDBIT_ECC_REG}

T

_{RCKO_RDADDR_ECC}and

Clock CLK to RDADDR output with ECC (without

output register)

T_{RCKO_RDADDR_ECC_REG}

Clock CLK to RDADDR output with ECC

(with output register)

0.84

0.93

1.08

ns, Max

Setup and Hold Times Before/After Clock CLK

T

_{RCCK_ADDRA}/T_{RCKC_ADDRA}

ADDR inputs⁽⁸⁾

0.45/0.31 0.49/0.33 0.57/0.36 ns, Min

0.58/0.60 0.65/0.63 0.74/0.67 ns, Min

T_{RDCK_DI_WF_NC}

T_{RCKD_DI_WF_NC}

/

Data input setup/hold time when block RAM is

configured in WRITE_FIRST or NO_CHANGE

mode⁽⁹⁾

T_{RDCK_DI_RF}/T_{RCKD_DI_RF}

Data input setup/hold time when block RAM is

configured in READ_FIRST mode⁽⁹⁾

0.20/0.29 0.22/0.34 0.25/0.41 ns, Min

0.50/0.43 0.55/0.46 0.63/0.50 ns, Min

T_{RDCK_DI_ECC}/T_{RCKD_DI_ECC}

DIN inputs with block RAM ECC in standard

mode⁽⁹⁾

DIN inputs with block RAM ECC encode only⁽⁹⁾

DIN inputs with FIFO ECC in standard mode⁽⁹⁾

Inject single/double bit error in ECC mode

0.93/0.43 1.02/0.46 1.17/0.50 ns, Min

1.04/0.56 1.15/0.59 1.32/0.64 ns, Min

0.58/0.35 0.64/0.37 0.74/0.40 ns, Min

T_{RCCK_INJECTBITERR}

/

T_{RCKC_INJECTBITERR}

T_{RCCK_RDEN}/T_{RCKC_RDEN}

Block RAM enable (EN) input

CE input of output register

Synchronous RSTREG input

Synchronous RSTRAM input

Write enable (WE) input (block RAM only)

WREN FIFO inputs

0.35/0.20 0.39/0.21 0.45/0.23 ns, Min

0.24/0.15 0.29/0.15 0.36/0.16 ns, Min

0.29/0.07 0.32/0.07 0.35/0.07 ns, Min

0.32/0.42 0.34/0.43 0.36/0.46 ns, Min

0.44/0.18 0.48/0.19 0.54/0.20 ns, Min

0.46/0.30 0.46/0.35 0.47/0.43 ns, Min

0.42/0.30 0.43/0.35 0.43/0.43 ns, Min

T_{RCCK_REGCE}/T_{RCKC_REGCE}

T

_{RCCK_RSTREG}/T_{RCKC_RSTREG}

T_{RCCK_RSTRAM}/T_{RCKC_RSTRAM}

_{RCCK_WEA}/T_{RCKC_WEA}

T_{RCCK_WREN}/T_{RCKC_WREN}

T_{RCCK_RDEN}/T_{RCKC_RDEN}

T

RDEN FIFO inputs

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Preliminary Product Specification

37

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 59: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade

-2

Symbol

Description

Units

-3

-1

Reset Delays

T_{RCO_FLAGS}

Reset RST to FIFO flags/pointers⁽¹⁰⁾

0.90

0.98

1.10

ns, Max

T_{RREC_RST}/T_{RREM_RST}

Maximum Frequency

F_{MAX_BRAM_WF_NC}

FIFO reset recovery and removal timing⁽¹¹⁾

1.87/–0.81 2.07/–0.81 2.37/–0.81 ns, Max

Block RAM (write first and no change modes)

When not in SDP RF mode.

509.68

460.83

388.20

MHz

F_{MAX_BRAM_RF_PERFORMANCE}

Block RAM (read first, performance mode)

When in SDP RF mode but no address overlap

between port A and port B.

F_{MAX_BRAM_RF_DELAYED_WRITE}

Block RAM (read first, delayed write mode)

447.63

404.53

339.67

MHz

When in SDP RF mode and there is possibility of

overlap between port A and port B addresses.

F_{MAX_CAS_WF_NC}

Block RAM cascade (write first, no change mode)

When cascade but not in RF mode.

467.07

418.59

345.78

MHz

F_{MAX_CAS_RF_PERFORMANCE}

Block RAM cascade

(read first, performance mode)

When in cascade with RF mode and no possibility

of address overlap/one port is disabled.

F_{MAX_CAS_RF_DELAYED_WRITE}

When in cascade RF mode and there is a

possibility of address overlap between port A and

port B.

405.35

362.19

297.35

MHz

F_{MAX_FIFO}

F_{MAX_ECC}

FIFO in all modes without ECC

509.68

410.34

460.83

365.10

388.20

297.53

MHz

Block RAM and FIFO in ECC configuration

Notes:

1. TRACE will report all of these parameters as T

.

RCKO_DO

2.

3. These parameters also apply to synchronous FIFO with DO_REG = 0.

4. includes T as well as the B port equivalent timing parameters.

5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.

T

includes T

, T

, and T

as well as the B port equivalent timing parameters.

RCKO_DOR

RCKO_DOW RCKO_DOPR

RCKO_DOPW

T

RCKO_DO

RCKO_DOP

6.

T

includes the following parameters: T

RCKO_WRERR.

, T

, and

RCKO_FLAGS

RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR

7.

T

includes both T

and T

RCKO_POINTERS

RCKO_RDCOUNT RCKO_WRCOUNT.

8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is

possible.

9. These parameters include both A and B inputs as well as the parity inputs of A and B.

10. T

includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

RCO_FLAGS

11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the

slowest clock (WRCLK or RDCLK).

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Preliminary Product Specification

38

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

DSP48E1 Switching Characteristics

Table 60: DSP48E1 Switching Characteristics

Speed Grade

-2

Symbol

Description

Units

-3

-1

Setup and Hold Times of Data/Control Pins to the Input Register Clock

A input to A register CLK

B input to B register CLK

C input to C register CLK

D input to D register CLK

ACIN input to A register CLK

BCIN input to B register CLK

0.26/0.12 0.30/0.13 0.37/0.14

0.33/0.15 0.38/0.16 0.45/0.18

0.17/0.17 0.20/0.19 0.24/0.21

0.25/0.25 0.32/0.27 0.42/0.27

0.23/0.12 0.27/0.13 0.32/0.14

0.25/0.15 0.29/0.16 0.36/0.18

ns

T

/ T

DSPDCK_A_AREG DSPCKD_A_AREG

/T

DSPDCK_B_BREG DSPCKD_B_BREG

/T

DSPDCK_C_CREG DSPCKD_C_CREG

/T

DSPDCK_D_DREG DSPCKD_D_DREG

/T

DSPDCK_ACIN_AREG DSPCKD_ACIN_AREG

/T

DSPDCK_BCIN_BREG DSPCKD_BCIN_BREG

Setup and Hold Times of Data Pins to the Pipeline Register Clock

T_{DSPDCK_ A, B _MREG_MULT}

/

{A, B,} input to M register CLK using

multiplier

2.40/–0.01 2.76/–0.01 3.29/–0.01

1.29/–0.02 1.48/–0.02 1.76/–0.02

ns

{

}

T_{DSPCKD_B_MREG_MULT}

T_{DSPDCK_ A, B _ADREG}/ T_{DSPCKD_ D_ADREG}

{A, D} input to AD register CLK

{

}

Setup and Hold Times of Data/Control Pins to the Output Register Clock

{A, B} input to P register CLK using

multiplier

4.02/–0.28 4.60/–0.28 5.48/–0.28

ns

T

/

A, B

DSPDCK_{

DSPCKD_{

}_PREG_MULT

} _PREG_MULT

D input to P register CLK using multiplier 3.93/–0.73 4.50/–0.73 5.35/–0.73

T

/

DSPDCK_D_PREG_MULT

DSPCKD_D_PREG_MULT

A or B input to P register CLK not using 1.73/–0.28 1.98/–0.28 2.35/–0.28

multiplier

T

/

A, B

DSPDCK_{

DSPCKD_{

} _PREG

C input to P register CLK not using

multiplier

1.54/–0.26 1.76/–0.26 2.10/–0.26

T

/

DSPDCK_C_PREG

DSPCKD_C_PREG

T_{DSPDCK_PCIN_PREG}

T_{DSPCKD_PCIN_PREG}

/

PCIN input to P register CLK

1.32/–0.15 1.51/–0.15 1.80/–0.15

Setup and Hold Times of the CE Pins

{CEA; CEB} input to {A; B} register CLK 0.35/0.06 0.42/0.08 0.52/0.11

ns

T

/

DSPDCK_{CEA;CEB}_{AREG;BREG}

DSPCKD_{CEA;CEB}_{AREG;BREG}

CEC input to C register CLK

CED input to D register CLK

CEM input to M register CLK

0.28/0.10 0.34/0.11 0.42/0.13

0.36/–0.03 0.43/–0.03 0.52/–0.03

0.17/0.18 0.21/0.20 0.27/0.23

ns

T

/ T

DSPDCK_CEC_CREG DSPCKD_CEC_CREG

/ T

DSPDCK_CED_DREG DSPCKD_CED_DREG

T

/

DSPDCK_CEM_MREG

DSPCKD_CEM_MREG

CEP input to P register CLK

0.36/0.01 0.43/0.01 0.53/0.01

ns

T

/ T

DSPDCK_CEP_PREG DSPCKD_CEP_PREG

Setup and Hold Times of the RST Pins

{RSTA, RSTB} input to {A, B} register

CLK

0.41/0.11 0.46/0.13 0.55/0.15

0.07/0.10 0.08/0.11 0.09/0.12

0.44/0.07 0.50/0.08 0.59/0.09

0.21/0.22 0.23/0.24 0.27/0.28

0.27/0.01 0.30/0.01 0.35/0.01

ns

T

/

DSPDCK_{RSTA; RSTB}_{AREG; BREG}

DSPCKD_{RSTA; RSTB}_{AREG; BREG}

RSTC input to C register CLK

RSTD input to D register CLK

RSTM input to M register CLK

RSTP input to P register CLK

T

/

DSPDCK_RSTC_CREG

DSPCKD_RSTC_CREG

T

/

DSPDCK_RSTD_DREG

DSPCKD_RSTD_DREG

T

/

DSPDCK_RSTM_MREG

DSPCKD_RSTM_MREG

T

/

DSPDCK_RSTP_PREG

DSPCKD_RSTP_PREG

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Preliminary Product Specification

39

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 60: DSP48E1 Switching Characteristics (Cont’d)

Speed Grade

-2

Symbol

Description

Units

-3

-1

Combinatorial Delays from Input Pins to Output Pins

T_{DSPDO_A_CARRYOUT_MULT}

A input to CARRYOUT output using

multiplier

3.79

4.35

5.18

ns

T_{DSPDO_D_P_MULT}

T_{DSPDO_B_P}

D input to P output using multiplier

B input to P output not using multiplier

C input to P output

3.72

1.53

1.33

4.26

1.75

1.53

5.07

2.08

1.82

ns

T_{DSPDO_C_P}

Combinatorial Delays from Input Pins to Cascading Output Pins

T_{DSPDO_{A; B}_{ACOUT; BCOUT}}

{A, B} input to {ACOUT, BCOUT} output

0.55

4.06

0.63

4.65

0.74

5.54

ns

T_{DSPDO_{A, B}_CARRYCASCOUT_MULT}

{A, B} input to CARRYCASCOUT output

using multiplier

T_{DSPDO_D_CARRYCASCOUT_MULT}

T_{DSPDO_{A, B}_CARRYCASCOUT}

T_{DSPDO_C_CARRYCASCOUT}

D input to CARRYCASCOUT output

using multiplier

3.97

1.77

1.58

4.54

2.03

1.81

5.40

2.41

2.15

ns

{A, B} input to CARRYCASCOUT output

not using multiplier

C input to CARRYCASCOUT output

Combinatorial Delays from Cascading Input Pins to All Output Pins

T_{DSPDO_ACIN_P_MULT}ACIN input to P output using multiplier

T_{DSPDO_ACIN_P}

3.65

1.37

4.19

1.57

5.00

1.88

ns

ACIN input to P output not using

multiplier

T_{DSPDO_ACIN_ACOUT}

ACIN input to ACOUT output

0.38

3.90

0.44

4.47

0.53

5.33

ns

T_{DSPDO_ACIN_CARRYCASCOUT_MULT}

ACIN input to CARRYCASCOUT output

using multiplier

T_{DSPDO_ACIN_CARRYCASCOUT}

ACIN input to CARRYCASCOUT output

not using multiplier

1.61

1.85

2.21

ns

T_{DSPDO_PCIN_P}

PCIN input to P output

1.11

1.36

1.28

1.56

1.52

1.85

ns

T_{DSPDO_PCIN_CARRYCASCOUT}

PCIN input to CARRYCASCOUT output

Clock to Outs from Output Register Clock to Output Pins

T_{DSPCKO_P_PREG}

CLK PREG to P output

CLK PREG to CARRYCASCOUT output

0.33

0.52

0.37

0.59

0.44

0.69

ns

T_{DSPCKO_CARRYCASCOUT_PREG}

Clock to Outs from Pipeline Register Clock to Output Pins

T_{DSPCKO_P_MREG}

CLK MREG to P output

1.68

1.92

2.72

2.96

1.93

2.21

3.10

3.38

2.31

2.64

3.69

4.02

ns

T_{DSPCKO_CARRYCASCOUT_MREG}

T_{DSPCKO_P_ADREG_MULT}

CLK MREG to CARRYCASCOUT output

CLK ADREG to P output using multiplier

T_{DSPCKO_CARRYCASCOUT_ADREG_MULT}

CLK ADREG to CARRYCASCOUT

output using multiplier

Clock to Outs from Input Register Clock to Output Pins

T_{DSPCKO_P_AREG_MULT}CLK AREG to P output using multiplier

T_{DSPCKO_P_BREG}

3.94

1.64

4.51

1.87

5.37

2.22

ns

CLK BREG to P output not using

multiplier

T_{DSPCKO_P_CREG}

CLK CREG to P output not using

multiplier

1.69

3.91

1.93

4.48

2.30

5.32

ns

T_{DSPCKO_P_DREG_MULT}

CLK DREG to P output using multiplier

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DS187 (v1.3) February 11, 2013

Preliminary Product Specification

40

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 60: DSP48E1 Switching Characteristics (Cont’d)

Symbol Description

Clock to Outs from Input Register Clock to Cascading Output Pins

Speed Grade

-2

Units

-3

-1

T_{DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}}

CLK (ACOUT, BCOUT) to {A,B} register

output

0.64

4.19

0.73

4.79

0.87

5.70

ns

T_{DSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT}

CLK (AREG, BREG) to

CARRYCASCOUT output using

multiplier

T_{DSPCKO_CARRYCASCOUT_ BREG}

CLK BREG to CARRYCASCOUT output

not using multiplier

1.88

4.16

1.94

2.15

4.76

2.21

2.55

5.65

2.63

ns

T_{DSPCKO_CARRYCASCOUT_ DREG_MULT}

CLK DREG to CARRYCASCOUT output

using multiplier

T_{DSPCKO_CARRYCASCOUT_ CREG}

Maximum Frequency

F_MAX

CLK CREG to CARRYCASCOUT output

With all registers used

628.93

531.63

349.28

317.26

550.66

465.77

305.62

277.62

464.25

392.93

257.47

233.92

MHz

F_{MAX_PATDET}

With pattern detector

F_{MAX_MULT_NOMREG}

F_{MAX_MULT_NOMREG_PATDET}

Two register multiply without MREG

Two register multiply without MREG with

pattern detect

F_{MAX_PREADD_MULT_NOADREG}

F_{MAX_PREADD_MULT_NOADREG_PATDET}

F_{MAX_NOPIPELINEREG}

Without ADREG

397.30

260.01

346.26

227.01

290.44

190.69

MHz

Without ADREG with pattern detect

Without pipeline registers (MREG,

ADREG)

F_{MAX_NOPIPELINEREG_PATDET}

Without pipeline registers (MREG,

ADREG) with pattern detect

241.72

211.15

177.43

MHz

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Preliminary Product Specification

41

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Clock Buffers and Networks

Table 61: Global Clock Switching Characteristics (Including BUFGCTRL)

Speed Grade

-2

Symbol

Description

Units

-3

-1

(1)

T_{BCCCK_CE}/T_{BCCKC_CE}

CE pins setup/hold

S pins setup/hold

0.13/0.39 0.14/0.41 0.18/0.42

ns

(1)

T_{BCCCK_S}/T_{BCCKC_S}

(2)

T_{BCCKO_O}

BUFGCTRL delay from I0/I1 to O

0.08

0.09

0.11

Maximum Frequency

F_{MAX_BUFG}

Global clock tree (BUFG)

628.00

464.00

MHz

Notes:

1.

T

and T

must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These

BCCCK_CE

BCCKC_CE

parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are

optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between

clocks.

2.

T

(BUFG delay from I0 to O) values are the same as T

values.

BCCKO_O

BGCKO_O

Table 62: Input/Output Clock Switching Characteristics (BUFIO)

Symbol Description

T_{BIOCKO_O}Clock to out delay from I to O

Speed Grade

Units

-3

-2

-1

1.16

1.32

1.61

ns

Maximum Frequency

F_{MAX_BUFIO}

I/O clock tree (BUFIO)

680.00

600.00

MHz

Table 63: Regional Clock Buffer Switching Characteristics (BUFR)

Symbol Description

Clock to out delay from I to O

Speed Grade

Units

-3

-2

-1

T_{BRCKO_O}

T_{BRCKO_O_BYP}

T_{BRDO_O}

0.64

0.35

0.85

0.80

0.41

0.89

1.04

0.54

1.14

ns

Clock to out delay from I to O with Divide Bypass attribute set

Propagation delay from CLR to O

Maximum Frequency

(1)

F_{MAX_BUFR}

Regional clock tree (BUFR)

420.00

375.00

315.00

MHz

Notes:

1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F

frequency.

MAX

Table 64: Horizontal Clock Buffer Switching Characteristics (BUFH)

Symbol Description

BUFH delay from I to O

Speed Grade

Units

-3

-2

-1

T_{BHCKO_O}

0.11

0.14

ns

T_{BHCCK_CE}/T_{BHCKC_CE}

Maximum Frequency

F_{MAX_BUFH}

CE pin setup and hold

0.20/0.13 0.23/0.16 0.29/0.21

Horizontal clock buffer (BUFH)

628.00

464.00

MHz

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 65: Duty-Cycle Distortion and Clock-Tree Skew

Speed Grade

-2

Symbol

Description

Device

All

Units

-3

-1

T_{DCD_CLK}

Global clock tree duty-cycle distortion⁽¹⁾

Global clock tree skew⁽²⁾

0.20

0.27

0.33

0.14

0.03

0.18

0.20

0.27

0.42

0.14

0.03

0.18

ns

T_CKSKEW

XC7Z010

XC7Z020

All

0.27

0.38

T_{DCD_BUFIO}

T_BUFIOSKEW

T_{DCD_BUFR}

I/O clock tree duty-cycle distortion

0.14

I/O clock tree skew across one clock region

Regional clock tree duty-cycle distortion

All

0.03

All

0.18

Notes:

1. These parameters represent the worst-case duty-cycle distortion observable at the pins of the device using LVDS output buffers. For cases

where other I/O standards are used, IBIS can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical

rise/fall times.

2. The T

value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree

CKSKEW

skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer

tools to evaluate application specific clock skew.

MMCM Switching Characteristics

Table 66: MMCM Specification

Speed Grade

Symbol

Description

Units

-3

-2

-1

MMCM_F_INMAX

MMCM_F_INMIN

MMCM_F_INJITTER

MMCM_F_INDUTY

Maximum input clock frequency

800.00

10.00

800.00

10.00

800.00

10.00

MHz

Minimum input clock frequency

Maximum input clock period jitter

< 20% of clock input period or 1 ns Max

Allowable input duty cycle: 10—49 MHz

Allowable input duty cycle: 50—199 MHz

Allowable input duty cycle: 200—399 MHz

Allowable input duty cycle: 400—499 MHz

Allowable input duty cycle: >500 MHz

Minimum dynamic phase-shift clock frequency

Maximum dynamic phase-shift clock frequency

Minimum MMCM VCO frequency

25

30

25

30

25

30

%

35

%

40

%

45

%

MMCM_F_{MIN_PSCLK}

MMCM_F_{MAX_PSCLK}

MMCM_F_VCOMIN

0.01

550.00

600.00

0.01

500.00

600.00

0.01

450.00

600.00

MHz

ns

MMCM_F_VCOMAX

MMCM_F_BANDWIDTH

Maximum MMCM VCO frequency

1600.00 1440.00 1200.00

Low MMCM bandwidth at typical⁽¹⁾

High MMCM bandwidth at typical⁽¹⁾

Static phase offset of the MMCM outputs⁽²⁾

MMCM output jitter

1.00

4.00

0.12

1.00

4.00

0.12

1.00

4.00

0.12

MMCM_T_{STATPHAOFFSET}

MMCM_T_OUTJITTER

MMCM_T_OUTDUTY

MMCM_T_LOCKMAX

MMCM_F_OUTMAX

MMCM_F_OUTMIN

Note 3

MMCM output clock duty-cycle precision⁽⁴⁾

MMCM maximum lock time

0.20

100.00

800.00

4.69

0.20

100.00

800.00

4.69

ns

µs

100.00

800.00

4.69

MMCM maximum output frequency

MMCM minimum output frequency⁽⁵⁾⁽⁶⁾

External clock feedback variation

MHz

MMCM_T_EXTFDVAR

MMCM_RST_MINPULSE

MMCM_F_PFDMAX

< 20% of clock input period or 1 ns Max

Minimum reset pulse width

5.00

550.00

10.00

5.00

500.00

10.00

5.00

450.00

10.00

ns

Maximum frequency at the phase frequency detector

Minimum frequency at the phase frequency detector

MHz

MMCM_F_PFDMIN

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 66: MMCM Specification (Cont’d)

Speed Grade

-2

Symbol

Description

Units

-3

-1

MMCM_T_FBDELAY

Maximum delay in the feedback path

3 ns Max or one CLKIN cycle

MMCM Switching Characteristics Setup and Hold

T_{MMCMDCK_PSEN}

/

Setup and hold of phase-shift enable

1.04/0.00 1.04/0.00 1.04/0.00

ns

T_{MMCMCKD_PSEN}

T_{MMCMDCK_PSINCDEC}

T_{MMCMCKD_PSINCDEC}

/

Setup and hold of phase-shift increment/decrement

Phase shift clock-to-out of PSDONE

T_{MMCMCKO_PSDONE}

0.59

0.68

0.81

Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK

T_{MMCMDCK_DADDR}

/

DADDR setup/hold

1.25/0.15 1.40/0.15 1.63/0.15 ns, Min

1.76/0.00 1.97/0.00 2.29/0.00 ns, Min

1.25/0.15 1.40/0.15 1.63/0.15 ns, Min

T_{MMCMCKD_DADDR}

T_{MMCMDCK_DI}

T_{MMCMCKD_DI}

/

DI setup/hold

T_{MMCMDCK_DEN}

/

DEN setup/hold

DWE setup/hold

T_{MMCMCKD_DEN}

T_{MMCMDCK_DWE}

/

T_{MMCMCKD_DWE}

T_{MMCMCKO_DRDY}

F_DCK

CLK to out of DRDY

DCLK frequency

0.65

0.72

0.99

ns, Max

200.00

200.00 MHz, Max

Notes:

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any MMCM outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50%.

VCO

6. When CLKOUT4_CASCADE = TRUE, MMCM_F

is 0.036 MHz.

OUTMIN

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PLL Switching Characteristics

Table 67: PLL Specification

Speed Grade

-2

Symbol

Description

Units

-3

-1

PLL_F_INMAX

PLL_F_INMIN

Maximum input clock frequency

800.00

19.00

800.00

19.00

800.00

19.00

MHz

Minimum input clock frequency

PLL_F_INJITTER

PLL_F_INDUTY

Maximum input clock period jitter

Allowable input duty cycle: 19—49 MHz

Allowable input duty cycle: 50—199 MHz

Allowable input duty cycle: 200—399 MHz

Allowable input duty cycle: 400—499 MHz

Allowable input duty cycle: >500 MHz

Minimum PLL VCO frequency

< 20% of clock input period or 1 ns Max

25

30

25

30

25

30

%

35

%

40

%

45

%

PLL_F_VCOMIN

800.00

MHz

ns

PLL_F_VCOMAX

PLL_F_BANDWIDTH

Maximum PLL VCO frequency

2133.00 1866.00 1600.00

Low PLL bandwidth at typical⁽¹⁾

1.00

4.00

0.12

1.00

4.00

0.12

1.00

4.00

0.12

High PLL bandwidth at typical⁽¹⁾

Static phase offset of the PLL outputs⁽²⁾

PLL output jitter

PLL_T_{STATPHAOFFSET}

PLL_T_OUTJITTER

PLL_T_OUTDUTY

PLL_T_LOCKMAX

PLL_F_OUTMAX

Note 3

PLL output clock duty-cycle precision⁽⁴⁾

PLL maximum lock time

0.20

100.00

800.00

6.25

0.20

100.00

800.00

6.25

0.20

100.00

800.00

6.25

ns

µs

PLL maximum output frequency

MHz

PLL_F_OUTMIN

PLL minimum output frequency⁽⁵⁾

External clock feedback variation

Minimum reset pulse width

PLL_T_EXTFDVAR

PLL_RST_MINPULSE

PLL_F_PFDMAX

< 20% of clock input period or 1 ns Max

5.00

550.00

19.00

5.00

500.00

19.00

5.00

450.00

19.00

ns

Maximum frequency at the phase frequency detector

Minimum frequency at the phase frequency detector

Maximum delay in the feedback path

MHz

PLL_F_PFDMIN

PLL_T_FBDELAY

3 ns Max or one CLKIN cycle

Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK

T_{PLLCCK_DADDR}/T_{PLLCKC_DADDR}Setup and hold of D address

1.25/0.15 1.40/0.15 1.63/0.15

1.76/0.00 1.97/0.00 2.29/0.00

1.25/0.15 1.40/0.15 1.63/0.15

ns, Min

ns, Max

T

_{PLLCCK_DI}/T_{PLLCKC_DI}

Setup and hold of D input

Setup and hold of D enable

Setup and hold of D write enable

CLK to out of DRDY

T_{PLLCCK_DEN}/T_{PLLCKC_DEN}

T_{PLLCCK_DWE}/T_{PLLCKC_DWE}

T_{PLLCKO_DRDY}

0.65

0.72

0.99

F_DCK

DCLK frequency

200.00

200.00 MHz, Max

Notes:

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any PLL outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50%.

VCO

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Device Pin-to-Pin Output Parameter Guidelines

Table 68: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)

Speed Grade

Symbol

Description

Device

Units

-3

-2

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.

T_ICKOF

Clock-capable clock input and OUTFF without

MMCM/PLL (near clock region)

XC7Z010

XC7Z020

5.08

5.42

5.68

6.05

6.65

7.08

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

Table 69: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)

Speed Grade

Symbol

Description

Device

Units

-3

-2

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.

T_ICKOFFAR

Clock-capable clock input and OUTFF without

MMCM/PLL (far clock region)

XC7Z010

XC7Z020

5.08

5.69

5.68

6.34

6.65

7.40

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

Table 70: Clock-Capable Clock Input to Output Delay With MMCM

Speed Grade

Symbol

Description

Device

Units

-3

-2

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with MMCM.

T_ICKOFMMCMCC

Clock-capable clock input and OUTFF with MMCM

XC7Z010

XC7Z020

1.04

1.05

1.03

1.04

1.03

1.05

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. MMCM output jitter is already included in the timing calculation.

Table 71: Clock-Capable Clock Input to Output Delay With PLL

Speed Grade

Symbol

Description

Device

Units

-3

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with PLL.

-2

-1

T_ICKOFPLLCC

Clock-capable clock input and OUTFF with PLL

XC7Z010

XC7Z020

0.82

ns

Notes:

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. PLL output jitter is already included in the timing calculation.

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 72: Pin-to-Pin, Clock-to-Out using BUFIO

Symbol Description

Speed Grade

-2

Units

-3

-1

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.

T_ICKOFCSClock to out of I/O clock 4.93

5.52

6.20

ns

Device Pin-to-Pin Input Parameter Guidelines

Table 73: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks

Speed Grade

Symbol

Description

Device

Units

-3

-2

-1

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSFD/ T_PHFD

Full delay (legacy delay or default delay)

global clock input and IFF⁽²⁾without MMCM/PLL with

ZHOLD_DELAY on HR I/O banks

XC7Z010

XC7Z020

2.00/–0.17 2.13/–0.17 2.44/–0.17

2.55/–0.25 2.74/–0.25 3.18/–0.25

ns

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global

clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input

signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch

3. A zero "0" hold time listing indicates no hold time or a negative hold time.

Table 74: Clock-Capable Clock Input Setup and Hold With MMCM

Speed Grade

Symbol

Description

Device

Units

-3

-2

-1

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSMMCMCC

/

No delay clock-capable clock input and IFF⁽²⁾with

MMCM

XC7Z010

XC7Z020

2.36/–0.62 2.68/–0.62 3.22/–0.62

2.48/–0.62 2.82/–0.62 3.38/–0.62

ns

T_PHMMCMCC

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global

clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input

signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Table 75: Clock-Capable Clock Input Setup and Hold With PLL

Speed Grade

Symbol

Description

Device

Units

-3

Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.⁽¹⁾

-2

-1

T_PSPLLCC

/

No delay clock-capable clock input and IFF⁽²⁾with

PLL

XC7Z010

XC7Z020

2.67/–0.19 3.03/–0.19 3.64/–0.19

2.79/–0.20 3.17/–0.20 3.80/–0.20

ns

T_PHPLLCC

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global

clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 76: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

Speed Grade

Symbol

Description

Units

-3

Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.

-2

-1

T_PSCS/T_PHCS

Setup and hold of I/O clock

–0.36/1.36 –0.36/1.50 –0.36/1.70

ns

Table 77: Sample Window

Speed Grade

Symbol

Description

Units

-3

-2

-1

T_SAMP

Sampling error at receiver pins⁽¹⁾

0.59

0.35

0.64

0.40

0.70

0.46

ns

T_{SAMP_BUFIO}

Sampling error at receiver pins using BUFIO⁽²⁾

Notes:

1. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The

characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:

- CLK0 MMCM jitter

- MMCM accuracy (phase offset)

- MMCM phase shift resolution

These measurements do not include package or clock tree skew.

2. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The

characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These

measurements do not include package or clock tree skew.

Additional Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for PL clock transmitter and

receiver data-valid windows.

Table 78: Package Skew

Symbol

T_PKGSKEW

Description

Device

Package

CLG225

CLG400

CLG484

Value

101

Units

ps

Package skew⁽¹⁾

XC7Z010

155

ps

166

ps

XC7Z020

248

ps

Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die

pad to ball.

2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

XADC Specifications

Table 79: XADC Specifications

Parameter Symbol

Comments/Conditions

Min

Typ

Max

Units

V_CCADC= 1.8V 5%, V_REFP= 1.25V, V_REFN= 0V, ADCCLK = 26 MHz, T_j= –40°C to 100°C, Typical values at T_j=+40°C

ADC Accuracy⁽¹⁾

Resolution

12

–

3

–

Bits

LSBs

%

Integral Nonlinearity⁽²⁾

Differential Nonlinearity

Offset Error

INL

2

DNL

No missing codes, guaranteed monotonic

Unipolar operation

–

1

8

–

Bipolar operation

–

4

Gain Error

–

0.5

4

Offset Matching

Gain Matching

Sample Rate

–

LSBs

%

–

0.3

1

0.1

60

–

MS/s

dB

Signal to Noise Ratio⁽²⁾

RMS Code Noise

SNR

THD

F_SAMPLE= 500KS/s, F_IN= 20KHz

External 1.25V reference

–

2

LSBs

dB

On-chip reference

–

Total Harmonic Distortion⁽²⁾

F_SAMPLE= 500KS/s, F_IN= 20KHz

70

–

ADC Accuracy at Extended Temperatures (-55°C to 125°C)

Resolution

10

–

1

Bits

Integral Nonlinearity⁽²⁾

Differential Nonlinearity

Analog Inputs⁽³⁾

INL

LSB

(at 10 bits)

DNL

No missing codes, guaranteed monotonic

–

ADC Input Ranges

Unipolar operation

0

–

1

V

Bipolar operation

–0.5

0

+0.5

Unipolar common mode range (FS input)

Bipolar common mode range (FS input)

+0.5

–0.1

+0.6

Maximum External Channel Input Ranges

Adjacent analog channels set within these

ranges should not corrupt measurements on

adjacent channels

V_CCADC

Auxiliary Channel Full

Resolution Bandwidth

FRBW

250

–

KHz

On-Chip Sensors

Temperature Sensor Error

T_j= –40°C to 100°C.

T_j= –55°C to +125°C

–

4

6

1

°C

%

Supply Sensor Error

Measurement range of V_CCAUX1.8V 5%

T_j= –40°C to +100°C

Measurement range of V_CCAUX1.8V 5%

T_j= –55°C to +125°C

–

2

%

Conversion Rate⁽⁴⁾

Conversion Time - Continuous t_CONV

Number of ADCCLK cycles

Number of CLK cycles

DRP clock frequency

Derived from DCLK

26

–

32

21

Cycles

MHz

Conversion Time - Event

DRP Clock Frequency

ADC Clock Frequency

t_CONV

DCLK

8

250

26

ADCCLK

1

MHz

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Table 79: XADC Specifications (Cont’d)

Parameter

DCLK Duty Cycle

Symbol

Comments/Conditions

Min

Typ

Max

Units

40

–

60

%

XADC Reference⁽⁵⁾

External Reference

On-Chip Reference

V_REFP

Externally supplied reference voltage

1.20

1.25

1.30

V

Ground V_REFPpin to AGND,

T_j= –40°C to 100°C

1.2375

1.2625

Notes:

1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature

is enabled.

2. Only specified for BitGen option XADCEnhancedLinearity = ON.

3. See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.

4. See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description.

5. Any variation in the reference voltage from the nominal V

= 1.25V and V

= 0V will result in a deviation from the ideal transfer

REFP

REFN

function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external

ratiometric type applications allowing reference to vary by 4% is permitted. On-chip reference variation is 1%.

Configuration Switching Characteristics

Table 80: Configuration Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-2

-1

Power-up Timing Characteristics

T_POR

Power-on reset

50.00

ms, Max

Boundary-Scan Port Timing Specifications

T_TAPTCK/T_TCKTAP

T_TCKTDO

TMS and TDI setup/hold

3.00/2.00 3.00/2.00 3.00/2.00

ns, Min

ns, Max

TCK falling edge to TDO output

TCK frequency

7.00

F_TCK

66.00

MHz, Max

Internal Configuration Access Port

F_ICAPCK

Internal configuration access port (ICAPE2)

100.00

MHz, Max

eFUSE Programming Conditions

Table 81 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA

Configuration User Guide.

(1)

Table 81: eFUSE Programming Conditions

Symbol

Description

Min

–

Typ

–

Max

115

125

Units

mA

I_FS

t _j

Notes:

1. The Zynq-7000 device must not be configured during eFUSE programming.

V_CCAUXsupply current

Temperature range

15

–

°C

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Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

Revision History

The following table shows the revision history for this document:

Date

Version

1.0

Description of Revisions

05/07/12

06/27/12

Initial Xilinx release.

1.1

Updated the descriptions, changed V_IN, Note 3, Note 4, and added V_PREF, V_PIN, and Note 5 in

Table 1. In Table 2, updated descriptions and notes. Updated Table 3 and added R_{IN_TERM}. Removed

I_CCMIOQfrom Table 5. Removed I_CCMIOQand updated XC7Z020 in Table 6. Updated LVCMOS12,

SSTL135, and SSTL15 in Table 10. Updated Table 17.

In PS Performance Characteristics section, added timing diagrams and revised many tables.

Updated Table 46 and removed notes 2 and 3. Added Note 2 and Note 3 to Table 47. Changed

Table 49 by adding T_{IOIBUFDISABLE}. Removed many of the combinatorial delay specifications and

T_CINCK/T_CKCINfrom Table 56.

In Table 79 updated Offset Error and Matching descriptions and Gain Error and Matching descriptions,

and added Note 2 to Integral Nonlinearity.

09/12/12

1.2

Changed Note 3 and added Note 6 in Table 1. Updated T_jin Table 2, also revised Note 4 and Note 7.

Updated specifications including R_{IN_TERM}in Table 3. Added Table 4. Updated the XC7Z020

specifications in Table 6. Updated standards in Table 8. Updated specifications in Table 12.

Updated the AC Switching Characteristics section for the ISE 14.2 speed specifications throughout the

document.

In PS Performance Characteristics section introduction, revised tables, updated Figure 4, and added

Figure 5. Updated parameters in Figure 5 through Figure 13. Updated values in Table 16. Added

Note 2 to Table 23. Added Note 3 to Table 32. Updated descriptions and revised F_MSPICLKin Table 36.

Updated Note 3 in Table 47. Changed F_PFDMAXconditions in Table 66 and Table 67. Updated devices

and added values to Table 78.

02/11/13

1.3

Updated the AC Switching Characteristics based upon ISE 14.4 and Vivado 2012.4, both at v1.05 for

the -3, -2, and -1 speed specifications throughout the document. Updated Table 14 and Table 15 to the

product status of production for the XC7Z020 devices with -2 and -1 speed specifications.

Updated description in Introduction. Revised V_PINin Table 1. Revised V_PINand I_INand added Note 2

to Table 2. Clarified PS specifications, added C_PIN, and removed Note 3 on I_RPDin Table 3. Added

values to Table 5. Updated Power Supply Requirements section. Revised descriptions in Table 7.

Revised Note 1, removed LVTTL, notes 2 and 3, and added SSTL135 to Table 8. Added Table 9.

Removed HSTL_I_12 and SSTL_12 from Table 10. Removed DIFF_SSTL12 from Table 12. Revise in

V_CCOmin/max in Table 13.

Many changes to the PS Switching Characteristics section including adding tables, figures, notes with

test conditions where applicable. In Table 16, updated the 6:2:1 clock ratio frequencies. Updated

minimum value for T_ULPIDCKin Table 31. Added a 2:1 memory controller section to Table 47.

Updated Note 1 in Table 63. Updated Note 1 and Note 2 in Table 78.Updated the rows on offset error

and matching and gain error and matching and the maximum external channel input ranges in

Table 79. Added Internal Configuration Access Port section to Table 80.

DS187 (v1.3) February 11, 2013

Preliminary Product Specification

www.xilinx.com

51

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics

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DS187 (v1.3) February 11, 2013

www.xilinx.com

Preliminary Product Specification

52


型号：	XC7Z020-3CLG484C
厂家：	XILINX, INC
描述：	Multifunction Peripheral,
文件：	总52页 (文件大小：1974K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC7Z020-3CLG484C [XILINX]

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