X9260US24IT1 [XICOR]
Digital Potentiometer, 2 Func, 50000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24;
| 型号： | X9260US24IT1 |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 2 Func, 50000ohm, 3-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24 光电二极管 转换器 电阻器 |
| 文件： | 总25页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Dual Supply / Low Power / 256-tap / SPI bus
X9260
Dual Digitally-Controlled (XDCPTM) Potentiometers
FEATURES
DESCRIPTION
• Dual–Two Separate Potentiometers
• 256 resistor taps/pot–0.4% resolution
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 100Ω typical @ V+ = 5V, V- = -5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
The X9260 integrates
potentiometer (XDCP) on
integrated circuit.
2
digitally controlled
monolithic CMOS
a
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nononvolatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.
• Standby Current < 5µA Max
• V : 2.7V to 5.5V Operation
CC
• 50KΩ, 100KΩ versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24-Lead SOIC, 24-Lead XBGA
• Low Power CMOS
The XDCP can be used as
a three-terminal
• Power Supply V
= 2.7V to 5.5V
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
CC
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
FUNCTIONAL DIAGRAM
V
V
+
R
R
H1
CC
H0
Write
Read
Address
Data
Status
Transfer
Inc/Dec
Power On Recall
Bus
SPI
Bus
Interface
Wiper Counter
Interface
and Control
Registers (WCR)
Data Registers
(DR0-DR3)
Control
V
V-
R
R
R
R
L1
SS
W0
L0
W1
50KΩ or 100KΩ versions
Characteristics subject to change without notice. 1 of 25
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X9260
DETAILED FUNCTIONAL DIAGRAM
R
R
R
H0
L0 W0
V
V
CC
+
Power On
Recall
Pot 0
R
R
0
1
Wiper
Counter
Register
(WCR)
HOLD
CS
SCK
SO
SI
A0
A1
INTERFACE
AND
CONTROL
CIRCUITRY
R
R
2
3
50KΩ and 100KΩ
256-taps
8
Power On
Recall
Data
WP
R
R
0
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
R
2
3
V
R
R R
SS
L1 H1 W1
V-
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF wireless
systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
Characteristics subject to change without notice. 2 of 25
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X9260
PIN CONFIGURATION
XBGA
1
2
3
4
SOIC
HOLD
SCK
NC
SO
1
2
24
23
22
21
20
19
18
17
16
A
B
A0
NC
Not Available
3
NC
NC
V+
NC
4
NC
5
C
D
V-
6
X9260
V
V
7
CC
SS
R
R
8
W1
L0
R
R
H0
9
H1
E
F
R
R
W0
10
11
12
15
14
L1
A1
SI
CS
WP
13
Top View–Bumps Down
PIN ASSIGNMENTS
Pin
Pin
(XBGA)
(SOIC)
Symbol
SO
Function
1
Serial Data Output for SPI bus
Device Address for SPI bus.
No Connect.
2
A0
3
NC
4
NC
No Connect.
5
NC
No Connect.
6
V+
Analog Supply Voltage (Positive)
System Supply Voltage
7
V
CC
8
R
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for SPI bus.
Hardware Write Protect
Serial Data Input for SPI bus
Device Address for SPI bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
L0
H0
W0
9
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R
CS
WP
SI
A1
R
L1
H1
W1
R
R
V
SS
V-
Analog Supply Voltage (Negative)
No Connect
NC
NC
No Connect
NC
No Connect
SCK
HOLD
Serial Clock for SPI bus
Device select. Pause the SPI serial bus.
Characteristics subject to change without notice. 3 of 25
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X9260
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
Potentiometer Pins
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2sets of R and
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
H
R such that R and R are the terminals of POT 0
L
H0
L0
and so on.
SERIAL INPUT
R
W
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are
2
potentiometers, there are 2 sets of R such that R
W
W0
is the terminals of POT 0 and so on.
SERIAL CLOCK (SCK)
Supply Pins
The SCK input is used to clock data into and out of the
X9260.
SYSTEM SUPPLY VOLTAGE (V
) AND SUPPLY GROUND (V )
SS
CC
The V pin is the system supply voltage. The V pin
CC
SS
HOLD (HOLD)
is the system ground.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Analog Supply Voltages (V+ and V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
Other Pins
NO CONNECT
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9260.
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
CHIP SELECT (CS)
When CS is HIGH, the X9260 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9260, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Characteristics subject to change without notice. 4 of 25
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X9260
PRINCIPLES OF OPERATION
Serial Interface
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R ) output. Within each individual array only one
W
switch may be turned on at a time.
The X9260 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Power Up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power
up and power down, VCC, V+, and V- must reach their
Array Description
final values within 1msecs of each other. The V
ramp rate spec is always in effect.
The X9260 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
CC
terminals of a mechanical potentiometer (R and R
H
L
inputs).
Figure 1. .Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
SERIAL
R
H
BUS
FROM INTERFACE
CIRCUITRY
INPUT
C
O
U
N
T
REGISTER 1
(DR1)
REGISTER 0
(DR0)
8
8
PARALLEL
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
IF WCR = FF[H] THEN R = R
UP/DN
CLK
W
H
R
MODIFIED SCK
L
R
W
Characteristics subject to change without notice. 5 of 25
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X9260
DEVICE DESCRIPTION
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
Wiper Counter Register (WCR)
The X9260 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9260 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR.
WIP:Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
Table 5. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
Characteristics subject to change without notice. 6 of 25
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X9260
DEVICE DESCRIPTION
Instructions
successful compare of both address bits is required for
the X9260 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3-A0 inputs
can be actively driven by CMOS input signals or tied
IDENTIFICATION BYTE ( ID AND A )
The first byte sent to the X9260 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte.The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device id for the X9260; this is fixed as 0101[B] (refer to
Table 3).
to V
or V
.
CC
SS
INSTRUCTION BYTE ( I[3:0] )
The next byte sent to the X9260 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.
The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A3-A0 input pins. The slave address is
externally specified by the user. The X9260 compares
the serial data stream with the address input state; a
Table 3. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
A2
A1
A0
(MSB)
(LSB)
Table 4. Instruction Byte Format
Data
Pot Selection
(WCR Selection)
Instruction
Opcode
Register
Selection
I3
I2
I1
I0
RB
RA
0
P0
(MSB)
(LSB)
Characteristics subject to change without notice. 7 of 25
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X9260
DEVICE DESCRIPTION
Instructions
Four of the ten instructions are three bytes in length.
These instructions are:
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified
Data Registers to the associated Wiper Counter
Registers.
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
– Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
INCREMENT/DECREMENT COMMAND
– Read Status - This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The final command is Increment/Decrement (see
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9260 has responded with
an acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
SCL clock pulse (t
) while SI is HIGH, the selected
HIGH
wiper will move one resistor segment towards the R
H
terminal. Similarly, for each SCL clock pulse while SI is
LOW, the selected wiper will move one resistor
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
segment towards the R terminal. A detailed illustration
L
of the sequence and timing for this operation are
shown. See Instruction format for more details.
minimum of t
to complete. The transfer can occur
WR
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register. The Read Status Register
instruction is the only unique format (see Figure 5).
Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9260; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register.These instructions are:
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
Characteristics subject to change without notice. 8 of 25
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X9260
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
0
0
0
0
0
0
1
0
1
A1 A0
ID3 ID2 ID1 ID0
Device ID
RB RA
P0
I3
I2
I1 I0
Register
Address
Instruction
Opcode
Pot/WCR
Address
Internal
Address
Figure 3. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
0
0
1
0
1
0
ID3 ID2 ID1 ID0
A1 A0
RB RA
P0
I3 I2
I0
D7 D6 D5 D4 D3 D2 D1 D0
I1
WCR[7:0]
or
Data Register Bit [7:0]
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 4. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
0
X
ID3 ID2 ID1 ID0
Device ID
A1 A0
I2 I1
RB RA
P0
I3
I0
Don’t Care
Internal
Address
Pot/WCR
Address
Instruction
Opcode
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
Characteristics subject to change without notice. 9 of 25
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X9260
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
CS
SCL
SI
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
ID3 ID2 ID1 ID0
I3
A1 A0
I2 I1 I0 RB RA
P0
WIP
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Status
Bit
Device ID
Figure 6. Increment/Decrement Instruction Sequence
CS
SCL
SI
0
0
0
0
0
1
0
1
0
ID3 ID2 ID1 ID0
Device ID
I2 I3
I0
A1 A0
I1
RB RA
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Register
Address
Figure 7. Increment/Decrement Timing Limits
t
WRID
SCK
SI
VOLTAGE OUT
R
W
INC/DEC CMD ISSUED
Characteristics subject to change without notice. 10 of 25
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X9260
Table 5. Instruction Set
Instruction Set
Instruction
I3 I2 I1 I0 RB RA
0
P0
Operation
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1/0 Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter
Register
0
0
0
0
0
0
1/0 Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
1/0 Read the contents of the Data Register
pointed to by P0 and RB-RA
Write Data Register
1/0 Write new value to the Data Register
pointed to by P0 and RB-RA
XFR Data Register to
Wiper Counter Register
1/0 Transfer the contents of the Data Register
pointed to by P0 and RB-RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
0
0
0
0
1/0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB-RA
Global XFR Data Registers
to Wiper Counter Registers
0
Transfer the contents of the Data Registers
pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB-RA of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
Note: 1/0 = data is one or zero
Characteristics subject to change without notice. 11 of 25
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X9260
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9260 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0 P0
5
4
3
2
1
0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0 P0
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
CS
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
D
D D D D D D D
0
1
0
1
0
0 A1 A0 1
0
1
1 RB RA
0
P0
6
5 4 3 2 1 0
7
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
D
7
D D D D D D D
6 5 4 3 2 1 0
0
1
0
1
0 0 A1 A0 1 1 0 0 RB RA
0
P0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0 0 0 1 RB RA 0 0
Characteristics subject to change without notice. 12 of 25
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X9260
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 0 0 A1 A0 1 0 0 0 RB RA 0 0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 0 0 A1 A0 1 1 1 0 RB RA 0 P0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1 0 0 A1 A0 1 1 0 1 RB RA 0 P0
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Increment/Decrement
(Sent by Master on SDA)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0
0
1
0
X X 0 P0 I/D I/D
.
.
.
. I/D I/D
Read Status Register (SR)
Device Type
Identifier
Device
Addresses
0 A1 A0 0
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by X9260 on SO)
WIP
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Characteristics subject to change without notice. 13 of 25
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X9260
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias........................–65 to +135°C
Storage temperature.............................–65 to +150°C
Voltage on SCK, SCL or any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ................................. –1V to +7V
SS
Voltage on V+ (referenced to V ).........................10V
SS
Voltage on V- (referenced to V ) ........................ -10V
SS
(V+) – (V-) ..............................................................12V
Any V /R .............................................................. V+
H
H
Any V /R .................................................................V-
L
L
Lead temperature (soldering, 10 seconds) ........300°C
(10 seconds)................................................. 6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
+70°C
+85°C
Device
X9260
Supply Voltage (V
)
(4) Limits
CC
Commercial
Industrial
5V 10%
–40°C
X9260-2.7
2.7V to 5.5V
V+
V-
2.7V to 5.5V
-2.5V to -5.5V
Characteristics subject to change without notice. 14 of 25
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X9260
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance
Power rating
Min.
Typ.
Max.
20
Unit
%
Test Conditions
25°C, each pot
50
mW
mA
Ω
I
Wiper current
3
W
R
Wiper resistance
250
Wiper current = 1mA,
V+ = 3V; V- = -3V
W
R
Wiper resistance
Voltage on V+ pin
150
Ω
Wiper current = 1mA,
V+ = 3V; V- = -3V
W
Vv+
Vv-
X9260
+4.5
+2.7
-5.5
-5.5
V-
+5.5
+5.5
-4.5
-2.7
V+
V
X9260-2.7
X9260
Voltage on V- pin
V
V
X9260-2.7
V
Voltage on any V /R or V /R
H H L L
pin
TERM
Noise
Resolution (4)
-120
0.4
dBV
%
Ref: 1kHz
Absolute linearity (1)
Relative linearity (2)
1
MI(3)
MI(3)
V
V
–V
w(n)(actual) w(n)(expected)
0.6
–[V
]
w(n + 1)
w(n) + MI
Temperature coefficient
300
ppm/°C
ppm/°C
Ratiometric Temperature
Coefficient
20
C /C /C
W
Potentiometer Capacitances
10/10/25
pF
See Circuit #3
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R – R ) / 255, single pot
H
L
(4) During power up V > V , V , and V .
CC
H
L
W
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
Characteristics subject to change without notice. 15 of 25
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X9260
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 2.5 MHz, SO = Open, V =6V
I
I
I
V
supply current
(active)
400
µA
f
SCK
CC1
CC2
SB
CC
CC
Other Inputs = V
SS
V
supply current
(nonvolatile write)
1
5
5
mA
f
= 2.5MHz, SO = Open, V =6V
SCK CC
CC
Other Inputs = V
SS
V
current (standby)
µA
SCK = SI = V , Addr. = V
,
CC
SS
SS
CS = V = 6V
CC
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
CC
–1
V
x 0.3
V
IL
CC
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
0.4
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
V
= -1mA, V ≥ +3V
CC
CC
- 0.4
V
= -0.4mA, V ≤ +3V
CC
CC
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(6)
C
Output capacitance (SO)
Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK)
8
6
V
V
= 0V
OUT
OUT
(6)
C
pF
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
V Power-up rate
CC
Min.
Max.
50
Units
V/ms
ms
(6)
t V
0.2
r
CC
(7)
t
Power-up to initiation of read operation
1
PUR
POWER UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies
CC
reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be
less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all
supplies reach their final value.The V ramp rate spec is always in effect.
CC
A.C.TEST CONDITIONS
Input Pulse Levels
Input rise and fall times
Input and output timing level
V
x 0.1 to V x 0.9
CC
CC
10ns
V
x 0.5
CC
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be
PUR
PUW
CC
issued.These parameters are not 100% tested.
Characteristics subject to change without notice. 16 of 25
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X9260
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
1382Ω
SPICE Macromodel
1462Ω
R
TOTAL
R
R
L
H
SO pin
SO pin
C
C
W
C
L
L
10pF
2714Ω
1217Ω
100pF
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSI/SPI clock frequency
SSI/SPI clock cycle rime
SSI/SPI clock high rime
SSI/SPI clock low time
Lead time
2
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
50
H
2
RI
2
FI
0
0
250
200
DIS
V
SO output valid time
SO output hold time
HO
RO
FO
SO output rise time
100
100
SO output fall time
HOLD time
400
100
100
HOLD
HSU
HH
HZ
HOLD setup time
HOLD hold time
HOLD low to output in high Z
HOLD high to output in low Z
100
100
10
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
I
t
t
t
CS deselect time
WP, A0 setup time
WP, A0 hold time
2
0
0
CS
WPASU
WPAH
Characteristics subject to change without notice. 17 of 25
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X9260
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
5
5
10
10
µs
µs
WRPO
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
.
Characteristics subject to change without notice. 18 of 25
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X9260
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
t
FO
RO
SO
t
t
LZ
HZ
SI
t
HOLD
HOLD
Characteristics subject to change without notice. 19 of 25
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X9260
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
LSB
MSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 20 of 25
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X9260
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R )} V (min)
1 1 2 O
Characteristics subject to change without notice. 21 of 25
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X9260
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 22 of 25
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X9260
PACKAGING INFORMATION
24-Ball BGA (X9260TA/X9260UA)
a
a
l
j
m
k
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Orientation mark
c
e
Side View (Bump Side Down)
Millimeters
Inches
Symbol
Min
Nom.
2.783
4.561
0.730
0.457
0.273
0.374
Max
Min
Nom.
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.753
4.531
0.697
0.444
0.253
0.360
2.813
4.591
0.763
0.470
0.293
0.388
0.10838 0.10956 0.11074
0.17838 0.17956 0.18074
0.02744 0.02874 0.03004
0.01748 0.01799 0.01850
0.00996 0.01075 0.01154
0.01417 0.01472 0.01528
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
24
4
Ball Count X Axis
Ball Count Y Axis
Pins Pitch X Axis
6
j
0.5
0.5
Pins Pitch Y Axis
k
l
Edge to Ball Center (Corner)
Distance Along X
0.611
1.000
0.641
0.671
1.060
0.02407 0.02525 0.02643
0.03939 0.04057 0.04175
Edge to Ball Center (Corner)
Distance Along Y
m
1.030
Characteristics subject to change without notice. 23 of 25
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X9260
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 24 of 25
REV 1.1.2 11/10/00
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X9260
ORDERING INFORMATION
X9260
Y
P
T
V
V
Limits
CC
Device
Blank = 5V 10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
xxx = xxx-Lead XBGA
Potentiometer Organization
Pot
U =
T =
50KΩ
100KΩ
PART MARK CONVENTION
xx Lead XBGA
X9260xxxx-2.7
X9260xxxx xx
X9260 xxxx
Top Mark
X9260xxxxx I-2.7
X9260xxxx-2.7
X9260xxxx xx
X9260 xxxx
X9260xxxxx I-2.7
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 25 of 25
REV 1.1.2 11/10/00
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