X84256ZM [XICOR]
EEPROM, 32KX8, Serial, CMOS, XBGA-8;
| 型号： | X84256ZM |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, Serial, CMOS, XBGA-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总15页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
256K
MPS EEPROM
X84256
µPort Saver EEPROM
DESCRIPTION
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 3mA
• Byte or Page Write Capable
—64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100Years
• Small Packages Options
—8, 16-Lead SOIC Packages
—14-Lead TSSOP Packages
—8-Lead XBGA Packages
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Internal Block Diagram
MPS
WP
H.V. GENERATION
TIMING & CONTROL
A15
µP
µC
A0
D7
DSP
ASIC
RISC
CE
I/O
OE
EEPROM
ARRAY
COMMAND
DECODE
AND
CONTROL
LOGIC
X
DEC
D0
OE
WE
32K x 8
P0/CS
P1/CLK
P2/DI
Ports
Saved
WE
P3/DO
Y DECODE
DATA REGISTER
Xicor, Inc. 1998 Patents Pending
Characteristics subject to change without notice
1
X84256
Preliminary
PIN CONFIGURATIONS
PIN NAMES
I/O
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Drawings are to the same scale, actual package sizes are
shown in inches:
CE
OE
WE
WP
8-LEAD SOIC
V
CE
I/O
WP
1
CC
8
7
6
5
2
3
4
NC
OE
WE
V
CC
V
SS
V
Ground
SS
NC
No Connect
14-LEAD TSSOP
PIN DESCRIPTIONS
Chip Enable (CE)
CE
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
NC
I/O
NC
NC
NC
NC
OE
WE
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
NC
NC
WP
V
SS
8
Output Enable (OE)
8-LEAD XBGA
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
I/O
CE
1
V
8
CC
Write Enable (WE)
NC
2
3
4
7
6
5
X84256
The Write Enable input must be LOW to write either data
or command sequences to the device.
WE
V
SS
OE
WP
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
16-LEAD SOIC
CE
16
V
1
2
3
4
5
6
7
CC
NC
Write Protect (WP)
I/O
NC
15
14
When the Write Protect input is LOW, nonvolatile writes to
the device are disabled. When WP is HIGH, all functions,
including nonvolatile writes, operate normally. If a nonvol-
atile write cycle is in progress, WP going LOW will have
no effect on the cycle already underway, but will inhibit
any additional nonvolatile write cycles.
NC
NC
NC
NC
13
12
11
NC
NC
NC
WP
10
9
OE
V
WE
SS
8
DEVICE OPERATION
The X84256 serial EEPROM is designed to interface
directly with most microprocessor buses. Standard CE,
OE, and WE signals control the read and write opera-
tions, and a single l/O line is used to send and receive
data and commands serially.
2
X84256
Preliminary
Reset Sequence
Data Timing
The reset sequence resets the device and sets an inter-
nal write enable latch. A reset sequence can be sent at
any time by performing a read/write “0”/read operation
(see Figs. 1 and 2). This breaks the multiple read or write
cycle sequences that are normally used to read from or
write to the part. The reset sequence can be used at any
time to interrupt or end a sequential read or page load.
As soon as the write “0” cycle is complete, the part is
reset (unless a nonvolatile write cycle is in progress).The
second read cycle in this sequence, and any further read
cycles, will read a HIGH on the l/O pin until a valid read
sequence (which includes the address) is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the device initiates
these operations properly.
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
the l/O line is active whenever both OE and CE are LOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle between
the write cycles.The address is sent serially, most signifi-
cant bit first, over the I/O line. Note that this sequence is
fully static, with no special timing restrictions, and the
processor is free to perform other tasks on the bus when-
ever the device CE pin is HIGH. Once the 16 address
bits are sent, a byte of data can be read on the I/O line by
issuing 8 separate read cycles (OE and CE LOW, WE
HIGH). At this point, writing a ‘1’ will terminate the read
sequence and enter the low power standby state, other-
wise the device will await further reads in the sequential
read mode.
Write Sequence
A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 64 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 64 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address in the array is reached, the
address counter rolls over to address $0000 and reading
may be continued indefinitely.
CE
OE
WE
"0"
A10
A15 A14 A13 A12 A11
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (IN)
D7 D6 D5 D4 D3 D2 D1 D0
I/O (OUT)
RESET
WHEN ACCESSING: X84256 ARRAY: A15=0
LOAD ADDRESS
READ DATA
Figure 1. Read Sequence
3
X84256
Preliminary
CE
OE
WE
"0"
A10
A15 A14 A13 A12 A11
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
I/O (IN)
I/O (OUT)
"1"
"0"
RESET
LOAD ADDRESS
LOAD DATA
START
NONVOLATILE
WRITE
WHEN ACCESSING: X84256 ARRAY: A15=0
Figure 2. Write Sequence
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 64-
byte pages (e.g., beginning at addresses XXXXXXXXX
000000 for X84256).
Low Power Operation
The device enters an idle state, which draws minimal
current when:
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this reason,
sending more than 512 consecutive data bits will result in
overwriting previous data.
• an illegal sequence is entered.The following are the
more common illegal sequences:
—Read/Write/Write—any time
—Read/Write ‘1’—When writing the address or writ-
ing data.
A nonvolatile write cycle will not start if a partial or incom-
plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com-
pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no spe-
cial timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin
(CE) is HIGH.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
Nonvolatile Write Status
May change
Will change
from HIGH to from HIGH to
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
LOW
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
4
X84256
Preliminary
—Write ‘1’—when reading data
RECOMMENDED OPERATING CONDITIONS
—Read/Read/Write ‘1’—after data is written to device,
but before entering the NV write sequence.
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
—the device powers-up;
–40°C
–55°C
—a nonvolatile write operation completes.
Military†
While a sequential read is in progress, the device remains
in an active state. This state draws more current than the
idle state, but not as much as during a read itself. To go
back to the lowest power condition, an invalid condition is
created by writing a‘1’after the last bit of a read operation.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
—A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage
X84256
Limits
Temperature under Bias ......................–65°C to +135°C
Storage Temperature...........................–65°C to +150°C
Terminal Voltage with
5V ±10%
X84256 – 2.5
X84256 – 1.8
2.5V to 5.5V
1.8V to 3.6V
Respect to V .......................................–1V to +7V
SS
DC Output Current................................................... 5mA
Lead Temperature (Soldering, 10 seconds)..........300°C
D.C. OPERATING CHARACTERISTICS (V
= 5V ±10%)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
OE = V , WE = V ,
I
V
V
Supply Current (Read)
1
mA
CC1
CC
IL
IH
I/O = Open, CE clocking @ 10MHz
I
During Nonvolatile Write Cycle
CC
I
Supply Current (Write)
Standby Current
3
mA
CC2
CC
CC
All Inputs at CMOS Levels
I
I
I
V
CE = V , Other Inputs = V or V
SS
1
µA
µA
µA
V
SB1
CC
CC
V
= V to V
SS
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
LI
IN
CC
V
= V to V
CC
LO
OUT
SS
(1)
(1)
V
V
x 0.3
V
–0.5
CC
lL
V
V
x 0.7
+ 0.5
CC
V
V
V
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
CC
IH
I
= 2.1mA
0.4
V
OL
OL
– 0.8
I
= –1mA
V
OH
CC
OH
Notes: (1) V Min. and V Max. are for reference only and are not tested.
IL
IH
5
X84256
Preliminary
D.C. OPERATING CHARACTERISTICS (V
= 2.5V to 5.5V)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Units
mA
Test Conditions
OE = V , WE = V ,
Min.
Max.
IL
IH
I
V
Supply Current (Read)
1
CC1
CC
I/O = Open, CE clocking @ 5MHz
During Nonvolatile Write Cycle
I
CC
I
V
V
Supply Current (Write)
Standby Current
3
mA
CC2
CC
CC
All Inputs at CMOS Levels
I
CE = V , Other Inputs = V or V
SS
1
µA
µA
µA
V
SB1
CC
CC
I
V
V
= V to V
CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
LI
IN
SS
I
= V to V
SS CC
LO
OUT
(1)
V
V
V
x 0.3
–0.5
CC
lL
(1)
V
V
V
x 0.7
+ 0.5
CC
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
CC
CC
CC
IH
V
I
= 1mA, V
= 3V
0.4
V
OL
OL
CC
V
– 0.4
I
= –400µA, V
= 3V
V
OH
OH
CC
D.C. OPERATING CHARACTERISTICS (V
= 1.8V to 3.6V)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Units
µA
Test Conditions
OE = V , WE = V ,
Min.
Max.
IL
IH
I
V
Supply Current (Read)
500
CC1
CC
I/O = Open, CE clocking @ 3MHz
During Nonvolatile Write Cycle
I
CC
I
V
V
Supply Current (Write)
Standby Current
2
mA
CC2
CC
CC
All Inputs at CMOS Levels
I
CE = V , Other Inputs = V or V
SS
1
µA
µA
µA
V
SB1
CC
CC
I
V
V
= V to V
CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
LI
IN
SS
I
= V to V
SS CC
LO
OUT
(1)
V
V
V
x 0.3
–0.5
CC
lL
(1)
V
V
V
x 0.7
+ 0.5
CC
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
CC
IH
V
I
= 0.5mA, V
= 2V
0.4
V
OL
OL
CC
V
– 0.2
I
= –250µA, V
= 2V
V
OH
CC
OH
CC
Notes: (1) V Min. and V Max. are for reference only and are not tested.
IL
IH
6
X84256
Preliminary
CAPACITANCE
Symbol
T = +25°C, f = 1MHz, V
= 5V
A
CC
Parameter
Max.
Units
Test Conditions
(2)
C
V
= 0V
= 0V
Input/Output Capacitance
8
pF
I/O
I/O
(2)
C
V
Input Capacitance
6
pF
IN
IN
Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(3)
t
t
Power-up to Read Operation
2
ms
ms
PUR
(3)
Power-up to Write Operation
5
PUW
Notes: (3) Time delays required from the time the V is stable until the specific operation can be initiated.
CC
Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST
V
x 0.1 to V x 0.9
CC
Input Pulse Levels
CC
Input Rise and Fall Times
5ns
V
x 0.5
Input and Output Timing Levels
CC
EQUIVALENT A.C. LOAD CIRCUITS
2V
5V
3V
2.8KΩ
2.06KΩ
2.39KΩ
OUTPUT
5.6KΩ
OUTPUT
OUTPUT
4.58KΩ
3.03KΩ
30pF
30pF
30pF
7008 FRM F06
7008 FRM F07
7
X84256
Preliminary
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits – X84256
V
= 5V±10%
V
= 2.5V – 5.5V V = 1.8V – 3.6V
CC
CC CC
Symbol
Parameter
Read Cycle Time
Min.
Max
Min.
200
Max.
Min.
330
Max.
Units
ns
t
100
RC
t
CE Access Time
25
25
50
50
70
70
ns
CE
t
OE Access Time
ns
OE
t
OE Pulse Width
50
50
50
50
0
60
60
70
120
0
90
90
90
180
0
ns
OEL
t
OE High Recovery Time
CE LOW Time
ns
OEH
t
ns
LOW
t
CE HIGH Time
ns
HIGH
(4)
t
CE LOW to Output In Low Z
ns
ns
LZ
(4)
t
CE HIGH to Output In High Z
0
25
25
0
30
30
0
35
35
HZ
(4)
t
OE LOW to Output In Low Z
OE HIGH to Output In High Z
Output Hold from CE or OE HIGH
WE HIGH Setup Time
0
0
0
0
0
0
ns
ns
ns
ns
ns
OLZ
(4)
t
OHZ
t
0
0
0
OH
t
25
25
25
25
25
25
WES
t
WE HIGH Hold Time
WEH
Notes: (4) Periodically sampled, but not 100% tested. t and t
are measured from the point where CE or OE goes HIGH (whichever occurs
HZ
OHZ
first) to the time when I/O is no longer being driven into a 5pF load.
t
RC
t
t
HIGH
LOW
t
CE
CE
WE
t
WES
t
OEL
t
OEH
t
OE
OE
I/O
t
WEH
t
OHZ
HIGH Z
DATA
t
OH
t
t
OLZ
LZ
t
HZ
8
X84256
Preliminary
Write Cycle Limits – X84256
V
= 5V ±10%
V
= 2.5V – 5.5V V = 1.8V – 3.6V
CC
CC CC
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
(5)
t
Nonvolatile Write Cycle Time
Write Cycle Time
5
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
NVWC
t
t
100
25
65
0
200
40
150
0
330
70
200
0
WC
WE Pulse Width
WP
t
t
t
t
t
t
t
t
t
WE HIGH Recovery Time
Write Setup Time
WPH
CS
Write Hold Time
0
0
0
CH
CE Pulse Width
25
65
25
25
40
150
25
25
70
200
50
50
CP
CE HIGH Recovery Time
OE HIGH Setup Time
OE HIGH Hold Time
CPH
OES
OEH
(6)
Data Setup Time
Data Hold Time
WP HIGH Setup
WP HIGH Hold
12
5
20
5
30
5
ns
ns
ns
ns
DS
(6)
DH
(7)
(7)
t
100
100
100
100
150
150
WPSU
t
WPHD
Notes: (5) t
is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write cycle”
NVWC
sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84256 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
9
X84256
Preliminary
CE Controlled Write Cycle
t
CPH
t
CP
CE
t
t
OEH
OES
OE
WE
WP
I/O
t
CS
t
CH
t
WP
t
WPH
t
t
WPSU
WPHD
t
t
DS
DH
HIGH Z
DATA
t
WC
WE Controlled Write Cycle
t
CPH
t
CP
CE
t
OES
t
OE
WE
WP
I/O
CS
t
CH
t
OEH
t
WPH
t
WP
t
WPHD
t
WPSU
t
t
DS
DH
HIGH Z
DATA
t
WC
10
X84256
Preliminary
PACKAGING INFORMATION
8-LEAD XBGA
X84256: Bottom View
D1
V
CC
I/O
CE
NC
V
WE
SS
OE
WP
D
D
A1
A
NOTE: ALL DIMENSIONS IN µM
ALL DIMENSIONS ARE TYPICAL VALUES
11
X84256
Preliminary
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050"TYPICAL
X 45°
0.050"
0° – 8°
TYPICAL
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
12
X84256
Preliminary
16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.386 (9.80)
0.394 (10.01)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0° – 8°
0.050"
Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030" Typical
16 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X84256
Preliminary
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X84256
Preliminary
ORDERING INFORMATION
X84256
X
X
–X
V
Range
CC
Device
Blank = 4.5V to 5.5V, 10 MHz
2.5 = 2.5V to 5.5V, 5 MHz
1.8 = 1.8V to 3.6V, 3MHz (contact factory)
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Military = –55°C to +125°C (contact factory)
Packages:
X84256
S8 = 8-Lead SOIC
S16 = 16-Lead SOIC
V14 = 14-Lead TSSOP
Z = 8-Lead XBGA
*PART MARK CONVENTION
14-Lead TSSOP
8-Lead XBGA
8-Lead SOIC
Complete Part Number
Top Mark
Blank = 8-Lead SOIC
YWW
84256
X84256 X
XX
X84256Z–2.5
X84256ZI–2.5
XABA
XABB
F = 2.5 to 5.5V, 0 to +70°C
G = 2.5 to 5.5V, -40 to +85°C
F = 2.5 to 5.5V, 0 to +70°C
G = 2.5 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
I = 4.5 to 5.5V, -40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
15
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