X5163 [XICOR]
CPU Supervisor with 16Kbit SPI EEPROM; CPU监控与16Kbit的EEPROM SPI
| 型号： | X5163 |
| 厂家： | 
XICOR INC. |
| 描述： | CPU Supervisor with 16Kbit SPI EEPROM |
| 文件： | 总21页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
Replaces X25163/X25165
X5163/X5165
CPU Supervisor with 16Kbit SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low V detection and reset assertion
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
CC
—Five standard reset threshold voltages
—Re-program low V reset threshold voltage
CC
using special programming sequence
—Reset signal valid to V = 1V
CC
• Determine watchdog or low voltage reset with a
volatile flag bit
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 16Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V falls below the minimum V trip point.
CC
CC
—Self-timed write cycle
RESET/RESET is asserted until V
returns to proper
CC
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14-lead TSSOP, 8-lead SOIC
operating level and stabilizes. Five industry standard
thresholds are available, however, Xicor’s unique
V
TRIP
circuits allow the threshold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET/RESET
SI
Data
Register
Status
Register
SO
X5163 = RESET
X5165 = RESET
Command
Decode &
Control
Reset &
Watchdog
Timebase
SCK
4K Bits
4K Bits
CS/WDI
Logic
V
Threshold
CC
8K Bits
Reset Logic
Power on and
Low Voltage
Reset
V
+
-
CC
Generation
V
TRIP
Characteristics subject to change without notice. 1 of 21
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X5163/X5165 – Preliminary Information
PIN DESCRIPTION
Pin
Pin
(SOIC/PDIP) TSSOP
Name
Function
1
1
CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power up, a HIGH to
LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
2
3
2
6
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin.The falling edge of the serial clock (SCK) clocks the data out.
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
4
5
7
8
V
Ground
SS
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
7
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put.The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin.The falling edge of SCK changes the data output on the SO pin.
13
RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V falls below the minimum V sense level. It will remain
RESET
CC
CC
active until V rises above the minimum V sense level for 200ms. RESET/
CC
CC
RESET goes active if the Watchdog Timer is enabled and CS remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power
up at 1V and remains active for 200ms after the power supply stabilizes.
8
14
V
Supply Voltage
CC
3-5,10-
12
NC
No internal connections
PIN CONFIGURATION
14-Lead TSSOP
8-Lead SOIC/PDIP
CS/WDI
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
SO
NC
RESET/RESET
V
1
8
CS/WDI
SO
CC
NC
NC
NC
SCK
SI
2
3
7
6
RESET/RESET
SCK
X5163/65
NC
NC
WP
X5163/65
WP
V
SS
4
5
SI
V
SS
8
Characteristics subject to change without notice. 2 of 21
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X5163/X5165 – Preliminary Information
PRINCIPLES OF OPERATION
Power On Reset
To set the new V
threshold to the V
the WP pin HIGH. RESET and SO pins are left uncon-
voltage, apply the desired V
pin and tie the CS/WDI pin and
TRIP TRIP
CC
nected. Then apply the programming voltage V to
both SCK and SI and pulse CS/WDI LOW then HIGH.
P
Application of power to the X5163/X5165 activates a
Power On Reset Circuit. This circuit goes active at 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
Remove V and the sequence is complete.
P
Figure 1. Set V
Voltage
TRIP
of the oscillator. When V
exceeds the device V
CC
TRIP
value for 200ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing code.
CS
V
P
Low Voltage Monitoring
SCK
SI
During operation, the X5163/X5165 monitors the V
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V . The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
CC
V
P
TRIP
Resetting the V
Voltage
TRIP
It also remains active until V
returns and exceeds
CC
This procedure sets the V
level. For example, if the current V
to a “native” voltage
V
for 200ms.
TRIP
TRIP
is 4.4V and the
TRIP
V
is reset, the new V
is something less than
Watchdog Timer
TRIP
TRIP
1.7V. This procedure must be used to set the voltage to
a lower value.
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the WDI input. The micropro-
cessor must toggle the CS/WDI pin periodically to
prevent a RESET/RESET signal. The CS/WDI pin
must be toggled from HIGH to LOW prior to the expira-
tion of the watchdog time out period. The state of two
nonvolatile control bits in the Status Register deter-
mine the watchdog timer period. The microprocessor
can change these watchdog bits, or they may be
“locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
To reset the V
voltage, apply a voltage between
TRIP
2.7 and 5.5V to the V
pin. Tie the CS/WDI pin, the
CC
WP pin, AND THE SCK pin HIGH. RESET and SO
pins are left unconnected. Then apply the program-
ming voltage V to the SI pin ONLY and pulse CS/WDI
P
LOW then HIGH. Remove V and the sequence is
P
complete.
Figure 2. Reset V
Voltage
TRIP
V
Threshold Reset Procedure
CC
CS
The X5163/X5165 has a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
V
V
CC
operating and storage conditions. However, in applica-
tions where the standard V
for higher precision in the V
X5165 threshold may be adjusted.
SCK
SI
is not exactly right, or
value, the X5163/
TRIP
TRIP
P
Setting the V Voltage
TRIP
This procedure sets the V
to a higher voltage
TRIP
value. For example, if the current V
is 4.4V and the
TRIP
new V
is 4.6V, this procedure directly makes the
TRIP
change. If the new setting is lower than the current set-
ting, then it is necessary to reset the trip point before
setting the new value.
Characteristics subject to change without notice. 3 of 21
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X5163/X5165 – Preliminary Information
Figure 3. V
Programming Sequence Flow Chart
TRIP
V
Programming
TRIP
Execute
Reset V
TRIP
Sequence
Set V
= V
Applied =
TRIP
CC
CC
Desired V
Execute
Set V
Sequence
New V
Applied =
applied + Error
New V
Applied =
CC
applied - Error
CC
TRIP
Old V
Old V
CC
CC
Execute
Apply 5V to V
CC
Reset V
TRIP
Sequence
Decrement V
= V
CC
(V
- 50mV)
CC
CC
NO
RESET pin
goes active?
YES
Error > -Emax
Error > Emax
Measured V
Desired V
–
TRIP
TRIP
Error < Emax
DONE
Emax = Maximum Desired Error
Characteristics subject to change without notice. 4 of 21
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X5163/X5165 – Preliminary Information
Figure 4. Sample V
Reset Circuit
TRIP
V
P
4.7K
NC
NC
4.7K
RESET
1
2
3
4
8
7
6
5
NC
X5163/65
V
TRIP
Adj.
+
Program
Reset V
TRIP
10K
10K
Test V
TRIP
Set V
TRIP
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8.The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Characteristics subject to change without notice. 5 of 21
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X5163/X5165 – Preliminary Information
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
WRDI/RFLB
RSDR
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
WRSR
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
WRITE
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
WD0, WD1
WEL
WPEN
WP#
Protected Block Unprotected Block
0
1
1
1
X
1
0
X
X
0
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
X
1
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
Watchdog Time Out
WD1
WD0
(Typical)
0
0
1
1
0
1
0
1
1.4 seconds
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.
600 milliseconds
200 milliseconds
disabled
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically
reset upon power up. This flag can be used by the sys-
tem to determine whether a reset occurs as a result of
a watchdog time out or power failure.
Status
Register Bits
Array Addresses Protected
X516x
BL1
BL0
0
0
1
1
0
1
0
1
None
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
$0600–$07FF
$0400–$07FF
$0000–$07FF
Characteristics subject to change without notice. 6 of 21
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X5163/X5165 – Preliminary Information
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
In Circuit Programmable ROM Mode
Read Sequence
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
Status Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
Characteristics subject to change without notice. 7 of 21
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X5163/X5165 – Preliminary Information
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
– Reset Signal is active for t
.
PURST
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Characteristics subject to change without notice. 8 of 21
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X5163/X5165 – Preliminary Information
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
6
5
4
3
2
1
0
SI
High Impedance
SO
Characteristics subject to change without notice. 9 of 21
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X5163/X5165 – Preliminary Information
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 10 of 21
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X5163/X5165 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................–65 to +135°C
Storage temperature .............................–65 to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Device Option
–2.7 or -2.7A
Supply Voltage
2.7V to 5.5V
4.5V-5.5V
–40°C
+85°C
Blank or -4.5A
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
V
V
Write Current (Active)
5
mA SCK = V x 0.1/V x 0.9 @ 2MHz,
CC CC
CC1
CC
CC
CC
SO = Open
I
Read Current (Active)
0.4
1
mA SCK = V x 0.1/V x 0.9 @ 2MHz,
CC CC
CC2
SO = Open
I
I
I
Standby Current
µA
µA
µA
CS = V , V = V or V
,
SB1
SB2
SB3
CC IN
SS
CC
WDT = OFF
V
= 5.5V
CC
V
Standby Current
50
20
CS = V , V = V or V
,
CC
CC IN
SS
CC
WDT = ON
V
= 5.5V
CC
V
Standby Current
CS = V , V = V or V
,
CC
CC IN
SS
CC
WDT = ON
V
V
V
= 3.6V
CC
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
Reset Output LOW Voltage
0.1
0.1
10
10
µA
µA
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
V
–0.5
V
x 0.3
IL
CC
(1)
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
V
V
0.4
V
V
> 3.3V, I = 2.1mA
CC OL
OL1
OL2
OL3
OH1
OH2
OH3
OLS
0.4
0.4
V
2V < VCC ≤ 3.3V, I = 1mA
OL
V
V
CC ≤ 2V, I = 0.5mA
OL
V
V
V
V
V
V
V
– 0.8
– 0.4
– 0.2
V
V
> 3.3V, I
= –1.0mA
CC
CC
CC
CC
OH
V
2V < VCC ≤ 3.3V, I
= –0.4mA
OH
V
VCC ≤ 2V, I
= –0.25mA
OH
0.4
V
I
= 1mA
OL
Characteristics subject to change without notice. 11 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
Unit
pF
Conditions
= 0V
(2)
C
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
8
6
V
OUT
OUT
(2)
C
pF
V
= 0V
IN
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
5V
Input rise and fall times
10ns
3.3KΩ
Input and output timing level
V
x0.5
CC
1.64KΩ
Output
1.64KΩ
RESET/RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
Parameter
Min.
0
Max.
Unit
MHz
ns
f
Clock Frequency
Cycle Time
2
SCK
CYC
t
500
250
250
200
200
50
t
CS Lead Time
CS Lag Time
ns
LEAD
t
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
WH
t
ns
WL
t
ns
SU
t
50
ns
H
(3)
t
t
100
100
ns
RI
(3)
ns
FI
t
500
ns
CS
(4)
t
10
ms
WC
Characteristics subject to change without notice. 12 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
Serial Input Timing
t
CS
CS
t
t
LAG
LEAD
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
2.7–5.5V
Symbol
Parameter
Min.
Max.
2
Unit
MHz
ns
f
Clock Frequency
Output Disable Time
0
SCK
t
250
200
DIS
t
Output Valid from Clock Low
Output Hold Time
ns
V
t
0
ns
HO
(3)
t
t
Output Rise Time
100
100
ns
RO
(3)
Output Fall Time
ns
FO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
SO
t
t
t
t
DIS
V
HO
WL
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
Characteristics subject to change without notice. 13 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
Power-Up and Power-Down Timing
V
V
TRIP
TRIP
V
CC
t
PURST
0 Volts
t
F
t
PURST
t
RPD
t
R
RESET (X5163)
RESET (X5165)
RESET Output Timing
Symbol
Parameter
Min. Typ. Max. Unit
V
Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7
4.5
4.63
4.38
2.92
2.63
4.75
4.5
3.0
2.7
TRIP
4.25
2.85
2.55
V
V
V
Hysteresis (HIGH to LOW vs. LOW to HIGH V voltage)
TRIP
20
mV
ms
ns
µs
µs
V
TH
TRIP
t
Power-up Reset Time Out
100
200
280
500
PURST
(5)
t
V
V
V
Detect to Reset/Output
Fall Time
RPD
CC
CC
CC
(5)
t
100
100
1
F
(5)
t
Rise Time
R
V
Reset Valid V
CC
RVALID
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) Typical values not tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
t
CST
RESET
RESET
t
t
t
t
RST
WDO
RST
WDO
Characteristics subject to change without notice. 14 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WDO
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
100
ns
CST
t
200
300
ms
RST
V
Set Conditions
TRIP
t
THD
V
V
CC
TRIP
t
TSU
t
RP
t
t
VPH
t
P
VPS
CS
t
t
t
VPO
VPH
VPS
V
P
SCK
V
t
P
VPO
SI
V
Reset Conditions
TRIP
t
THD
V
TRIP
V
CC
t
TSU
t
RP
t
t
VP1
t
P
VPS
CS
t
t
t
VPS
VPO
VPH
V
CC
SCK
SI
V
t
P
VPO
Characteristics subject to change without notice. 15 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
V
Programming Specifications: V
= 1.7–5.5V; Temperature = 0°C to 70°C
TRIP
CC
Parameter
Description
Min. Max. Unit
t
SCK V
SCK V
Program Voltage Setup time
Program Voltage Hold time
1
1
µs
µs
µs
µs
ms
ms
ms
ms
V
VPS
VPH
TRIP
t
TRIP
t
V
V
V
V
V
Program Pulse Width
1
P
TRIP
TRIP
TRIP
TRIP
TRIP
t
Level Setup time
10
10
TSU
THD
t
Level Hold (stable) time
t
Write Cycle Time
10
WC
t
Program Cycle Recovery Period (Between successive programming cycles)
10
0
RP
t
SCK V
Program Voltage Off time before next cycle
VPO
TRIP
V
Programming Voltage
Programed Voltage Range
15
1.7
18
P
V
V
5.0
V
TRAN
TRIP
V
V
Initial V
Program Voltage accuracy (V applied—V ) (Programmed at 25°C.) -0.1 +0.4
TRIP
V
ta1
ta2
TRIP
CC
Subsequent V
(Programmed at 25°C.)
Program Voltage accuracy [(V
applied—V )—V )
TRIP
-25
-25
-25
+25
+25
+25
mV
TRIP
CC
ta1
V
V
Program Voltage repeatability (Successive program operations.) (Programmed
mV
mV
tr
TRIP
at 25°C.)
V
V
TRIP
Program variation after programming (0-75°C). (Programmed at 25°C.)
tv
V
programming parameters are periodically sampled and are not 100% tested.
TRIP
Characteristics subject to change without notice. 16 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
V
Supply Current vs. Temperature (I
)
t vs. Voltage/Temperature (WD1, 0 = 1, 1)
WDO
CC
SB
1.9
1.8
18
Watchdog Timer On (V
= 5V)
CC
16
14
12
10
8
1.7
1.6
1.5
1.4
–40°C
25°C
Watchdog Timer On (V
= 5V)
CC
90°C
1.3
1.2
1.1
1
6
4
Watchdog Timer Off (V
25
= 3V, 5V)
CC
2
0
1.7
2.4
3.1
3.8
4.5
5.2
–40
90
Voltage
Temp (°C)
V
vs. Temperature (programmed at 25°C)
t
vs. Voltage/Temperature (WD1, 0 = 1, 0)
WDO
TRIP
0.8
5.025
V
= 5V
TRIP
5.000
0.75
–40°C
4.975
3.525
0.7
0.65
0.6
25°C
V
= 3.5V
= 2.5V
TRIP
TRIP
3.500
90°C
3.475
2.525
0.55
0.5
V
2.500
0.45
2.475
1.7
2.4
3.1
Voltage
3.8
4.5
5.2
0
25
85
Temperature
t
vs. Temperature
t
vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
WDO
PURST
205
200
205
200
195
190
185
180
175
170
165
–40°C
25°C
195
190
185
180
175
90°C
170
165
160
160
1.7
2.4
3.1
3.8
4.5
5.2
–40
25
90
Voltage
Degrees °C
Characteristics subject to change without notice. 17 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 18 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 21
REV 1.1 3/5/01
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X5163/X5165 – Preliminary Information
Ordering Information
V
V
Operating Temperature Part Number RESET Part Number RESET
CC
TRIP
Range
Range
Package
8-Pin PDIP
8L SOIC
Range
(Active LOW)
(Active HIGH)
4.5-5.5V
4.5.4.75
0oC - 70oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
X5163S8-4.5A
X5163S8I-4.5A
X5165S8-4.5A
14L TSSOP
4.5-5.5V
4.25.4.5
8-Pin PDIP
8L SOIC
X5163P
X5163S8
X5163S8I
X5163V14
X5165P
X5165S8
14L TSSOP
8L SOIC
2.7-5.5V
2.7-5.5V
2.85-3.0
2.55-2.7
X5163S8-2.7A
14L TSSOP
8L SOIC
X5163S8-2.7
X5163V14-2.7
X5165S8-2.7
14L TSSOP
Part Mark Information
X5163/65 W
X
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
Blank = 5V 10%, 0°C to +70°C, V
= 4.25-4.5
TRIP
A = 5V 10%, 0°C to +70°C, V
= 4.5-4.75
TRIP
I = 5V 10%, –40°C to +85°C, V
= 4.25-4.5
TRIP
IA = 5V 10%, –40°C to +85°C, V
= 4.5-4.75
= 2.55-2.7
TRIP
F = 2.7V to 5.5V, 0°C to +70°C, V
TRIP
FA = 2.7V to 5.5V, 0°C to +70°C, V
= 2.85-3.0
TRIP
G = 2.7V to 5.5V, –40°C to +85°C, V
= 2.55-2.7
TRIP
GA = 2.7V to 5.5V, –40°C to +85°C, V
= 2.85-3.0
TRIP
Characteristics subject to change without notice. 20 of 21
REV 1.1 3/5/01
www.xicor.com
X5163/X5165 – Preliminary Information
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
REV 1.1 3/5/01
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