X51638S8-2.7A [ETC]
SPI Serial EEPROM with Supervisory Features ; SPI串行EEPROM与监控功能\n
| 型号： | X51638S8-2.7A |
| 厂家： | 
ETC |
| 描述： | SPI Serial EEPROM with Supervisory Features
|
| 文件： | 总21页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X51638
CPU Supervisor with 16Kb SPI EEPROM
FEATURES
DESCRIPTION
• Extended Power-On Reset (800ms Nominal)
• Selectable Watchdog Timer
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervi-
sion, and Block Lock™ Protect Serial EEPROM in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Re-program Low Vcc Reset Threshold Voltage
using special programming sequence
—Reset Signal Valid to Vcc=1V
Applying power to the device activates a power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and oscillator to stabilize
before the processor can execute code. This device
allows 800ms before releasing the controller.
• Determine Watchdog or Low Voltage Reset with
a Volatile Flag bit
• Long Battery Life With Low Power Consumption
—<50mA Max Standby Current, Watchdog On
—<1mA Max Standby Current, Watchdog Off
—<400mA Max Active Current during Read
• 16Kbits of EEPROM
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM Array with
Block LockTM Protection
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontrol-
ler fails to restart a timer within a selectable time-out
interval, the device activates the RESET signal. The user
selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
—In Circuit Programmable ROM Mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
The X51638 low Vcc detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when Vcc falls below the minimum Vcc trip point.
RESET is asserted until Vcc returns to proper operating
level and stabilizes. Five industry standard V
thresh-
TRIP
olds are available, however, Xicor’s unique circuits allow
the thresold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• Available Packages
—14-Lead TSSOP, 8-Lead SOIC
BLOCK DIAGRAM
WATCHDOG TRANSITION
DETECTOR
WATCHDOG
TIMER RESET
WP
PROTECT LOGIC
RESET
SI
DATA
STATUS
REGISTER
SO
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET &
WATCHDOG
TIMEBASE
SCK
4K BITS
4K BITS
CS/WDI
VCC THRESHOLD
RESET LOGIC
8K BITS
POWER ON AND
LOW VOLTAGE
RESET
V
+
-
CC
GENERATION
V
TRIP
ÓXicor, Inc. 1999 Patents Pending
9900-3002.10 2/12/99 T0/C0/D0
Characteristics subject to change without notice
1
X51638
PIN DESCRIPTION
PIN
PIN
(SOIC/PDIP)
TSSOP
Name
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin
is at a high impedance state. Unless a nonvolatile write cycle is underway,
the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after
power up, a HIGH to LOW transition on CS is required
1
1
CS/WDI
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time-out period results in RESET going active.
Serial Output. SO is a push/pull serial data output pin.A read cycle shifts data
out on this pin.The falling edge of the serial clock (SCK) clocks the data out.
2
5
2
8
SO
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses,
and memory data on this pin.The rising edge of the serial clock (SCK) latches
the input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output.The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin.The falling edge of SCK changes the data output on the
SO pin.
6
3
9
6
SCK
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN
bit to “lock” the setting of the Watchdog Timer control and the memory write
protect bits.
V
4
8
7
Ground
SS
V
14
Supply Voltage
CC
Reset Output. RESET is an active LOW open drain output which goes
active whenever Vcc falls below the minimum Vcc sense level. It will
remain active until Vcc rises above the minimum Vcc sense level for
800ms. RESET goes active if the Watchdog Timer is enabled and CS
remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge of CS will reset the Watchdog Timer. RESET goes
active on power up at 1V and remains active for 800ms after the power
supply stabilizes.
7
13
RESET
NC
3-5,10-12
No internal connections
PIN CONFIGURATION
14-LEAD TSSOP
X51638
8-LEAD SOIC/PDIP
X51638
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CS
SO
NC
CC
RESET
NC
V
1
2
3
4
8
7
6
5
CS
SO
WP
CC
RESET
SCK
SI
NC
NC
WP
NC
NC
V
SS
SCK
SI
V
SS
8
2
X51638
PRINCIPLES OF OPERATION
To set the new V
voltage, apply the desired V
TRIP TRIP
threshold to the Vcc pin and tie the CS/WDI pin and the
WP pin HIGH. RESET and SO pins are left unconnected.
Then apply the programming voltage Vp to both SCK and
SI and pulse CS/WDI LOW then HIGH. Remove Vp and
the sequence is complete.
POWER ON RESET
Application of power to the X51638 activates a Power On
Reset Circuit. This circuit goes active at V
sense level
CC
(V
) and pulls the RESET pin LOW. This signal pre-
TRIP
vents the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the oscil-
Figure 1. Set V
Voltage
TRIP
lator. When Vcc exceeds the device V
value for
TRIP
800ms (nominal) the circuit releases RESET, allowing the
processor to begin executing code.
CS
Vp
SCK
LOW VOLTAGE MONITORING
During operation, the X51638 monitors the V level and
asserts RESET if supply voltage falls below a preset mini-
CC
Vp
SI
mum V
. The RESET signal prevents the microproces-
TRIP
sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
Resetting the V
Voltage
TRIP
exceeds V
for 800ms.
TRIP
This procedure sets the V
to a “native” voltage level.
TRIP
For example, if the current V
is 4.4V and the V
is
TRIP
TRIP
WATCHDOG TIMER
reset, the new V
is something less than 1.7V. This
TRIP
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Status Register determine the watchdog timer period.The
microprocessor can change these watchdog bits, or they
may be “locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
procedure must be used to set the voltage to a lower
value.
To reset the V
voltage, apply a voltage between 2.7
TRIP
and 5.5V to the Vcc pin. Tie the CS/WDI pin, the WP pin,
AND THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage Vp to
the SI pin ONLY and pulse CS/WDI LOW then HIGH.
Remove Vp and the sequence is complete.
Figure 2. Reset V
Voltage
TRIP
VCC THRESHOLD RESET PROCEDURE
The X51638 is offered with one of several standard Vcc
CS
threshold (V
) voltages. This value will not change
TRIP
Vcc
over normal operating and storage conditions. However,
in applications where the standard V is not exactly
SCK
TRIP
right, or for higher precision in the V
X51638 threshold may be adjusted.
value, the
TRIP
Vp
SI
Setting the V
Voltage
TRIP
This procedure sets the V
to a higher voltage value.
TRIP
For example, if the current V
is 4.4V and the new
TRIP
V
is 4.6V, this procedure directly makes the change. If
TRIP
the new setting is lower than the current setting, then it is
necessary to reset the trip point before setting the new
value.
3
X51638
Figure 3. V
Programming Sequence Flow Chart
TRIP
V
Programming
TRIP
Execute
Reset V
TRIP
Sequence
Set Vcc = Vcc applied =
Desired V
TRIP
Execute
New Vcc applied =
Old Vcc applied + Error
New Vcc applied =
Old Vcc applied - Error
Set V
TRIP
Sequence
Apply 5V to Vcc
Execute
Reset V
TRIP
Sequence
Decrement Vcc
(Vcc = Vcc - 50mV)
NO
RESET pin
goes active?
YES
Error < 0
Error > 0
Measured V
-
TRIP
TRIP
Desired V
Error = 0
DONE
Figure 4. Sample V
Reset Circuit
TRIP
V
P
4.7K
RESET
NC
NC
4.7K
X51638
1
2
3
4
8
7
6
5
NC
V
TRIP
Adj.
+
Program
V
TRIP
Reset
10K
10K
V
TRIP
Test
V
TRIP
Set
4
X51638
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 3). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families. It contains an 8-bit instruction
register that is accessed via the SI input, with data being
clocked in on the rising edge of SCK. CS must be LOW
during the entire operation.
7
6
5
4
3
2
1
0
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
WRDI/RFLB
RSDR
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
WRSR
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
WRITE
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
STATUS
REGISTER
DEVICE
PIN
STATUS
REGISTER
WREN CMD
BLOCK
BLOCK
WPEN, BL0, BL1
WD0, WD1
Protected
PROTECTED
BLOCK
UNPROTECTED
BLOCK
WEL
WPEN
WP#
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Writable
5
X51638
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
Status Register Bits
Watchdog Time-out
(Typical)
WD1
WD0
0
0
1
1
0
1
0
1
1.4 Seconds
600 Milliseconds
400 Milliseconds
Disabled
The Block Lock bits, BL0 and BL1, set the level of Block
LockTM Protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is Block Lock
Protected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable Block Lock
Protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that can
be set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon
power up. This flag can be used by the system to deter-
mine whether a reset occurs as a result of a watchdog
time-out or power failure.
Status
Register Bits
Array Addresses Protected
X516x
BL1
BL0
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all Status Register Write Operations.
0
0
1
1
0
1
0
1
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
In Circuit Programmable ROM Mode
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption.
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”.This mode
disables nonvolatile writes to the device’s Status Register.
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
6
X51638
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused
address bits are specified to be “0’s”. The WRITE opera-
tion minimally takes 32 clocks. CS must go low and
remain low for the duration of the operation. If the
address counter reaches the end of a page and the clock
continues, the counter will roll back to the first address of
the page and overwrite any data that may have been pre-
viously written.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.
Setting the WPEN bit in the Status Register to “0” blocks
the WP pin function, allowing writes to the Status Regis-
ter when WP is HIGH or LOW. Setting the WPEN bit to
“1” while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin prior
to subsequent Status Register changes. This allows
manufacturing to install the device in a system with WP
pin grounded and still be able to program the Status Reg-
ister. Manufacturing can then load Configuration data,
manufacturing time and other parameters into the
EEPROM, then set the portion of memory to be pro-
tected by setting the Block Lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0” .
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS high. Refer to the Read EEPROM Array Sequence
(Figure 1).
While the write is in progress following a Status Register
or EEPROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
OPERATIONAL NOTES
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for t
.
PURST
To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
• CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
7
X51638
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
8
X51638
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
7
6
5
4
3
2
1
0
SI
HIGH IMPEDANCE
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
9
X51638
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ........................–65°Cto+135°C
Storage Temperature .............................–65°Cto+150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ....... –1.0V to +7V
SS
D.C. Output Current ....................................................5mA
Lead Temperature (Soldering, 10 seconds)............ 300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
70°C
Voltage Option
–1.8
Supply Voltage
1.8V-3.6V
Commercial
Industrial
–40°C
+85°C
–2.7 or -2.7A
Blank or -4.5A
2.7V to 5.5V
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions
SCK = V
SO = Open
x 0.1/V
x 0.9 @ 2MHz,
CC
CC
I
V
Write Current (Active)
5
mA
mA
CC1
CC
SCK = V
x 0.1/V
x 0.9 @ 2MHz,
CC
CC
I
V
V
Read Current (Active)
Standby Current
0.4
CC2
CC
CC
SO = Open
CS = V , V = V or V
,
,
CC IN
SS
CC
CC
I
1
µA
µA
µA
SB1
WDT=OFF
V
= 5.5V
CC
CS = V , V = V or V
CC IN
SS
V
Standby Current
CC
I
50
20
SB2
V
= 5.5V
WDT=ON
CC
CS = V , V = V or V
,
V
Standby Current
CC IN
SS
CC
CC
I
SB3
WDT=ON
V
V
V
=3.6V
CC
I
= V to V
SS CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
0.1
0.1
10
10
µA
µA
V
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
V
V
V
x0.3
–0.5
CC
IL
(1)
V
V
x0.7
+0.5
CC
V
V
V
V
V
V
V
V
CC
IH
V
V
> 3.3V, I = 2.1mA
CC OL
0.4
OL1
V
2V < VCC £ 3.3V, I = 1mA
0.4
0.4
OL2
OL
V
V
V
CC £ 2V, I = 0.5mA
OL
OL3
V
V
V
V
–0.8
–0.4
–0.2
> 3.3V, I
= –1.0mA
CC
CC
CC
OH1
CC
OH
V
2V < VCC £ 3.3V, I
= –0.4mA
OH2
OH
V
V
I
CC £ 2V, I
= –0.25mA
OH3
OH
= 1mA
V
Reset Output LOW Voltage
0.4
OL
OLS
10
X51638
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Max.
Units
pF
Conditions
= 0V
(2)
8
6
V
OUT
Output Capacitance (SO, RESET)
C
OUT
(2)
pF
V
= 0V
Input Capacitance (SCK, SI, CS, WP)
C
IN
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
V
x 0.1 to V x 0.9
Input Pulse Levels
CC
CC
5V
5V
Input Rise and Fall Times
Input and Output Timing Level
10ns
3.3KW
1.64KW
V
x 0.5
CC
SO
OUTPUT
RESET
1.64KW
30pF
100pF
11
X51638
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
1.8-3.6V
Max.
2.7-5.5V
Max.
Symbol
SCK
CYC
LEAD
LAG
WH
Parameter
Clock Frequency
Cycle Time
Min.
0
Min.
0
Units
MHz
ns
f
t
t
t
t
t
t
t
1
2
1000
500
500
400
400
50
500
250
250
200
250
50
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
ns
ns
WL
ns
SU
50
50
ns
H
(3)
RI
t
t
t
t
Input Rise Time
Input Fall Time
100
100
100
100
ns
ns
ns
ms
(3)
FI
CS Deselect Time
Write Cycle Time
500
500
CS
(4)
10
10
WC
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
12
X51638
Serial Output Timing
1.8-3.6V
Min.
2.7-5.5V
Min.
Symbol
Parameter
Clock Frequency
Max.
1
Max.
2
Units
MHz
ns
f
t
t
t
0
0
SCK
DIS
V
Output Disable Time
Output Valid from Clock Low
Output Hold Time
250
400
250
250
ns
0
0
ns
HO
(3)
t
Output Rise Time
100
100
100
100
ns
ns
RO
(3)
t
Output Fall Time
FO
Notes:
(3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
WC
nonvolatile write cycle.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
13
X51638
Power-Up and Power-Down Timing
V
V
TRIP
TRIP
VCC
t
PURST
0 Volts
t
t
PURST
F
t
RPD
t
R
RESET
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
Reset Trip Point Voltage, X51638-4.5A
Reset Trip Point Voltage, X51638
Reset Trip Point Voltage, X51638-2.7A
Reset Trip Point Voltage, X51638-2.7
Reset Trip Point Voltage, X51638-1.8
4.5
4.25
2.85
2.55
1.7
4.62
4.38
2.92
2.62
1.75
4.75
4.5
3.0
2.7
1.8
V
V
TRIP
V
Hysteresis
TRIP
(5)
V
t
20
mV
TH
(HIGH to LOW vs. LOW to HIGH V
voltage)
TRIP
Power-up Reset Timeout
500
800
1400
500
ms
ns
ms
ms
V
PURST
(5)
V
V
V
Detect to Reset/Output
Fall Time
t
t
t
CC
CC
CC
RPD
(5)
F
100
100
1
(5)
R
Rise Time
V
Reset Valid V
CC
RVALID
Notes: (5) This parameter is periodically sampled and not 100% tested.
14
X51638
CS/WDI vs. RESET Timing
CS/WDI
RESET
t
CST
t
t
t
t
WDO
RST
WDO
RST
RESET Output Timing (WD1 = 1, WD0 = 0)
Symbol
WDO
Parameter
Min.
300
400
200
Typ.
Max.
Units
ms
t
t
t
Watchdog Timeout Period
400
550
CS Pulse Width to Reset the Watchdog
Reset Timeout
ns
CST
400
600
ms
RST
RESET Output Timing (WD1 = 0, WD0 = 1)
Symbol
WDO
Parameter
Watchdog Timeout Period
CS Pulse Width to Reset the Watchdog
Reset Timeout
Min.
450
400
100
Typ.
Max.
Units
ms
t
t
t
600
800
ns
CST
200
300
ms
RST
RESET Output Timing (WD1 = 0, WD0 = 0)
Symbol
WDO
Parameter
Watchdog Timeout Period
CS Pulse Width to Reset the Watchdog
Reset Timeout
Min.
1
Typ.
Max.
Units
sec
ns
t
t
t
1.4
2
400
100
CST
200
300
ms
RST
15
X51638
V
Set Conditions
TRIP
t
THD
Vcc
V
Trip
t
TSU
t
RP
t
t
VPH
t
P
VPS
CS
t
t
t
VPO
VPH
VPS
Vp
Vp
SCK
t
VPO
SI
V
Reset Conditions
TRIP
t
THD
V
Trip
Vcc
CS
t
TSU
t
RP
t
t
VP1
t
P
VPS
t
t
t
VPS
VPO
VPH
Vcc
Vp
SCK
SI
t
VPO
16
X51638
Table 3. V
Programming Specifications: Vcc=1.7-5.5V; Temperature = 0oC to 70oC
TRIP
Parameter
Description
Min
1
Max
Units
ms
t
SCK V
SCK V
Program Voltage Setup time
VPS
TRIP
t
Program Voltage Hold time
1
ms
VPH
TRIP
t
V
Program Pulse Width
Level Setup time
1
ms
P
TRIP
t
V
10
10
ms
TSU
TRIP
t
V
Level Hold (stable) time
Write Cycle Time
ms
ms
THD
TRIP
t
V
10
WC
TRIP
V
Program Cycle Recovery Period
TRIP
t
10
ms
RP
(Between successive programming cycles)
t
SCK V Program Voltage Off time before next cycle
0
ms
V
VPO
TRIP
Vp
Programming Voltage
15
18
5.0
V
V
V
V
Programed Voltage
1.7
-0.3
V
TRIP
TRIP
TRIP
TRIP
Programed Voltage accuracy (Vcc applied - V
)
Vta
Vtr
+0.3
V
TRIP
Programed Voltage repeatability
-5
+5
mV
(Successive program operations.)
V
Programming parameters are periodically sampled and are not 100% Tested.
TRIP
17
X51638
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45°
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
X51638
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
X51638
Ordering Information
Operating
Temperature Range
PART NUMBER
RESET (Active LOW)
V
Range
Vcc Range
Package
TRIP
0oC - 70oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
0oC - 70oC
-40oC - 85oC
0°c - 70°C
0oC - 70oC
-40oC - 85oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
8 pin PDIP
X51638P-4.5A
X51638S8-4.5A
X51638S8I-4.5A
X51638P
4.5-5.5V
4.5-4.75
8L SOIC
8 pin PDIP
8L SOIC
X51638S8
4.5-5.5V
2.7-5.5V
4.25-4.5
2.85-3.0
X51638S8I
14L TSSOP
8L SOIC
X51638V14
X51638S8-2.7A
X51638S8I-2.7A
X51638V14-2.7A
X51638S8-2.7
X51638V14-2.7
X51638S8-1.8
X51638V14-1.8
14L TSSOP
8L SOIC
2.7-5.5V
1.8-3.6V
2.55-2.7
1.7-1.8V
14L TSSOP
8L SOIC
14L TSSOP
Part Mark Information
X51638
W
X
P = 8-Pin DIP
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
Blank = 5V ±10%, 0°C to +70°C, V
=4.25-4.5
TRIP
AL=5V±10%, 0°C to +70°C, V
= 4.5-4.75
TRIP
I = 5V ±10%, –40°C to +85°C, V
=4.25-4.5
TRIP
AM = 5V ±10%, –40°C to +85°C, V
=4.5-4.75
TRIP
F = 2.7V to 5.5V, 0°C to +70°C, V
=2.55-2.7
TRIP
AN = 2.7V to 5.5V, 0°C to +70°C, V
=2.85-3.0
TRIP
G = 2.7V to 5.5V, –40°C to +85°C, V
=2.55-2.7
TRIP
AP = 2.7V to 5.5V, –40°C to +85°C, V
=2.85-3.0
TRIP
AG = 1.8V to 3.6V, 0°C to +70°C, V
=1.7-1.8
TRIP
AH = 1.8V to 3.6V, –40°C to +85°C, V
=1.7-1.8
TRIP
20
X51638
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
21
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