W39V040FAQ_技术文档

W39V040FA

512K × 8 CMOS FLASH MEMORY

WITH FWH INTERFACE

1. GENERAL DESCRIPTION

The W39V040FA is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For

flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are

composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased in-

system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture

of the W39V040FA results in fast program/erase operations with extremely low current consumption.

This device can operate at two modes, Programmer bus interface mode and FWH bus interface

mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed

address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification.

The device can also be programmed and erased using standard EPROM programmers.

2. FEATURES

• Single 3.3-volt operations:

− 3.3-volt read

− 3.3-volt erase

• Hardware protection:

− Optional 16K byte or 64K byte Top Boot

Block with lockout protection

− #TBL & #WP support the whole chip

− 3.3-volt program

hardware protection

• Fast Program operation:

− Byte-by-Byte programming: 35 µS (typ.)

• Fast erase operation:

• Flexible 4K-page size can be used as

Parameter Blocks

• Low power consumption

− Chip erase 100 mS (max.)

− Sector erase 25 mS (max.)

− Page erase 25 mS (max.)

• Fast Read access time: Tkq 11 nS

• Endurance: 10K cycles (typ.)

• Twenty-year data retention

− Active current: 12.5 mA (typ. for FWH mode)

• Automatic program and erase timing with

internal VPP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• 8 Even sectors with 64K bytes each, which is

composed of 16 flexible pages with 4K bytes

• Any individual sector or page can be erased

• Available packages: 32L PLCC, 32L STSOP,

40L TSOP (10 x 20 mm)

Publication Release Date: December 19, 2002

- 1 -

Revision A2

W39V040FA

3. PIN CONFIGURATIONS

4. BLOCK DIAGRAM

7FFFF

#WP

BOOT BLOCK 64K BYTES

Optional

16KBytes

as

#TBL

A

FWH

70000

6FFFF

A

8

^

A

9

^

R

/

1

0

^

CLK

Interface

FWH[3:0]

FWH4

MAIN MEMORY BLOCK6

64K BYTES

Boot Block

#

C

^

#

R

E

S

E

T

F

G

P

I

F

G

P

I

F

G

P

I

60000

5FFFF

7C000

7BFFF

4K Page

C

L

K

v

MAIN MEMORY BLOCK5

64K BYTES

V

D

IC

#INIT

N

C

2

v

3

v

4

v

50000

4FFFF

MAIN MEMORY BLOCK4

64K BYTES

#RESET

3

4

2

1

32 31 30

40000

3FFFF

4K Page

MAIN MEMORY BLOCK3

64K BYTES

29

28

27

26

25

24

23

22

21

A7(FGPI1)

A6(FGPI0)

A5(#WP)

A4(#TBL)

A3(ID3)

5

6

IC

R/#C

A[10:0]

DQ[7:0]

30000

2FFFF

VSS

NC

4K Page

MAIN MEMORY BLOCK2

64K BYTES

7

Program-

mer

20000

1FFFF

8

NC

Interface

4K Page

MAIN MEMORY BLOCK1

64K BYTES

9

VDD

32L PLCC

#OE

#WE

10000

0FFFF

10

11

12

13

#OE(#INIT)

#WE(FWH4)

NC

A2(ID2)

MAIN MEMORY BLOCK0

64K BYTES

A1(ID1)

70000

00000

A0(ID0)

DQ7(RSV)

DQ0(FWH0)

14 15 16 17 18 19 20

D

Q

1

D

Q

2

D

Q

5

D

Q

3

D

Q

4

D

Q

6

V

S

^

F

W

H

1

F

W

H

2

R

S

V

v

F

W

H

3

R

S

V

v

R

S

V

v

5. PIN DESCRIPTION

v

INTERFACE

SYM.

PIN NAME

PGM FWH

32

31

30

29

28

27

26

25

#OE(#INIT)

NC

1

IC

#RESET

#INIT

#TBL

#WP

*

Interface Mode Selection

Reset

Initialize

Top Boot Block Lock

Write Protect

CLK Input

2

#WE(FWH4)

NC

3

V

DD

VSS

4

DQ7(RSV)

DQ6(RSV)

DQ5(RSV)

DQ4(RSV)

DQ3(FWH3)

VSS

IC

5

A10(FGPI4)

6

7

R/#C(CLK)

VDD

8

32L STSOP

24

23

22

21

20

19

18

17

NC

9

#RESET

A9(FGPI3)

A8(FGPI2)

10

11

12

13

14

15

16

DQ2(FWH2)

DQ1(FWH1)

DQ0(FWH0)

A0(ID0)

A7(FGPI1)

A6(FGPI0)

A5(#WP)

A1(ID1)

A2(ID2)

A3(ID3)

A4(#TBL)

CLK

FGPI[4:0]

General Purpose Inputs

Identification Inputs They

Are Internal Pull Down to

Vss

40

39

VSS

VDD

1

2

3

4

5

6

7

NC

IC

NC

ID[3:0]

*

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

#WE(FWH4)

NC

#OE(#INIT)

NC

FWH[3:0]

FWH4

R/#C

A[10:0]

DQ[7:0]

#OE

#WE

VDD

VSS

RSV

*

Address/Data Inputs

FWH Cycle Initial

Row/Column Select

Address Inputs

Data Inputs/Outputs

Output Enable

Write Enable

Power Supply

Ground

Reserved Pins

No Connection

NC

DQ7(RSV)

NC

DQ6(RSV)

DQ5(RSV)

DQ4(RSV)

VDD

VSS

A10(FGPI4)

NC

CLK

VDD

NC

#RESET

NC

A9(FGPI3)

A8(FGPI2)

A7(FGPI1)

A6(FGPI0)

A5(#WP)

A4(#TBL)

8

9

*

10

40L TSOP

11

12

13

14

15

16

17

18

DQ3(FWH3)

DQ2(FWH2)

DQ1(FWH1)

DQ0(FWH0)

A0(ID0)

A1(ID1)

A2(ID2)

A3(ID3)

19

20

*

NC

- 2 -

W39V040FA

6. FUNCTIONAL DESCRIPTION

Interface Mode Selection and Description

This device can operate in two interface modes, one is Programmer interface mode, and the other is

FWH interface mode. The IC pin of the device provides the control between these two interface

modes. These interface modes need to be configured before power up or return from #RESET. When

IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low

state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just

behaves like traditional flash parts with 8 data lines. But the row and column address inputs are

multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column

address are mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH

Interface Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W39V040FA is controlled by #OE

(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).

#OE is the output control and is used to gate data from the output pins. The data bus is in high

impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined

by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for

further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the

device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all

outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device

will return to read or standby mode, it depends on the control signals.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this

device can be locked as boot block, which can be used to store boot codes. It is located in the last

16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the

data for the designated block cannot be erased or programmed (programming lockout), other memory

locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other

sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will

not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not

be programmed/erased.

In order to detect whether the boot block feature is set on or not, users can perform software

command sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address

7FFF2(hex). If the DQ0/DQ1 output data is "1," the 64Kbytes/16Kbytes boot block programming

lockout feature will be activated; if the DQ0/DQ1 output data is "0," the lockout feature will be

inactivated and the boot block can be erased/programmed. But the hardware protection will override

the software lock setting, i.e., while the #TBL pin is trapped at low state, the top boot block cannot be

Publication Release Date: December 19, 2002

- 3 -

Revision A2

W39V040FA

programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL

will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can

check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If

the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can

be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it

means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.

Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in

high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if

the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited.

To return to normal operation, perform a three-byte command sequence (or an alternate single-byte

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed within fast 100 mS (max). The host system is not required to provide any control or timing

during this operation. If the boot block programming lockout is activated, only the data in the other

memory sectors will be erased to FF(hex) while the data in the boot block will not be erased (remains

as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)

by the chip erase operation if the boot block programming lockout feature is not activated. The device

will automatically return to normal read mode after the erase operation completed. Data polling and/or

Toggle Bits can be used to detect end of erase cycle.

Sector/Page Erase Command

Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by

writing the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase

command. The sector/page address (any address location within the desired sector/page) is latched

on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE.

Sector/page erase does not require the user to program the device prior to erase. When erasing a

sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is

not required to provide any controls or timings during these operations.

The automatic sector/page erase begins after the erase command is completed, right from the rising

edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data

on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be

performed at an address within any of the sectors/pages being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.

Program Operation

The W39V040FA is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or

boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the byte-

program command is entered. The internal program timer will automatically time-out (50 µS max. -

TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be

used to detect end of program cycle.

- 4 -

W39V040FA

Hardware Data Protection

The integrity of the data stored in the W39V040FA is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is

less than 1.5V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W39V040FA includes a data polling feature to indicate the end of a program or erase cycle.

When the W39V040FA is in the internal program or erase cycle, any attempts to read DQ7 of the last

byte loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle,

and when erase cycle has been completed it becomes logical "1" or true data.

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W39V040FA provides another method for determining the end of a

program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between

0's and 1's will stop. The device is then ready for the next operation.

Register

There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock

Control Registers and Product Identification Registers. Users can access these registers through

respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.

General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W39V040FA.This is a pass-through register which can

read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.

GPI Register Table

BIT

7 − 5

FUNCTION

Reserved

4

3

2

1

0

Read FGPI4 pin status

Read FGPI3 pin status

Read FGPI2 pin status

Read FGPI1 pin status

Read FGPI0 pin status

Publication Release Date: December 19, 2002

Revision A2

- 5 -

W39V040FA

Block Locking Registers

This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These

control registers can be set or clear through memory address. Below is the detail description.

Block Locking Registers type and access memory map Table

REGISTERS

CONTROL

DEVICE PHYSICAL

4GBYTES SYSTEM

MEMORY ADDRESS

REGISTERS

TYPE

BLOCK

ADDRESS

BLR7

BLR6

BLR5

BLR4

BLR3

BLR2

BLR1

BLR0

R/W

7

6

5

4

3

2

1

0

7FFFFh – 70000h

6FFFFh – 60000h

5FFFFh – 50000h

4FFFFh – 40000h

3FFFFh – 30000h

2FFFFh – 20000h

1FFFFh – 10000h

0FFFFh – 00000h

FFBF0002h

FFBE0002h

FFBD0002h

FFBC0002h

FFBB0002h

FFBA0002h

FFB90002h

FFB80002h

Block Locking Register Bits Function Table

BIT

FUNCTION

7 – 3

Reserved

Read Lock

1: Prohibit to read in the block where set

2

0: Normal read operation in the block where clear. This is default state.

Lock Down

1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down

Bit can only be set not clear. Only the device is reset or re-powered, the Lock

Down Bit is cleared.

0: Normal operation for Read Lock or Write Lock. This is the default state.

Write Lock

1: Prohibited to write in the block where set. This is default state.

0: Normal programming/erase operation in the block where clear.

1

0

Register Based Block Locking Value Definitions Table

BIT [7:3]

00000

BIT 2

BIT 1

BIT 0

RESULT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Full Access.

Write Lock. Default State.

Locked Open (Full Access, Lock Down).

Write Locked, Locked Down.

Read Locked.

Read & Write Locked.

Read Locked, Locked Down.

Read & Write Locked, Locked Down.

- 6 -

W39V040FA

Read Lock

Any attempt to read the data of read locked block will result in “00.” The default state of any block is

unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit

is not set.

Write Lock

This is the default state of blocks upon power up. Before any program or erase to the specified block,

user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the

lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP &

TBL. When hardware protect pins are enabled, it will override the register block locking functions and

write lock the blocks no matter how the status of the register bits. Reading the register bit will not

reflect the status of the #WP or #TBL pins.

Lock Down

The default state of lock down bit for any block is unlocked. This bit can be set only once; any further

attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit.

Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be

set or cleared, and keep its current state.

Product Identification Registers

In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code,

DA(hex). A read from FFBC, 0001(hex) can output the device code 34(hex).

There is an alternative software method (six commands bytes) to read out the Product Identification in

both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment

can automatically matches the device with its proper erase and programming algorithms.

In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to

access the product ID for programmer interface mode. A read from address 0000(hex) outputs the

manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 34(hex).” The

product ID operation can be terminated by a three-byte command sequence or an alternate one-byte

command sequence (see Command Definition table for detail).

Table of Operating Mode

Operating Mode Selection - Programmer Mode

PINS

MODE

ADDRESS

DQ.

#OE

VIL

VIH

X

#WE

VIH

VIL

X

#RESET

VIH

Read

Write

AIN

X

Dout

Din

VIH

VIL

Standby

High Z

VIL

X

VIH

X

VIH

X

VIH

X

High Z/DOUT

High Z

Write Inhibit

Output Disable

Publication Release Date: December 19, 2002

Revision A2

- 7 -

W39V040FA

Operating Mode Selection - FWH Mode

Operation modes in FWH interface mode are determined by "START Cycle" when it is selected.

When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle

Definition".

Table of Command Definition

COMMAND

DESCRIPTION

Read

Chip Erase

Sector Erase

Page Erase

Byte Program

NO. OF

1ST CYCLE

Addr. Data

A_IND_OUT

5555 AA

2ND CYCLE

Addr. Data

3RD CYCLE

Addr. Data

4TH CYCLE

Addr. Data

5TH CYCLE

Addr. Data

6TH CYCLE

Addr. Data

Cycles (1)

1

6

4

2AAA 55

5555 80

5555 A0

5555 AA

A_IND_IN

2AAA 55

5555 10

SA⁽⁵⁾30

PA⁽⁶⁾50

Top Boot Block

Lockout –

6

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 40/70

64K/16KByte

Product ID Entry

Product ID Exit ⁽⁴⁾

Notes:

3

1

5555 AA

XXXX F0

2AAA 55

5555 90

5555 F0

1. The cycle means the write command cycle not the FWH clock cycle.

2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address

A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]

3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)

4. Either one of the two Product ID Exit commands can be used.

5. SA: Sector Address

SA = 7XXXXh for Unique Sector7 (Boot Sector)

SA = 6XXXXh for Unique Sector6

SA = 5XXXXh for Unique Sector5

SA = 3XXXXh for Unique Sector3

SA = 2XXXXh for Unique Sector2

SA = 1XXXXh for Unique Sector1

SA = 0XXXXh for Unique Sector0

SA = 4XXXXh for Unique Sector4

6. PA : Page Address

PA = 7FXXXh for Page 15 in Sector 7

PA = 7EXXXh for Page 14 in Sector 7

PA = 7DXXXh for Page 13 in Sector 7

PA = 7CXXXh for Page 12 in Sector 7

PA = 7BXXXh for Page 11 in Sector 7

PA = 7AXXXh for Page 10 in Sector 7

PA = 79XXXh for Page 9 in Sector 7

PA = 78XXXh for Page 8 in Sector 7

PA = 77XXXh for Page 7 in Sector 7

PA = 76XXXh for Page 6 in Sector 7

PA = 75XXXh for Page 5 in Sector 7

PA = 74XXXh for Page 4 in Sector 7

PA = 73XXXh for Page 3 in Sector 7

PA = 72XXXh for Page 2 in Sector 7

PA = 71XXXh for Page 1 in Sector 7

PA = 70XXXh for Page 0 in Sector 7

PA =

6FXXXh

to

PA =

5FXXXh

to

PA =

4FXXXh

to

PA =

3FXXXh

to

PA =

2FXXXh

to

PA =

1FXXXh

to

PA =

0FXXXh

to

60XXXh

for

50XXXh

for

40XXXh

for

30XXXh

for

20XXXh

for

10XXXh

for

00XXXh

for

Page 15

to

Page 0

In

Page 0

In

Page 0

In

Page 0

In

Page 0

In

Page 0

In

Page 0

In

Sector 6

Sector 5

Sector 4

Sector 3

Sector 2

Sector 1

Sector 0

(Reference (Reference (Reference (Reference (Reference (Reference (Reference

to the

first

column)

to the

first

column)

to the

first

column)

to the

first

column)

to the

first

column)

to the

first

column)

first

column)

- 8 -

W39V040FA

FWH Cycle Definition

NO. OF

FIELD

DESCRIPTION

CLOCKS

"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH

Memory Write cycle. 0000b" appears on FWH bus to indicate the initial

START

1

IDSEL

MSIZE

TAR

1

2

This one clock field indicates which FWH component is being selected.

Memory Size. There is always show “0000b” for single byte access.

Turned Around Time

Address Phase for Memory Cycle. FWH supports the 28 bits address

protocol. The addresses transfer most significant nibble first and least

significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and

Address[3:0] on FWH[3:0] last.)

ADDR

7

Synchronous to add wait state. "0000b" means Ready, "0101b" means

Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"

means error, and other values are reserved.

Data Phase for Memory Cycle. The data transfer least significant nibble

first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then

DQ[7:4] on FWH[3:0] last.)

SYNC

DATA

N

2

Publication Release Date: December 19, 2002

- 9 -

Revision A2

W39V040FA

Embedded Programming Algorithm

Start

Write Program Command Sequence

(see below)

Pause

BP

T

#Data Polling/ Toggle bit

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence (Address/Command):

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program Data

- 10 -

W39V040FA

Embedded Erase Algorithm

Start

Write Erase Command Sequence

(see below)

#Data Polling or Toggle Bit

Successfully Completed

EC SEC PEC

Pause T /T

/T

Erasure Completed

Chip Erase Command Sequence

(Address/Command):

Individual Page Erase

Command Sequence

(Address/Command):

Individual Sector Erase

Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/10H

5555H/AAH

2AAAH/55H

5555H/AAH

2AAAH/55H

Page Address/50H

Sector Address/30H

Publication Release Date: December 19, 2002

Revision A2

- 11 -

W39V040FA

Embedded #Data Polling Algorithm

Start

VA = Byte address for programming

= Any of the sector addresses within

the sector being erased during sector

erase operation

Read Byte

(DQ0 - DQ7)

Address = VA

= Any of the page addresses within

the page being erased during page

erase operation

= Any of the device addresses being erased

during chip erase operation

No

DQ7 = Data

?

Yes

Pass

Embedded Toggle Bit Algorithm

Start

Read Byte

(DQ0 - DQ7)

Address = Don't Care

Yes

DQ6 = Toggle

?

No

Pass

- 12 -

W39V040FA

Software Product Identification and Boot Block Lockout Detection Acquisition

Flow

Product

Identification

and Boot Block

Lockout Detection

Mode (3)

Identification

Entry (1)

Identification Exit(6)

Load data AA

to

Load data AA

to

address 5555

(2)

Load data 55

to

Load data 55

to

Read address = 00000

data = DA

address 2AAA

(2)

(4)

Load data 90

to

Load data F0

to

Read address = 00001

data = 34

address 5555

Read address = 7FFF2

Pause 10 S

µ

Check DQ[3:0] of data

outputs

(5)

Normal Mode

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)

(2) A1 − A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block lockout detection mode if power down.

(4) The DQ[3:0] to indicate the sectors protect status as below:

DQ0

DQ1

DQ2

DQ3

64Kbytes Boot Block

Unlocked by #TBL

hardware trapping

Whole Chip Unlocked by #WP

hardware trapping Except Boot

Block

64K Boot Block

16Kbytes Boot Block

Unlocked by Software

0

1

Unlocked by Software

64Kbytes Boot Block

Locked by #TBL hardware

trapping

Whole Chip Locked by #WP

hardware trapping Except Boot

Block

64K Boot Block

16Kbytes Boot Block

Locked by Software

(5) The device returns to standard operation mode.

(6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout

detection.

Publication Release Date: December 19, 2002

- 13 -

Revision A2

W39V040FA

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA

to

address 5555

Load data 55

to

Pause T_BP

Exit

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40/70

to

40 to lock 64K Boot Block

70 to lcok 16K Boot Block

address 5555

- 14 -

W39V040FA

7. DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

Power Supply Voltage to VSS Potential

Operating Temperature

RATING

-0.5 to +4.6

0 to +70

UNIT

V

°C

V

Storage Temperature

-65 to +150

-0.5 to VDD +0.5

-1.0 to VDD +0.5

D.C. Voltage on Any Pin to Ground Potential

Transient Voltage (<20 nS) on Any Pin to Ground Potential

V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability

of the device.

Programmer interface Mode DC Operating Characteristics

(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)

LIMITS

MIN. TYP.

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MAX.

In Read or Write mode, all DQs open

Address inputs = 3.0V/0V, at f = 3 MHz

mA

Power Supply

Current

ICC

ILI

-

10

20

Input Leakage

Current

Output Leakage

Current

VIN = VSS to VDD

-

90

µA

ILO VOUT = VSS to VDD

Input Low Voltage

Input High Voltage

Output Low Voltage

VIL

VIH

-

-0.5

2.0

-

0.8

VDD +0.5

0.45

V

VOL IOL = 2.1 mA

Output High Voltage VOH IOH = -0.1mA

2.4

-

Publication Release Date: December 19, 2002

Revision A2

- 15 -

W39V040FA

FWH interface Mode DC Operating Characteristics

(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)

LIMITS

MIN. TYP.

PARAMETER

SYM.

TEST CONDITIONS

UNIT

MAX.

All Iout = 0A, CLK = 33 MHz,

in FWH mode operation.

mA

Power Supply Current

ICC

-

12.5

20

FWH4 = 0.9 VDD, CLK = 33 MHz,

uA

Standby Current 1

Isb1

Isb2

-

5

25

10

all inputs = 0.9 VDD / 0.1 VDD

no internal operation

FWH4 = 0.1 VDD, CLK = 33 MHz,

mA

Standby Current 2

Input Low Voltage

Input Low Voltage of

#INIT

Input High Voltage

Input High Voltage of

#INIT Pin

-

3

all inputs = 0.9 VDD /0.1 VDD

no internal operation.

VIL

VILI

VIH

VIHI

-

-0.5

-

0.3 VDD

0.2 VDD

V

0.5 VDD

1.35 V

VDD +0.5

Output Low Voltage

Output High Voltage

VOL IOL = 1.5 mA

VOH IOH = -0.5 mA

-

0.1 VDD

-

V

0.9 VDD

Power-up Timing

PARAMETER

Power-up to Read Operation

Power-up to Write Operation

SYMBOL

TPU. READ

TPU. WRITE

TYPICAL

UNIT

µS

mS

100

5

Capacitance

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CI/O

CONDITIONS

VI/O = 0V

VIN = 0V

MAX.

12

6

UNIT

pF

CIN

- 16 -

W39V040FA

8. PROGRAMMER INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

Input Rise/Fall Time

Input/Output Timing Level

Output Load

CONDITIONS

0V to 0.9 VDD

< 5 nS

1.5V/1.5V

1 TTL Gate and CL = 30 pF

AC Test Load and Waveform

+3.3V

1.8K

Ω

D_OUT

Input

Output

30 pF

(Including Jig and

Scope)

0.9VDD

1.5V

0V

1.3K

Ω

1.5V

Test Point

Publication Release Date: December 19, 2002

Revision A2

- 17 -

W39V040FA

Programmer Interface Mode AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)

W39V040FA

MIN. MAX.

PARAMETER

Read Cycle Time

Row / Column Address Set Up Time

Row / Column Address Hold Time

Address Access Time

Output Enable Access Time

#OE Low to Active Output

#OE High to High-Z Output

Output Hold from Address Change

SYMBOL

UNIT

TRC

TAS

300

50

-

0

-

nS

TAH

TAA

TOE

TOLZ

TOHZ

TOH

150

75

-

0

35

-

Write Cycle Timing Parameters

PARAMETER

Reset Time

Address Setup Time

Address Hold Time

R/#C to Write Enable High Time

#WE Pulse Width

#WE High Width

Data Setup Time

Data Hold Time

#OE Hold Time

SYMBOL

TRST

TAS

TAH

TCWH

TWP

TWPH

TDS

TDH

TOEH

TBP

TPEC

TEC

MIN.

TYP.

-

35

20

75

MAX.

UNIT

µS

nS

1

50

100

50

0

-

nS

Byte programming Time

Sector/Page Erase Cycle Time

Chip Erase Cycle Time

-

50

25

100

µS

mS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

Data Polling and Toggle Bit Timing Parameters

W39V040FA

UNIT

PARAMETER

SYMBOL

MIN.

MAX.

#OE to Data Polling Output Delay

#OE to Toggle Bit Output Delay

TOEP

TOET

-

40

nS

- 18 -

W39V040FA

9. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE

Read Cycle Timing Diagram

#RESET

T_RST

T_RC

Row Address

Column Address

T_AH

Row Address

A[10:0]

R#/C

T_AH

T_AS

V

IH

#WE

#OE

T_AA

T_OH

T_OE

T_OHZ

T_OLZ

High-Z

DQ[7:0]

Data Valid

Write Cycle Timing Diagram

T_RST

#RESET

Column Address

T_AS

Row Address

T_AS

A[10:0]

T_AH

R/

#C

T_CWH

T_OEH

#OE

#WE

T_WP

T_WPH

T_DH

T_DS

Data Valid

DQ[7:0]

Publication Release Date: December 19, 2002

Revision A2

- 19 -

W39V040FA

Timing Waveforms for Programmer Interface Mode, continued

Program Cycle Timing Diagram

Byte Program Cycle

A[10:0]

Programmed Address

2AAA

55

5555

(Internal A[18:0])

DQ[7:0]

A0

Data-In

AA

R/#C

#OE

#WE

T_WPH

BP

T

WP

T

Internal Write Start

Byte 0

Byte 1

Byte 2

Byte 3

Note: The internal address A[18:0] are converted from external Column/Row address

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

#DATA Polling Timing Diagram

A[10:0]

(Internal A[18:0])

R/#C

An

#WE

#OE

T

OEP

X

DQ7

X

T

BP or

T

EC

- 20 -

W39V040FA

Timing Waveforms for Programmer Interface Mode, continued

Toggle Bit Timing Diagram

A[10:0]

R/#C

#WE

#OE

T

OET

DQ6

T

BP or

T

EC

Boot Block Lockout Enable Timing Diagram

Six-byte code for Boot Block Lockout command

A[10:0]

2AAA

55

5555

AA

5555

AA

5555

80

2AAA

55

5555

(Internal A[18:0])

DQ[7:0]

40/70

R/#C

#OE

#WE

WP

T

WC

T

WPH

T

SB0

SB2

SB3

SB5

SB4

SB1

Note: The internal address A[18:0] are converted from external Column/Row add

Column/Row Address are mapped to the Low/High order internal addr

i.e. Column Address A[10:0] are mapped to the internal A[10:

Row Address A[7:0] are mapped to the internal A[18:11

When 40(hex) is loaded, the 64KByte are locked; while 70(hex) is loaded, the 16KByte is lo

Publication Release Date: December 19, 2002

Revision A2

- 21 -

W39V040FA

Timing Waveforms for Programmer Interface Mode, continued

Chip Erase Timing Diagram

Six-byte code for 3.3V-only software chip erase

A[10:0]

2AAA

55

5555

2AAA

5555

(Internal A[18:0])

AA

80

55

AA

10

DQ[7:0]

R/#C

#OE

#WE

T_WP

SB0

T_EC

T_WPH

Internal Erasure Starts

SB2

SB3

SB5

SB4

SB1

Note: The internal address A[18:0] are converted from external Column/Row addre

Column/Row Address are mapped to the Low/High order internal addre

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

Sector/Page Erase Timing Diagram

Six-byte code for 3.3V-only

Sector/Page Erase

A[10:0]

5555

AA

2AAA

55

(Internal A[18:0])

DQ[7:0]

5555

80

5555

AA

2AAA

55

SA/PA

30/50

R/#C

#OE

#WE

T_WP

SB0

T_PEC

T_WPH

Internal Erase starts

SB2

SB3

SB5

SB4

SB1

Note: The internal address A[18:0] are converted from external Column/Row address

Column/Row Address are mapped to the Low/High order internal address

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"

- 22 -

W39V040FA

10. FWH INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

Input Rise/Fall Slew Rate

Input/Output Timing Level

Output Load

CONDITIONS

0.6 VDD to 0.2 VDD

1 V/nS

0.4VDD / 0.4VDD

1 TTL Gate and CL = 10 pF

Read/Write Cycle Timing Parameters

(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)

W39V040FA

PARAMETER

Clock Cycle Time

Input Set Up Time

Input Hold Time

SYMBOL

UNIT

MIN.

30

7

MAX.

TCYC

TSU

THD

TKQ

-

nS

0

2

Clock to Data Valid

11

Note: Minimum and Maximum time has different loads. Please refer to PCI specification.

Reset Timing Parameters

PARAMETER

VDD stable to Reset Active

Clock Stable to Reset Active

Reset Pulse Width

Reset Active to Output Float

Reset Inactive to Input Active

SYMBOL

TPRST

TKRST

TRSTP

TRSTF

TRST

MIN.

1

100

-

TYP.

MAX.

UNIT

mS

µS

nS

-

50

-

10

µS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

Publication Release Date: December 19, 2002

Revision A2

- 23 -

W39V040FA

11. TIMING WAVEFORMS FOR FWH INTERFACE MODE

Read Cycle Timing Diagram

T_CYC

CLK

#RESET

FWH4

T_SU

T_HD

T_KQ

T_SU

Start

FWH

Read

M Size

0000

Address

TAR

1111b Tri-State 0000b

2 Clocks

1 Clock Data out 2 Clocks

Next Start

0000b

IDSEL

TAR

Tri-State

2 Clocks

Sync

Data

D[3:0]

D[7:4]

XA[22]XXb

XXA[18:16]

FWH[3:0]

XXXXb

A[3:0]

1111b

1101b

A[15:12] A[11:8] A[7:4]

0000b

Load Address in 7

1 Clock

Note: When A22 = high, the host will read the BIOS code from the FWH d

While A22 = low, the host will read the GPI (Add = FFBC0100

Product ID (Add = FFBC0000/FFBC0001) from the FWH dev

Write Cycle Timing Diagram

T

CYC

CLK

#RESET

FWH4

T

SU HD

Start

FWH

Write

TAR

M Size

Sync

0000b

Address

Next Start

1 Clock

IDSEL

0000b

Data

D[7:4]

XXXXb XXXXb XXA[18:16]b

A[7:4]

1111b

Tri-State 0000b

A[15:12] A[11:8]

A[3:0]

0000b

Tri-State

1111b

FWH[3:0]

1110b

D[3:0]

2 Clocks

1 Clock

2 Clocks

Load Data in 2 Clocks

1 Clock

Load Address in 7 Clocks

1 Clock

- 24 -

W39V040FA

Timing Waveforms, for FWH Interface Mode, continued

Program Cycle Timing Diagram

CLK

#RESET

FWH4

Start next

Data

TAR

Sync

0000b

TAR

1111b

2 Clocks

Address

X101b

M Size

0000b

IDSEL

0000b

1st Start

1110b

command

XXXXb

0101b

1111b

Load Data "AA" in 2 Clocks

Tri-State

FWH[3:0 ]

1010b

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

1111b

2 Clocks

Address

X010b

M Size

0000b

Sync

0000b

IDSEL

0000b

2nd Start

1110b

XXXXb

1010b

FWH[3:0]

XXXXb

1111b

2 Clocks

Tri-State

0101b

Tri-State

Load Data "55"

in 2 Clocks

1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

1111b

2 Clocks

Sync

0000b

IDSEL

0000b

Address

X101b

M Size

0000b

3rd Start

1110b

]

FWH[3:0

XXXXb

0101b

0000b

1010b

1111b

Tri-State

Load Data "A0"

in 2 Clocks

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 3rd command to the device in FWH mode.

CLK

#RESET

Internal

FWH4

program start

Address

A[15:12]

Data

TAR

IDSEL

TAR

M Size

0000b

Sync

0000b

4th Start

1110b

]

1111b

2 Clocks

Internal

FWH[3:0

D[3:0]

D[7:4]

1111b

Tri-State

XA[18:16]b

A[11:8]

A[7:4]

A[3:0]

Tri-State

0000b

program start

Load Din in 2 Clocks

1 Clock

Load Ain in 7 Clocks

2 Clocks

1 Clock

Write the 4th command(target location to be programmed) to the device in FWH mode.

Publication Release Date: December 19, 2002

Revision A2

- 25 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

#DATA Polling Timing Diagram

CLK

#RESET

FWH4

Data

TAR

Sync

0000b

TAR

1111b

2 Clocks

Next Start

1 Clock

Address

An[15:12]

M Size

Start

IDSEL

0000b

XXXXb

Dn[3:0] Dn[7:4]

XXA[18:16]b

0000b

1111b

FWH[3:0]

1110b

An[7:4]

An[3:0]

Tri-State

An[11:8]

Load Data "Dn"

in 2 Clocks

2 Clocks

1 Clock

Load Address "An" in 7 Clocks

1 Clock

Write the last command(program or erase) to the device in FWH mode.

CLK

#RESET

XXXXb

FWH4

TAR

1111b

2 Clocks

Next Start

1 Clock

M Size

TAR

Tri-State 0000b

2 Clocks

Read the DQ7 to see if the internal write complete or not.

Address

Start

Sync

Data

IDSEL

0000b

XXXXb

XXA[18:16]b

An[3:0]

0000b

An[15:12]

An[11:8]

An[7:4]

Tri-State

FWH[3:0]

1101b

1111b

XXXXb Dn7,xxx

1 Clock

Data out 2 Clocks

Load Address in 7 Clocks

1 Clock

CLK

#RESET

FWH4

TAR

1111b

2 Clocks

Next Start

1 Clock

Address

An[15:12]

TAR

Tri-State 0000b

1 Clock

IDSEL

0000b

Start

1101b

M Size

Data

Sync

XXXXb

Dn7,xxx

FWH[3:0]

1111b

2 Clocks

Tri-State

XXA[18:16]b

An[3:0]

0000b

An[11:8]

An[7:4]

Load Address in 7 Clocks

Data out 2 Clocks

1 Clock

When internal write complete, the DQ7 will equal to Dn7.

- 26 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

Toggle Bit Timing Diagram

CLK

#RESET

FWH4

Data

D[7:4]

TAR

1111b

2 Clocks

Next Start

1 Clock

Sync

0000b

Address

M Size

Start

IDSEL

0000b

XXXXb

XXA[18:16]b A[15:12]

A[7:4]

A[3:0]

0000b

D[3:0]

1111b

Tri-State

FWH[3:0]

1110b

A[11:8]

Tri-State

Load Data "Dn"

in 2 Clocks

2 Clocks

1 Clock

Load Address "An" in 7 Clocks

1 Clock

Write the last command(program or erase) to the device in FWH mode.

CLK

#RESET

FWH4

TAR

1111b

Next Start

1 Clock

Address

XXXXb

TAR

1111b

Tri-State 0000b

Start

IDSEL

0000b

M Size

Sync

Data

XXXXb

0000b

FWH[3:0]

1101b

X,D6,XXb

Tri-State

2 Clocks

1 Clock

2 Clocks

Read the DQ6 to see if the internal write complete or not.

1 Clock Data out 2 Clocks

Load Address in 7 Clocks

1 Clock

CLK

#RESET

FWH4

TAR

1111b

2 Clocks

Next Start

1 Clock

Address

XXXXb

TAR

1111b

Tri-State 0000b

Start

1101b

Data

XXXXb

1 Clock Data out 2 Clocks

M Size

Sync

IDSEL

0000b

XXXXb

FWH[3:0]

XXXXb

0000b

Tri-State

XXXXb

X,D6,XXb

2 Clocks

When internal write complete, the DQ6 will stop toggle.

Load Address in 7 Clocks

1 Clock

Publication Release Date: December 19, 2002

Revision A2

- 27 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

Boot Block Lockout Enable Timing Diagram

CLK

#RESET

FWH4

Start next

Data

1010b

TAR

Sync

0000b

TAR

1111b

2 Clocks

Address

X101b

IDSEL

0000b

M Size

1st Start

1110b

command

XXXXb

0101b

1111b

2 Clocks

0101b

0000b

Tri-State

FWH[3:0]

0101b

1010b

Load Data "AA"

in 2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

TAR

1111b

2 Clocks

Address

X010b

Data

0101b

TAR

Sync

0000b

IDSEL

0000b

M Size

2nd Start

1110b

XXXXb

FWH[3:0]

XXXXb

1010b

1111b

2 Clocks

Tri-State

1010b

0000b

Tri-State

0101b

Load Data "55"

in 2 Clocks

1 Clocks

1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

1111b

2 Clocks

Sync

0000b

IDSEL

0000b

Address

X101b

M Size

3rd Start

1110b

XXXXb

FWH[3:0]

XXXXb

0101b

1111b

0101b

0000b

1000b

Tri-State

Load Data "80"

in 2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

1010b

TAR

1111b

2 Clocks

Address

X101b

M Size

IDSEL

Sync

0000b

4th Start

1110b

XXXXb

1111b

2 Clocks

Tri-State

FWH[3:0]

0000b

Tri-State

XXXXb

0101b

1010b

0000b

Load Data "AA"

in 2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

1111b

2 Clocks

Sync

0000b

Address

X010b

M Size

5th Start

1110b

IDSEL

0000b

XXXXb

1111b

XXXXb

Tri-State

FWH[3:0]

1010b

0000b

1010b

0101b

Load Data "55"

in 2 Clocks

2 Clocks

1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X101b

Data

TAR

1111b

2 Clocks

Sync

0000b

IDSEL

0000b

M Size

6th Start

1110b

0100b/

0111b

XXXXb

0000b

XXXXb

0000b

1111b

Tri-State

0101b

Tri-State

FWH[3:0]

Load Data "40" or

1 Clock

2 Clocks

1 Clock

Load Address "5555" 7 Clocks

1 Clock

"70" in Two Clocks

Write the 6th command to the device in FWH mode.

- 28 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

Chip Erase Timing Diagram

CLK

#RESET

FWH4

Start next

Data

1010b

TAR

Sync

0000b

IDSEL

TAR

Address

X101b

M

Size

1st Start

1110b

command

XXXXb

1111b

FWH[3:0]

0101b

0000b

Tri-State

1111b

Tri-State

1010b

0000b

Load Data "AA"

in 2 Clocks

2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X010b

M

Size

Data

0101b

TAR

Sync

0000b

IDSEL

0000b

2th Start

1110b

XXXXb

FWH[3:0]

XXXXb

0000b

1111b

1010b

1111b

2 Clocks

Tri-State

0101b

Tri-State

Load Data "55"

in 2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

M

Size

Sync

0000b

TAR

Address

X101b

IDSEL

0000b

3th Start

1110b

XXXXb

FWH[3:0]

XXXXb

0000b

0101b

1000b

1111b

0000b

Tri-State

Load Data "80"

in 2 Clocks

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

2 Clocks

1 Clock

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X101b

Data

1010b

TAR

M

Size

Sync

0000b

TAR

IDSEL

0000b

4th Start

1110b

FWH[3:0]

XXXXb

0101b

0000b

1111b

2 Clocks

1111b

1010b

Tri-State

Load Data "AA"

in 2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

2 Clocks

1 Clock

Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

0101b

TAR

M

Size

Sync

0000b

TAR

IDSEL

0000b

Address

X010b

5th Start

1110b

FWH[3:0]

XXXXb

0000b

1111b

Tri-State

1111b

1010b

Tri-State

0101b

Load Data "55"

in 2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "2AAA" in 7 Clocks

2 Clocks

1 Clock

Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4

Internal

erase start

Address

X101b

Data

TAR

Sync

0000b

IDSEL

0000b

M

Size

6th Start

1110b

FWH[3:0]

XXXXb

Internal

XXXXb

0001b

1111b

2 Clocks

1111b Tri-State

2 Clocks

0000b

Tri-State

0101b

erase start

Load Data "10"

in 2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

Write the 6th command to the device in FWH mode.

Publication Release Date: December 19, 2002

Revision A2

- 29 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

Sector Erase Timing Diagram

CLK

#RESET

FWH4

Start next

Data

1010b

TAR

M Size

0000b

Sync

Address

command

1st Start IDSEL

XXXXb

0000b

1110b

XXXXb

1111b

2 Clocks

0000b

FWH[3:0]

Tri-State

0101b

X101b

1010b

1111b

Tri-State

Load Data "AA"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "5555" in 7 Clocks

2 Clocks

1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X010b

Data

0101b

TAR

Sync

0000b

M

IDSEL

0000b

2nd Start

1110b

Size

XXXXb

FWH[3:0]

XXXXb

0000b

1111b

Tri-State

1111b

1010b

0101b

Tri-State

Load Data "55"

in 2 Clocks

2 Clocks

1 Clock

2 Clocks

1 Clock 1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

TAR

M Size

0000b

Sync

Address

X101b

3rd Start

1110b

IDSEL

0000b

XXXXb

FWH[3:0]

0000b

XXXXb

Tri-State

1111b

Tri-State

2 Clocks

0000b

1000b

0101b

1111b

Load Data "80"

in 2 Clocks

2 Clocks

1 Clocks

1 Clocks1 Clocks

Load Address "5555" in 7 Clocks

1 Clocks

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

1010b

TAR

Address

X101b

M Size

0000b

Sync

IDSEL

0000b

4th Start

1110b

FWH[3:0]

XXXXb

Tri-State

XXXXb

0101b

1111b

Tri-State 0000b

1111b

1010b

Load Data "AA"

in 2 Clocks

1 Clock

2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

0101b

TAR

1111b

Tri-State

M Size

0000b

Sync

Address

X010b

5th Start

1110b

IDSEL

0000b

FWH[3:0]

XXXXb

Tri-State 0000b

XXXXb

1111b

1010b

0101b

Load Data "55"

in 2 Clocks

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4

Internal

erase start

Address

XXXXb

Data

TAR

Sync

M Size

0000b

IDSEL

0000b

6th Start

1110b

FWH[3:0]

Internal

XXXXb

0011b

1111b Tri-State

2 Clocks

0000b

1111b

2 Clocks

Tri-State

0000b

XA[18:16]b

XXXXb

XXXXb XXXXb

erase start

Load Din

1 Clock

Load Sector Address in 7 Clocks

1 Clock

in 2 Clocks

Write the 6th command(target sector to be erased) to the device in FWH mode.

- 30 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

Page Erase Timing Diagram

CLK

#RESET

FWH4

Start next

Data

1010b

TAR

Sync

M Size

0000b

Address

command

1st Start

1110b

IDSEL

0000b

XXXXb

1111b

2 Clocks

0000b

FWH[3:0]

Tri-State

0101b

X101b

1010b

1111b

Tri-State

Load Data "AA"

in 2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "5555" in 7 Clocks

2 Clocks

1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X010b

Data

0101b

TAR

Sync

0000b

IDSEL

0000b

M

2nd Start

1110b

Size

XXXXb

FWH[3:0]

1111b

XXXXb

0000b

1111b

Tri-State

1010b

0101b

Tri-State

Load Data "55"

in 2 Clocks

2 Clocks

1 Clock

2 Clocks

1 Clock 1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

0000b

TAR

M Size

0000b

Sync

Address

X101b

3rd Start

1110b

IDSEL

0000b

XXXXb

FWH[3:0]

XXXXb

Tri-State

2 Clocks

0000b

1111b

Tri-State

2 Clocks

1000b

0101b

1111b

Load Data "80"

in 2 Clocks

1 Clocks

1 Clocks1 Clocks

Load Address "5555" in 7 Clocks

1 Clocks

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Address

X101b

Data

1010b

TAR

M Size

0000b

Sync

IDSEL

0000b

4th Start

1110b

FWH[3:0]

XXXXb

Tri-State

XXXXb

0101b

Tri-State 0000b

1111b

1010b

1111b

Load Data "AA"

in 2 Clocks

1 Clock

2 Clocks

1 Clock

2 Clocks

1 Clock

Load Address "5555" in 7 Clocks

1 Clock

Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next

command

Data

0101b

TAR

1111b

2 Clocks

M Size

0000b

Sync

Address

X010b

5th Start IDSEL

FWH[3:0]

XXXXb

Tri-State 0000b

Tri-State

XXXXb

1110b

0000b

1010b

1111b

1010b

0101b

Load Data "55"

in 2 Clocks

2 Clocks

1 Clock

1 Clock 1 Clock

Load Address "2AAA" in 7 Clocks

1 Clock

Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4

Internal

erase start

Address

A[15:12]

Data

0101b

TAR

Sync

0000b

M Size

0000b

IDSEL

0000b

6th Start

1110b

FWH[3:0]

Internal

XXXXb

1111b

Tri-State

XA[18:16]b

1111b

2 Clocks

0000b

Tri-State

XXXXb

XXXXb XXXXb

erase start

Load Din

2 Clocks

1 Clock

Load Page Address in 7 Clocks

1 Clock

in 2 Clocks

Write the 6th command(target page to be erased) to the device in FWH mode.

Publication Release Date: December 19, 2002

Revision A2

- 31 -

W39V040FA

Timing Waveforms for FWH Interface Mode, continued

FGPI Register/Product ID Readout Timing Diagram

CLK

#RESET

FWH4

M Size

0000b

IDSEL

0000b

Address

0000b

TAR

Next Sta

1 Clock

TAR

Start

Sync

Data

FWH[3:0]

0001b

/0000b

0000b

/0001b

1101b

Tri-State 1111b

D[3:0]

D[7:4]

A[27:24]

Tri-State 1111b

A[23:20] A[19:16]

0000b

Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register

& "FFBC0000(hex)/FFBC0001(hex) for Product ID

2 Clocks

1 Clock Data out 2 Clocks

1 Clock 1 Clock

2 Clocks

Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins

Reset Timing Diagram

VDD

CLK

T

PRST

T

KRST

T

RSTP

#RESET

FWH[3:0]

T

RST

T

RST

FWH4

- 32 -

W39V040FA

12. ORDERING INFORMATION

ACCESS

POWER SUPPLY

STANDBY VDD

CURRENT MAX.

(mA)

PART NO.

TIME

CURRENT MAX.

(mA)

PACKAGE

(nS)

W39V040FAP

W39V040FAQ

W39V040FAT

11

20

10

32L PLCC

32L STSOP

40L TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

13. HOW TO READ THE TOP MARKING

Example: The top marking of 32-pin STSOP W39V040FAQ

W39V040FAQ

2138977A-A12

149OBSA

1^stline: Winbond logo

2^ndline: the part number: W39V040FAQ

3^rdline: the lot number

4^thline: the tracking code: 149 O B SA

149: Packages made in '01, week 49

O: Assembly house ID: A means ASE, O means OSE, ...etc.

B: IC revision; A means version A, B means version B, ...etc.

SA: Process code

Publication Release Date: December 19, 2002

Revision A2

- 33 -

W39V040FA

14. PACKAGE DIMENSIONS

32L PLCC

Dimension in Inches

Min. Nom. Max. Min. Nom. Max.

Dimension in mm

Symbol

H _E

E

0.140

3.56

A

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

1

A

4

1

32

30

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

0.115

0.032

0.022

0.014

2.80

0.71

2.93

0.81

0.56

0.35

A

b

c

2

1

0.46

5

29

0.25

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

D

E

e

12.45

9.91

12.95

13.46

10.92

15.11

12.57

2.41

G

H

D

G^D

10.41

14.99

12.45

2.29

E

D

E

D

H^D

14.86

12.32

1.91

L

0.10

y

0

10

0

10

θ

21

13

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusio

3. Controlling dimension: Inches

14

20

c

4. General appearance spec. should be based on final

visual inspection sepc.

L

A²

A

θ

e

1

b

b¹

A

Seating Plane

y

E

G

32L STSOP

H_D

D

c

Dimension in Inches Dimension in mm

Symbol

Max.

1.20

Min. Nom. Max. Min. Nom.

e

0.047

A

0.002

0.035

0.006

0.041

0.05

0.95

0.17

0.10

0.15

1

A

E

0.040

1.00

0.22

A²

b

c

1.05

0.27

b

0.007 0.009 0.010

0.004

0.008

-----

12.40

8.00

0.21

-----

0.488

D

E

0.315

0.551

0.020

14.00

D

H

0.50

0.60

0.80

e

0.50

0.70

0.020 0.024 0.028

0.031

L

θ

1

L

A

¹A

2

0.000

0.004

0.00

0

0.10

5

L

Y

θ

A

0

3

5

3

L

1

- 34 -

W39V040FA

Package Dimensions, continued

40L TSOP (10 mm x 20 mm)

R

0.08

0.02

0.003

0.008

Publication Release Date: December 19, 2002

Revision A2

- 35 -

W39V040FA

15. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

A2

June 19, 2002

Dec. 19, 2002

-

23

Initial Issued

Delete AC Test Load and Waveform.

Add a note below Read/Write Cycle Timing

Parameter

15

1, 16, 33

16

Modify PGM mode power supply current (Icc)

parameter from 20 mA (typ.) to 10 mA (typ.) and

30 mA (max.) to 20 mA (max.)

Modify FWH mode power supply current (Icc)

parameter from 40 mA (typ.) to 12.5 mA (typ.) and

60 mA (max.) to 20 mA (max.)

Modify Standby current (Isb1) parameter from 20 µA

(typ.) to 5 µA (typ.) and 100 µA (max.) to 25 µA

(max.)

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

2727 North First Street, San Jose,

CA 95134, U.S.A.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62365998

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

TEL: 852-27513100

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 36 -


型号：	W39V040FAQ
厂家：	WINBOND
描述：	512K X 8 CMOS FLASH MEMORY WITH FWH INERFACE 512K ×8 CMOS闪光灯FWH INERFACE记忆闪存存储内存集成电路闪光灯光电二极管
文件：	总36页 (文件大小：515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W39V040FAQ [WINBOND]

相关型号：

W39V040FAQZ

W39V040FAT

W39V040FATZ

W39V040FB

W39V040FBP

W39V040FBPZ

W39V040FBQ

W39V040FBQZ

W39V040FB_07

W39V040FC

W39V040FCP

W39V040FCPZ