W39V040FC [WINBOND]
512K 】 8 CMOS FLASH MEMORY WITH FWH INTERFACE; 512K 】 8 CMOS闪光灯FWH接口存储器
| 型号： | W39V040FC |
| 厂家： | 
WINBOND |
| 描述： | 512K 】 8 CMOS FLASH MEMORY WITH FWH INTERFACE |
| 文件： | 总36页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W39V040FC Data Sheet
512K × 8 CMOS FLASH MEMORY
WITH FWH INTERFACE
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 3
2. FEATURES ...................................................................................................................................... 3
3. PIN CONFIGURATIONS.................................................................................................................. 4
4. BLOCK DIAGRAM ........................................................................................................................... 5
5. PIN DESCRIPTION.......................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION......................................................................................................... 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Interface Mode Selection and Description ............................................................................ 7
Read (Write) Mode................................................................................................................ 7
Reset Operation .................................................................................................................... 7
Accelerated Program Operation............................................................................................ 7
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP............................... 7
Sector/Page Erase Command............................................................................................... 8
Program Operation................................................................................................................ 8
Hardware Data Protection..................................................................................................... 8
Write Operation Status.......................................................................................................... 8
6.10 DQ7: #Data Polling................................................................................................................ 9
6.11 RY/#BY: Ready/#Busy .......................................................................................................... 9
6.12 DQ6: Toggle Bit..................................................................................................................... 9
6.13 DQ5: Exceeded Timing Limits............................................................................................. 10
6.14 Identification Input pin ID[3:0].............................................................................................. 10
7. REGISTER FOR FWH MODE ....................................................................................................... 11
7.1
7.2
7.3
7.4
7.5
7.6
7.7
General Purpose Inputs Register for FWH Mode ............................................................... 11
Product Identification Registers........................................................................................... 11
Block Locking Registers...................................................................................................... 11
Register Based Block Locking Value Definitions Table ...................................................... 12
Read Lock ........................................................................................................................... 12
Write Lock............................................................................................................................ 12
Lock Down........................................................................................................................... 12
8. TABLE OF OPERATING MODES ................................................................................................. 13
8.1
8.2
8.3
8.4
Operating Mode Selection - Programmer Mode ................................................................. 13
Operating Mode Selection - FWH Mode ............................................................................. 13
FWH Cycle Definition .......................................................................................................... 13
TABLE OF COMMAND DEFINITION ................................................................................. 14
9. EMBEDDED PROGRAMMING ALGORITHM ............................................................................... 15
10. EMBEDDED ERASE ALGORITHM............................................................................................... 16
11. EMBEDDED #DATA POLLING ALGORITHM............................................................................... 17
Publication Release Date: Apr. 11, 2006
- 1 -
Revision A1
W39V040FC
12. EMBEDDED TOGGLE BIT ALGORITHM...................................................................................... 18
13. SOFTWARE PRODUCT IDENTIFICATION AND BOOT BLOCK LOCKOUT DETECTION
ACQUISITION FLOW............................................................................................................................ 19
14. ELECTRICAL CHARACTERISTICS.............................................................................................. 20
14.1 Absolute Maximum Ratings................................................................................................. 20
14.2 Programmer interface Mode DC Operating Characteristics ............................................... 20
14.3 FWH Interface Mode DC Operating Characteristics........................................................... 21
14.4 Power-up Timing ................................................................................................................. 21
14.5 Capacitance......................................................................................................................... 21
14.6 Programmer Interface Mode AC Characteristics ................................................................ 22
14.7 Read Cycle Timing Parameters .......................................................................................... 22
14.8 Write Cycle Timing Parameters........................................................................................... 23
14.9 Data Polling and Toggle Bit Timing Parameters ................................................................. 23
15. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ............................................ 24
15.1 Read Cycle Timing Diagram ............................................................................................... 24
15.2 Write Cycle Timing Diagram................................................................................................ 24
15.3 Program Cycle Timing Diagram.......................................................................................... 25
15.4 #DATA Polling Timing Diagram........................................................................................... 25
15.5 Toggle Bit Timing Diagram.................................................................................................. 26
15.6 Sector /Page Erase Timing Diagram................................................................................... 26
16. FWH INTERFACE MODE AC CHARACTERISTICS..................................................................... 27
16.1 AC Test Conditions ............................................................................................................. 27
16.2 Read/Write Cycle Timing Parameters................................................................................. 27
16.3 Reset Timing Parameters.................................................................................................... 27
17. TIMING WAVEFORMS FOR FWH INTERFACE MODE............................................................... 28
17.1 Read Cycle Timing Diagram ............................................................................................... 28
17.2 Write Cycle Timing Diagram................................................................................................ 28
17.3 Program Cycle Timing Diagram.......................................................................................... 29
17.4 #DATA Polling Timing Diagram........................................................................................... 30
17.5 Toggle Bit Timing Diagram.................................................................................................. 31
17.6 Sector /Page Erase Timing Diagram................................................................................... 32
17.7 FGPI Register/Product ID Readout Timing Diagram .......................................................... 33
17.8 Reset Timing Diagram......................................................................................................... 33
18. ORDERING INFORMATION.......................................................................................................... 34
19. HOW TO READ THE TOP MARKING........................................................................................... 34
20. PACKAGE DIMENSIONS.............................................................................................................. 35
20.1 32L PLCC............................................................................................................................ 35
20.2 32L STSOP ......................................................................................................................... 35
21. VERSION HISTORY...................................................................................................................... 36
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W39V040FC
1. GENERAL DESCRIPTION
The W39V040FC is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For
flexible erase capability, the 4Mbits of data are divided into 16 x 8 Kbytes pages and 6 x 64 Kbytes
sectors or 8 x 64 Kbytes sectors. The device can be programmed and erased in-system with a standard
3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of
the W39V040FC results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode, Firmware Hub (FWH) bus interface
mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed
address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification.
The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
y
Single 3.3-volt operations:
− 3.3-volt Read
− 3.3-volt Erase
− 3.3-volt Program
Fast Program operation:
y
− Byte-by-Byte programming: 7 μS (typ.) (VPP = 12V)
− Byte-by-Byte programming: 10 μS (typ.) (VPP = Vcc)
Fast Erase operation:
− Sector erase 0.6 Sec. (typ.)
− Page erase 0.3 Sec. (typ.)
y
y
y
y
Fast Read access time: Tkq 11 nS
Endurance: 50K cycles (typ.)
Twenty-year data retention
6 Even sectors with 64K bytes
16 Even pages with 8K bytes or 8 Even sectors with 64 Kbytes
Any individual sector/page can be erased
Hardware protection:
y
y
− #TBL supports 64-Kbyte Boot Block hardware protection
− #WP supports the whole chip except Boot Block hardware protection
Low power consumption
y
− Active current: 15 mA (typ. for FWH read mode)
Automatic program and erase timing with internal VPP generation
End of program or erase detection
− Toggle bit
y
y
− Data polling
y
y
y
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC, 32L STSOP
32L PLCC Lead free, 32L STSOP Lead free
Publication Release Date: Apr. 11, 2006
Revision A1
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W39V040FC
3. PIN CONFIGURATIONS
Firmware Hub (FWH) Mode
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
#OE(#INIT)
#WE(FWH4)
RY/#BY(RSV)
NC
NC
NC
SS
DQ7(RSV)
V
IC
A10(FGPI4)
R/#C(CLK)
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
8
9
DD
Vpp
#RESET
A9(FGPI3)
A8(FGPI2)
A7(FGPI1)
A6(FGPI0)
V
DQ3(FWH3)
32L STSOP
SS
V
10
11
12
13
14
15
16
DQ2(FWH2)
DQ1(FWH1)
DQ0(FWH0)
A0(ID0)
A1(ID1)
A2(ID2)
A5(#WP)
A4(#TBL)
A3(ID3)
A
A
8
^
R
/
A
9
^
1
0
#
C
^
^
#
F
G
P
I
F
G
P
I
F
G
P
I
R
E
S
E
T
C
L
K
v
V
P
P
V
D
D
2
v
3
v
4
v
4
3
1
2
32 31 30
A7(FGPI1)
A6(FGPI0)
A5(#WP)
A4(#TBL)
A3(ID3)
29
28
27
26
25
24
23
22
21
5
IC
6
V SS
NC
7
8
NC
9
V DD
32L PLCC
10
11
12
13
A2(ID2)
#OE(#INIT)
#WE(FWH4)
RY/#BY(RSV)
DQ7(RSV)
A1(ID1)
A0(ID0)
DQ0(FWH0)
14
15 16 17 18
19 20
D
Q
1
D
Q
2
D
Q
5
D
Q
3
D
Q
4
D
Q
6
V
S
S
^
^
^
^
^
^
F
F
R
S
V
v
F
R
S
V
v
R
S
V
v
W
H
1
W
H
2
W
H
3
v
v
v
- 4 -
W39V040FC
4. BLOCK DIAGRAM
#WP
7FFFF
7E000
8K BYTES
#TBL
64K BYTES
Boot block
sector 7
FWH
Interface
CLK
FWH[3:0]
FWH4
71FFF
70000
6FFFF
6E000
8K BYTES
8K BYTES
IC
#INIT
64K BYTES
sector 6
#RESET
61FFF
60000
5FFFF
8K BYTES
64K BYTES sector 5
R/#C
A[10:0]
50000
Program-
mer
DQ[7:0]
1FFFF
10000
0FFFF
Interface
64K BYTES sector 1
64K BYTES sector 0
#OE
#WE
RY/#BY
00000
Publication Release Date: Apr. 11, 2006
Revision A1
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W39V040FC
5. PIN DESCRIPTION
INTERFACE
SYM.
PIN NAME
Interface Mode Selection
PGM
FWH
IC
#RESET
#INIT
*
*
*
*
*
*
*
*
*
Reset
Initialize
#TBL
Top Boot Block Lock
Write Protect
CLK Input
#WP
CLK
FGPI[4:0]
General Purpose Inputs
Identification Inputs They Are Internal Pull Down
to Vss
ID[3:0]
*
FWH[3:0]
FWH4
R/#C
*
*
Address/Data Inputs
FWH Cycle Initial
Row/Column Select
Address Inputs
*
*
*
*
*
*
*
*
*
*
*
A[10:0]
DQ[7:0]
#OE
Data Inputs/Outputs
Output Enable
#WE
Write Enable
RY/#BY
VDD
Ready/ Busy
*
*
*
*
*
Power Supply
VSS
Ground
VPP
Accelerate Program Power Supply
Reserved Pins
RSV
NC
No Connection
- 6 -
W39V040FC
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
IC pin is set to VDD, the device will be in the Programmer mode; while the IC pin is set to low state (or
leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like
traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row
address are mapped to the higher internal address A[18:11]. And the column address are mapped to
the lower internal address A[10:0]. For FWH mode, it complies with the FWH Interface Specification,
through the FWH[3:0] to communicate with the system chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040FC is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined
by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for
further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Accelerated Program Operation
The device provides accelerated program operations through the ACC function.This function is
primarily intended to allow a faster manufacturing throughput in the factory.
6.5 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on
programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If
#WP pin is tied to low state before power on, the other sectors will not be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). You can check the
DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is
“0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be
programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it
means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.
Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in
high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if
the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Publication Release Date: Apr. 11, 2006
- 7 -
Revision A1
W39V040FC
6.6 Sector/Page Erase Command
Sector/Page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by
writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector/Page erase
command. The Sector/Page address (any address location within the desired Sector/Page) is latched
on the rising edge of R/#C in programmer mode, while the command (30/50H) is latched on the rising
edge of #WE.
Sector/Page erase does not require the user to program the device prior to erase. When erasing a
Sector/Page, the remaining unselected sectors/pages are not affected. The system is not required to
provide any controls or timings during these operations.
The automatic Sector/Page erase begins after the erase command is completed, right from the rising
edge of the #WE pulse for the last Sector/Page erase command pulse and terminates when the data on
DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be
performed at an address within any of the sectors/page being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.7 Program Operation
The W39V040FC is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (10μS typ. -
TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
6.8 Hardware Data Protection
The integrity of the data stored in the W39V040FC is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 5 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 2.0V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
6.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,
and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase
operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in
programmer mode, to determine whether an Embedded Program or Erase operation is in progress or
has been completed.
- 8 -
W39V040FC
6.10 DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress
or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command
sequence.
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the
data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector , #Data Polling on DQ7 is
active for about 1μS, and then the device returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded
Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the
sector /page selected for erasure must be provided to read valid status information on DQ7.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the DQ7
output, the system may read the status or valid data. Even if the device has completed the program or
erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data
on DQ7-DQ0 will appear on successive read cycles.
6.11 RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command
sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a
pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. When the output is high
(Ready), the device is in the read mode or standby mode.
6.12 DQ6: Toggle Bit
Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE
pulse in the command sequence (before the program or erase operation), and during the sector /page
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation
has completed, DQ6 stops toggling.
The system can use DQ6 to determine whether a sector /page is actively erasing. If the device is
actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address
falls within a protected sector , DQ6 toggles for about 1 μs after the program command sequence is
written, and then returns to reading array data.
Publication Release Date: Apr. 11, 2006
- 9 -
Revision A1
W39V040FC
6.13 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the
device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must hardware reset to return to the read mode.
6.14 Identification Input pin ID[3:0]
These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot
device should be 0000b. And all the subsequent parts should use the up-count strapping.
- 10 -
W39V040FC
7. REGISTER FOR FWH MODE
There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock
Control Registers and Product Identification Registers. Users can access these registers through
respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.
7.1 General Purpose Inputs Register for FWH Mode
This register reads the FGPI[4:0] pins on the W39V040FC.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
GPI Register Table
BIT
FUNCTION
Reserved
7 − 5
4
3
2
1
0
Read FGPI4 pin status
Read FGPI3 pin status
Read FGPI2 pin status
Read FGPI1 pin status
Read FGPI0 pin status
7.2 Product Identification Registers
In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex).
A read from FFBC, 0001(hex) can output the device code 50 (hex).
There is an alternative software method to read out the Product Identification in both the Programmer
interface mode and the FWH interface mode. Thus, the programming equipment can automatically
matches the device with its proper erase and programming algorithms.
In the software access mode, a or JEDEC 3-byte command sequence can be used to access the
product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer
code, DA(hex). A read from address 0001(hex) outputs the device code, 50 (hex). The product ID
operation can be terminated by a three-byte command sequence or an alternate one-byte command
sequence (see Command Definition table for detail).
7.3 Block Locking Registers
This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These
control registers can be set or clear through memory address. Below is the detail description.
Please note that this feature is only can be applied on FWH mode.
Block Locking Registers type and access memory map Table
REGISTERS
TYPE
CONTROL
BLOCK
DEVICE PHYSICAL
ADDRESS
4GBYTES SYSTEM
MEMORY ADDRESS
REGISTERS
BLR7
BLR6
BLR5
BLR4
BLR3
BLR2
BLR1
BLR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
7FFFFh – 70000h
6FFFFh – 60000h
5FFFFh – 50000h
4FFFFh – 40000h
3FFFFh – 30000h
2FFFFh – 20000h
1FFFFh – 10000h
0FFFFh – 00000h
FFBF0002h
FFBE0002h
FFBD0002h
FFBC0002h
FFBB0002h
FFBA0002h
FFB90002h
FFB80002h
Publication Release Date: Apr. 11, 2006
Revision A1
- 11 -
W39V040FC
Block Locking Register Bits Function Table
BIT
FUNCTION
7 – 3
Reserved
Read Lock
2
1: Prohibit to read in the block where set
0: Normal read operation in the block where clear. This is default state.
Lock Down
1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down
Bit can only be set not clear. Only the device is reset or re-powered, the Lock Down
Bit is cleared.
0: Normal operation for Read Lock or Write Lock. This is the default state.
Write Lock
1
0
1: Prohibited to write in the block where set. This is default state.
0: Normal programming/erase operation in the block where clear.
7.4 Register Based Block Locking Value Definitions Table
BIT [7:3]
00000
00000
00000
00000
00000
00000
00000
00000
BIT 2
BIT 1
BIT 0
RESULT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full Access.
Write Lock. Default State.
Locked Open (Full Access, Lock Down).
Write Locked, Locked Down.
Read Locked.
Read & Write Locked.
Read Locked, Locked Down.
Read & Write Locked, Locked Down.
7.5 Read Lock
Any attempt to read the data of read locked block will result in “00H.” The default state of any block is
unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit is
not set.
7.6 Write Lock
This is the default state of blocks upon power up. Before any program or erase to the specified block,
user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the
lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP &
TBL. When hardware protect pins are enabled, it will override the register block locking functions and
write lock the blocks no matter how the status of the register bits. Reading the register bit will not reflect
the status of the #WP or #TBL pins.
7.7 Lock Down
The default state of lock down bit for any block is unlocked. This bit can be set only once; any further
attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit.
Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be
set or cleared, and keep its current state.
- 12 -
W39V040FC
8. TABLE OF OPERATING MODES
8.1 Operating Mode Selection - Programmer Mode
PINS
MODE
#OE
VIL
VIH
X
#WE
VIH
VIL
X
#RESET
VIH
ADDRESS
DQ.
Dout
Read
AIN
AIN
X
Write
VIH
Din
Standby
VIL
High Z
VIL
X
X
VIH
X
High Z/DOUT
High Z/DOUT
High Z
Write Inhibit
VIH
X
VIH
X
Output Disable
VIH
VIH
X
8.2 Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected.
When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".
8.3 FWH Cycle Definition
NO. OF
CLOCKS
FIELD
DESCRIPTION
"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle. 0000b" appears on FWH bus to indicate the initial
START
1
IDSEL
MSIZE
TAR
1
1
2
This one clock field indicates which FWH component is being selected.
Memory Size. There is always show “0000b” for single byte access.
Turned Around Time
Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and
Address[3:0] on FWH[3:0] last.)
ADDR
7
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
SYNC
DATA
N
2
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then DQ[7:4]
on FWH[3:0] last.)
Publication Release Date: Apr. 11, 2006
- 13 -
Revision A1
W39V040FC
8.4 TABLE OF COMMAND DEFINITION
COMMAND
NO. OF
1ST CYCLE
2ND CYCLE
3RD
4TH CYCLE
5TH
6TH CYCLE
CYCLE
CYCLE
DESCRIPTION
CYCLES
(1)
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
Read
1
6
AIN
DOUT
Sector Erase
5555 AA
2AAA 55 5555 80 5555 AA
2AAA 55 5555 80 5555 AA
2AAA
55
SA(5) 30
PA(6) 50
Page Erase
6
5555 AA
2AAA
55
Byte Program
4
3
3
1
5555 AA
5555 AA
5555 AA
XXXX F0
2AAA 55 5555 A0 AIN
2AAA 55 5555 90
2AAA 55 5555 F0
DIN
Product ID Entry
Product ID Exit (4)
Product ID Exit (4)
Notes: 1. The cycle means the write command cycle not the FWH clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]
3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 7XXXXh for Unique Sector 7 (boot sector)
SA = 6XXXXh for Unique Sector6
SA = 5XXXXh for Unique Sector5
SA = 4XXXXh for Unique Sector4
6. PA: Page Address
SA = 3XXXXh for Unique Sector3
SA = 2XXXXh for Unique Sector2
SA = 1XXXXh for Unique Sector1
SA = 0XXXXh for Unique Sector0
PA = 7E000-7FFFFh for Unique page 15
PA = 7C000-7DFFFh for Unique page 14
PA = 7A000-7BFFFh for Unique page 13
PA = 78000-79FFFh for Unique page 12
PA = 76000-77FFFh for Unique page 11
PA = 74000-75FFFh for Unique page 10
PA = 72000-73FFFh for Unique page 9
PA = 70000-71FFFh for Unique page 8
PA = 6E000-6FFFFh for Unique page 7
PA = 6C000-6DFFFh for Unique page 6
PA = 6A000-6BFFFh for Unique page 5
PA = 68000-69FFFh for Unique page 4
PA = 66000-67FFFh for Unique page 3
PA = 64000-65FFFh for Unique page 2
PA = 62000-63FFFh for Unique page 1
PA = 60000-61FFFh for Unique page 0
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W39V040FC
9. EMBEDDED PROGRAMMING ALGORITHM
Start
Write Program Command Sequence
(see below)
#Data Polling/ Toggle bit
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Publication Release Date: Apr. 11, 2006
Revision A1
- 15 -
W39V040FC
10. EMBEDDED ERASE ALGORITHM
Start
Write Erase Command Sequence
(see below)
#Data Polling or Toggle Bit
Erasure Completed
Individual Sector Erase
Command Sequence
(Address/Command):
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
OR
Page Address/50H
- 16 -
W39V040FC
11. EMBEDDED #DATA POLLING ALGORITHM
Start
Read Byte
(DQ0 - DQ7)
Address = SA or PA
Yes
DQ7 = Data
?
No
No
DQ5 = 1
Yes
Read Byte
(DQ0 - DQ7)
Address = SA or PA
Yes
DQ7 = Data
No
Fail
Pass
Note: SA/PA
= Valid address for programming. During a
sector/page erase operation, a valid address is an address within
any sector/page selected for erasure.
Publication Release Date: Apr. 11, 2006
Revision A1
- 17 -
W39V040FC
12. EMBEDDED TOGGLE BIT ALGORITHM
Start
Read Byte
(DQ0-DQ7)
Read Byte
(DQ0-DQ7)
No
Toggle Bit
=Toggle ?
Yes
No
DQ5 = 1 ?
Yes
Read Byte
(DQ0-DQ7) Twin
No
Toggle Bit
=Toggle ?
Pass
Fail
Note: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
- 18 -
W39V040FC
13. SOFTWARE PRODUCT IDENTIFICATION AND BOOT BLOCK LOCKOUT
DETECTION ACQUISITION FLOW
Product
Product
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Identification
Entry (1)
Identification Exit(6)
Load data AA
to
address 5555
Load data AA
to
address 5555
(2)
(2)
(4)
Load data 55
to
address 2AAA
Load data 55
to
Read address = 00000
data = DA
address 2AAA
Load data 90
to
address 5555
Load data F0
to
address 5555
Read address = 00001
data = 50
Read address = 7FFF2
Check DQ[3:0] of data
outputs
Pause 10
S
μ
μ
S
Pause 10
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) The DQ[3:2] to indicate the sector s protect status as below:
DQ2
DQ3
0
1
64Kbytes Boot Block Unlocked by #TBL
hardware trapping
Whole Chip Unlocked by #WP hardware trapping Except
Boot Block
64Kbytes Boot Block Locked by #TBL
hardware trapping
Whole Chip Locked by #WP hardware trapping Except
Boot Block
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout
detection.
Publication Release Date: Apr. 11, 2006
- 19 -
Revision A1
W39V040FC
14. ELECTRICAL CHARACTERISTICS
14.1 Absolute Maximum Ratings
PARAMETER
Operating Temperature
RATING
UNIT
°C
°C
V
0 to +70
-65 to +150
Storage Temperature
Power Supply Voltage to VSS Potential
D.C. Voltage on Any Pin to Ground Potential
VPP Voltage
-0.5 to +4.0
-0.5 to VDD +0.5
-0.5 to +13
V
V
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-1.0 to VDD +0.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability
of the device.
14.2 Programmer interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
LIMITS
PARAMETER
Power Supply
SYM.
TEST CONDITIONS
UNIT
MIN. TYP.
MAX.
In Read or Write mode, all DQs open
Address inputs = 3.0V/0V, at f = 3 MHz
mA
ICC
ILI
-
-
-
15
-
30
Current
Input Leakage
Current
VIN = VSS to VDD
90
90
μA
μA
Output Leakage
Current
ILO VOUT = VSS to VDD
-
Input Low Voltage
Input High Voltage
Output Low Voltage
VIL
-
-
-0.5
2.0
-
-
-
-
-
0.8
VDD +0.5
0.45
V
V
V
V
VIH
VOL IOL = 2.1 mA
Output High Voltage VOH IOH = -0.1mA
2.4
-
- 20 -
W39V040FC
14.3 FWH Interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
LIMITS
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MIN.
TYP.
MAX.
Power Supply Current
Read
All Iout = 0A, CLK = 33 MHz,
in FWH mode operation.
ICC
ICC
-
15
25
mA
mA
Power Supply Current
Program/Erase
CLK = 33 MHz,
in FWH mode operation.
-
-
18
20
30
50
FWH4 = 0.9 VDD, CLK = 33 MHz,
Standby Current 1
Isb1
Isb2
uA
all inputs = 0.9 VDD / 0.1 VDD
no internal operation
FWH4 = 0.1 VDD, CLK = 33 MHz,
Standby Current 2
Input Low Voltage
-
3
10
mA
all inputs = 0.9 VDD /0.1 VDD
no internal operation.
VIL
VILI
VIH
VIHI
-
-
-
-
-0.5
-0.5
-
-
-
-
0.3 VDD
0.2 VDD
V
V
V
V
Input Low Voltage of
#INIT
Input High Voltage
0.5 VDD
1.35 V
VDD +0.5
VDD +0.5
Input High Voltage of
#INIT Pin
Output Low Voltage
Output High Voltage
VOL IOL = 1.5 mA
VOH IOH = -0.5 mA
-
-
-
0.1 VDD
-
V
V
0.9 VDD
14.4 Power-up Timing
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
SYMBOL
TPU. READ
TPU. WRITE
TYPICAL
100
UNIT
μS
5
mS
14.5 Capacitance
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
MAX.
12
UNIT
pf
CIN
VIN = 0V
6
pf
Publication Release Date: Apr. 11, 2006
Revision A1
- 21 -
W39V040FC
14.6 Programmer Interface Mode AC Characteristics
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
Input Rise/Fall Time
Input/Output Timing Level
Output Load
0V to 0.9 VDD
< 5 nS
1.5V/1.5V
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+3.3V
1.8K
Ω
DOUT
Input
Output
30 pF
(Including Jig and
Scope)
0.9VDD
1.3K
1.5V
Ω
1.5V
0V
Test Point
Test Point
14.7 Read Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
W39V040FC
MIN. MAX.
PARAMETER
SYMBOL
UNIT
Read Cycle Time
TRC
350
50
50
-
-
nS
nS
nS
nS
nS
nS
nS
nS
Row / Column Address Set Up Time
Row / Column Address Hold Time
Address Access Time
-
-
TAS
TAH
TAA
150
75
-
Output Enable Access Time
#OE Low to Active Output
#OE High to High-Z Output
Output Hold from Address Change
TOE
TOLZ
TOHZ
TOH
-
0
-
35
-
0
- 22 -
W39V040FC
14.8 Write Cycle Timing Parameters
PARAMETER
Reset Time
SYMBOL
TRST
TAS
MIN.
1
TYP.
MAX.
UNIT
μS
nS
nS
nS
nS
nS
nS
nS
nS
μS
S
-
-
Address Setup Time
50
50
50
100
100
50
50
0
-
-
Address Hold Time
TAH
-
-
R/#C to Write Enable High Time
#WE Pulse Width
TCWH
TWP
-
-
-
-
-
#WE High Width
TWPH
TDS
-
Data Setup Time
-
-
Data Hold Time
TDH
-
-
-
#OE Hold Time
TOEH
TBP
-
Byte programming Time
Sector Erase Cycle Time (Note 2)
Page Erase Cycle Time (Note 2)
Program/Erase Valid to RY/#BY Delay
-
10
0.6
0.3
-
200
6
TPEC
TPEC2
TBUSY
-
-
6
S
90
-
nS
Notes: 1. All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
2. Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm,
all bytes are programmed to 00H before erasure
14.9 Data Polling and Toggle Bit Timing Parameters
W39V040FC
PARAMETER
SYMBOL
UNIT
MIN.
MAX.
350
350
-
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
Toggle or Polling interval
TOEP
TOET
-
-
-
nS
nS
50
mS
Note1: Minimum timing interval between Toggle-check or Polling-check is required for sector /page erase only
Publication Release Date: Apr. 11, 2006
Revision A1
- 23 -
W39V040FC
15. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
15.1 Read Cycle Timing Diagram
#RESET
T
RST
TRC
Row Address
Column Address
Row Address
A[10:0]
R/#C
Column Address
T
AS
T
T
AS
T
AH
AH
VIH
#WE
#OE
T
AA
OH
T
TOE
TOHZ
T
OLZ
High-Z
High-Z
DQ[7:0]
Data Valid
15.2 Write Cycle Timing Diagram
TRST
#RESET
Column Address
Row Address
A[10:0]
TAS
TAS
TAH
TAH
R/
#C
TCWH
TOEH
#OE
#WE
TWP
TWPH
TDH
TDS
Data Valid
DQ[7:0]
- 24 -
W39V040FC
Timing Waveforms for Programmer Interface Mode, continued
15.3 Program Cycle Timing Diagram
Byte Program Cycle
A[10:0]
2AAA
55
Programmed Address
(Internal A[18:0])
DQ[7:0]
5555
5555
A0
Data-In
AA
R/#C
#OE
#WE
TWPH
BP
T
WP
T
Internal Write Start
Byte 0
Byte 1
Byte 2
Byte 3
RY/#BY
TBUSY
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
15.4 #DATA Polling Timing Diagram
A[10:0]
(Internal A[18:0])
An
An
An
An
R/#C
#WE
#OE
TOEP
X
X
DQ7
X
X
BP
T
RY/#BY
BUSY
T
Publication Release Date: Apr. 11, 2006
Revision A1
- 25 -
W39V040FC
Timing Waveforms for Programmer Interface Mode, continued
15.5 Toggle Bit Timing Diagram
A[10:0]
R/#C
#WE
#OE
TOET
DQ6
TBP
RY/#BY
15.6 Sector /Page Erase Timing Diagram
Six-byte code for 3.3V-only
Sector/Page Erase
A[10:0]
5555
AA
2AAA
55
(Internal A[18:0])
DQ[7:0]
5555
80
5555
AA
2AAA
55
SA/PA
30/50
R/#C
#OE
#WE
T
WP
T
PEC
T
WPH
Internal Erase starts
SB0
SB2
SB3
SB5
SB4
SB1
RY/#BY
Note: The internal address A[18:0] are converted from external Column/Row addres
Column/Row Address are mapped to the Low/High order internal address
i.e. Column Address A[10:0] are mapped to the internal A[10:0]
Row Address A[7:0] are mapped to the internal A[18:11].
T
BUSY
SA = Sector Address,PA=Page address, Please ref. to the "Table of Command Definition
- 26 -
W39V040FC
16. FWH INTERFACE MODE AC CHARACTERISTICS
16.1 AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0.6 VDD to 0.2 VDD
1 V/nS
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
0.4VDD / 0.4VDD
1 TTL Gate and CL = 10 pF
16.2 Read/Write Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W39V040FC
MIN. MAX.
UNIT
Clock Cycle Time
TCYC
TSU
THD
TKQ
30
7
-
nS
nS
nS
nS
Input Set Up Time
Input Hold Time
-
-
0
Clock to Data Valid
2
11
Note: Minimum and Maximum time have different load. Please refer to PCI specification.
16.3 Reset Timing Parameters
PARAMETER
VDD stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
SYMBOL
TPRST
TKRST
TRSTP
TRSTF
TRST
MIN.
1
TYP.
MAX.
UNIT
mS
μS
-
-
-
-
-
-
-
100
100
-
-
nS
Reset Active to Output Float
Reset Inactive to Input Active
50
-
nS
10
μS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Please refer to the AC testing condition.
Publication Release Date: Apr. 11, 2006
Revision A1
- 27 -
W39V040FC
17. TIMING WAVEFORMS FOR FWH INTERFACE MODE
17.1 Read Cycle Timing Diagram
TCYC
CLK
#RESET
FWH4
T
SU THD
TSU THD
TKQ
Start
FWH
Read
M Size
IDSEL
Address
A[15:12] A[11:8] A[7:4]
TAR
0000b 1111b Tri-State 0000b
2 Clocks 1 Clock Data out 2 Clocks
Next Start
0000b
TAR
Data
Sync
A[18:16]
XA[22]XXb
D[3:0]
FWH[3:0]
XXXXb
A[3:0]
D[7:4]
1111b Tri-State
2 Clocks
1101b
0000b
Load Address in 7
Clocks
1 Clock
1 Clock
1 Clock
Note: When A22 = high, the host will read the BIOS code from the FWH device.
While A22 = low, the host will read the GPI (Add = FFBC0100) or
Product ID (Add = FFBC0000/FFBC0001) from the FWH device
17.2 Write Cycle Timing Diagram
T
CYC
CLK
#RESET
FWH4
T
T
SU HD
Start
FWH
TAR
1111b
2 Clocks
TAR
Sync
0000b
M Size
0000b
Address
Next Start
IDSEL
0000b
Data
D[7:4]
Load Data in 2 Clocks
Write
XXXXb XXXXb
A[15:12] A[11:8]
A[7:4]
Tri-State
Tri-State 0000b
FWH[3:0]
1110b
A[3:0]
D[3:0]
1111b
A[18:16]
1 Clock
2 Clocks
1 Clock
Load Address in 7 Clocks
1 Clock
1 Clock
- 28 -
W39V040FC
Timing Waveforms, for FWH Interface Mode, continued
17.3 Program Cycle Timing Diagram
CLK
#RESET
FWH4
Start next
Data
TAR
Sync
0000b
TAR
Address
M
Size
IDSEL
1st Start
1110b
command
XXXXb
XXXXb
XXXXb
0101b
0101b
0101b
0000b
1111b
FWH[3:0
]
X101b
Tri-State
1111b
Tri-State
0000b
1010b
1010b
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X010b
Data
TAR
TAR
M
Size
Sync
0000b
IDSEL
2nd Start
1110b
FWH[3:0
]
XXXXb
1010b
1010b
1010b
0000b
XXXXb
1111b
1111b
Tri-State
Tri-State
XXXXb
0101b
0101b
0000b
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock
Load Address "2AAA" in 7 Clocks
2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
TAR
TAR
Sync
0000b
Address
IDSEL
M Size
3rd Start
1110b
]
XXXXb
FWH[3:0
XXXXb
0000b
1111b
1111b
Tri-State
Tri-State
XXXXb
X101b
0101b
0101b
0101b
0000b
1010b
0000b
Load Data "A0"
in 2 Clocks
2 Clocks
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
2 Clocks
1 Clock
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
Internal
FWH4
program start
Address
Data
TAR
TAR
Sync
IDSEL
M
Size
4th Start
1110b
A[18:16]
A[15:12]
A[11:8]
A[7:4]
]
XXXXb
A[3:0]
FWH[3:0
XA[22]XXb
1111b
Tri-State
0000b
1111b
Tri-State
Internal
0000b
D[7:4]
D[3:0]
0000b
program start
Load Din in 2 Clocks
2 Clocks
2 Clocks
1 Clock
1 Clock
Load Ain in 7 Clocks
1 Clock
Write the 4th command(target location to be programmed) to the device in FWH mode.
Publication Release Date: Apr. 11, 2006
Revision A1
- 29 -
W39V040FC
Timing Waveforms for FWH Interface Mode, continued
17.4 #DATA Polling Timing Diagram
CLK
#RESET
FWH4
Data
TAR
Sync
M Size
TAR
1111b
2 Clocks
Next Start
1 Clock
Address
An[15:12]
Start
1110b
IDSEL
0000b
XXXXb
XXXXb
An[18:16]
Dn[3:0] Dn[7:4]
An[7:4]
An[3:0]
0000b
1111b
2 Clocks
0000b
FWH[3:0]
An[11:8]
Tri-State
Tri-State
Load Data "Dn"
in 2 Clocks
1 Clock
Load Address "An" in 7 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
XXXXb
FWH4
M Size
TAR
1111b
2 Clocks
Next Start
1 Clock
Address
An[15:12]
TAR
Tri-State 0000b
1 Clock
Start
1101b
Sync
Data
IDSEL
0000b
XXXXb
XXXXb
An[18:16]
An[11:8]
An[7:4]
An[3:0]
0000b
FWH[3:0]
1111b
XXXXb Dn7,xxx
Tri-State
1 Clock
2 Clocks
Read the DQ7 to see if the internal write complete or not.
1 Clock
Load Address in 7 Clocks
Data out 2 Clocks
CLK
#RESET
FWH4
TAR
Next Start
1 Clock
Address
An[15:12]
TAR
Tri-State 0000b
1 Clock
IDSEL
0000b
M Size
Start
1101b
Sync
Data
XXXXb
XXXXb
An[18:16]
FWH[3:0]
An[11:8]
An[7:4]
An[3:0]
1111b
2 Clocks
XXXXb
Dn7,xxx 1111b
Tri-State
0000b
Load Address in 7 Clocks
Data out 2 Clocks
2 Clocks
1 Clock
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 30 -
W39V040FC
Timing Waveforms for FWH Interface Mode, continued
17.5 Toggle Bit Timing Diagram
CLK
#RESET
FWH4
Data
D[7:4]
TAR
TAR
1111b
2 Clocks
Next Start
1 Clock
Sync
0000b
Address
A[18:16] A[15:12]
M Size
Start
1110b
IDSEL
0000b
XXXXb
XXXXb
A[7:4]
A[3:0]
0000b
Tri-State
D[3:0]
1111b
2 Clocks
FWH[3:0]
A[11:8]
Tri-State
Load Data "Dn"
in 2 Clocks
1 Clock
Load Address "An" in 7 Clocks
1 Clock
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
FWH4
TAR
1111b
Next Start
1 Clock
TAR
Tri-State 0000b
1 Clock Data out 2 Clocks
Address
XXXXb
Start IDSEL
M Size
Sync
Data
0000b
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb XXXXb
0000b
XXXXb
FWH[3:0]
1101b
1111b
X,D6,XXb
Tri-State
2 Clocks
1 Clock
2 Clocks
Read the DQ6 to see if the internal write complete or not.
1 Clock
Load Address in 7 Clocks
CLK
#RESET
FWH4
TAR
1111b
2 Clocks
Next Start
1 Clock
Address
TAR
Tri-State 0000b
2 Clocks 1 Clock Data out 2 Clocks
When internal write complete, the DQ6 will stop toggle.
Start
1101b
Sync
Data
IDSEL
0000b
M Size
XXXXb
XXXXb
0000b
1111b
FWH[3:0]
XXXXb
XXXXb
XXXXb
XXXXb
Tri-State
XXXXb
XXXXb
X,D6,XXb
Load Address in 7 Clocks
1 Clock
1 Clock
Publication Release Date: Apr. 11, 2006
Revision A1
- 31 -
W39V040FC
Timing Waveforms for FWH Interface Mode, continued
17.6 Sector /Page Erase Timing Diagram
CLK
#RESET
FWH4
Start next
command
M Size
0000b
Data
1010b 1010b
TAR
1111b
TAR
Sync
0000b
Address
X101b
1st Start IDSEL
FWH[3:0]
0000b
1110b
XXXXb
XXXXb
Tri-State
2 Clocks
XXXXb
0101b
0101b
0101b
1111b
Tri-State
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Address
X010b
Data
0101b
TAR
1111b
2 Clocks
TAR
1111b
2 Clocks
M
Sync
0000b
IDSEL
0000b
2nd Start
1110b
Size
FWH[3:0]
XXXXb
XXXXb
0000b
Tri-State
XXXXb
1010b
1010b
1010b
0101b
Tri-State
Load Data "55"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
M Size
0000b
Data
0000b 1000b
TAR
Tri-State
2 Clocks
TAR
Tri-State
2 Clocks
Sync
Address
X101b
Load Address "5555" in 7 Clocks
3rd Start IDSEL
1110b 0000b
XXXXb
FWH[3:0]
XXXXb
0000b
XXXXb
1111b
0101b
0101b
0101b
1111b
Load Data "80"
in 2 Clocks
1 Clocks
1 Clocks1 Clocks
1 Clocks
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
M Size
0000b
Data
1010b
Address
X101b
TAR
TAR
1111b Tri-State
2 Clocks
Sync
IDSEL
4th Start
1110b
FWH[3:0]
XXXXb
XXXXb
0101b
0101b
0101b
1010b
1111b
Tri-State 0000b
0000b
XXXXb
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Load Address "5555" in 7 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4
Start next
command
Data
0101b
TAR
1111b Tri-State 0000b
TAR
1111b
Tri-State
2 Clocks
M Size
0000b
Sync
Address
X010b
5th Start IDSEL
FWH[3:0]
XXXXb
1110b
0000b
XXXXb
XXXXb
1010b
1010b
1010b
0101b
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal
erase start
Address
XXXXb
Data
0011b
TAR
1111b
2 Clocks
TAR
M Size
0000b
Sync
0000b
IDSEL
6th Start
1110b
FWH[3:0]
Internal
erase start
XA[22]XXb A[18:16]
1111b Tri-State
2 Clocks
XXXXb
XXXXb XXXXb XXXXb
0000b
Tri-State
0000b
(0101b)
Load Din
in 2 Clocks
1 Clock
1 Clock
Load Sector/Page Address in 7 Clocks
1 Clock
Write the 6th command(target sector to be erased) to the device in FWH mode.
- 32 -
W39V040FC
Timing Waveforms for FWH Interface Mode, continued
17.7 FGPI Register/Product ID Readout Timing Diagram
CLK
#RESET
FWH4
M Size
0000b
IDSEL
0000b
Address
0000b
TAR
Next Sta
1 Clock
TAR
Start
Sync
Data
FWH[3:0]
0001b
/0000b
0000b
/0001b
1101b
Tri-State 1111b
D[3:0]
D[7:4]
A[27:24]
Tri-State 1111b
A[23:20] A[19:16]
0000b
0000b
Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register
& "FFBC0000(hex)/FFBC0001(hex) for Product ID
2 Clocks
1 Clock Data out 2 Clocks
1 Clock 1 Clock
2 Clocks
Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins
17.8 Reset Timing Diagram
VDD
CLK
TPRST
TKRST
TRSTP
#RESET
FWH[3:0]
TRST
TRSTF
FWH4
Publication Release Date: Apr. 11, 2006
Revision A1
- 33 -
W39V040FC
18. ORDERING INFORMATION
ACCESS
TIME
POWER SUPPLY
CURRENT MAX.
STANDBY VDD
CURRENT MAX.
PART NO.
PACKAGE
(NS)
(MA)
(MA)
W39V040FCP
W39V040FCQ
11
11
30
10
32L PLCC
30
10
32L STSOP
32L PLCC
Lead free
W39V040FCPZ
W39V040FCQZ
11
11
30
30
10
10
32L STSOP
Lead free
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
19. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin STSOP W39V040FCQ
W39V040FCQZ
2138977A-A12
345OBFA
1st line: Winbond logo
2nd line: the part number: W39V040FCQZ (Z: For Lead Free)
3rd line: the lot number
4th line: the tracking code: 345 O B FA
149: Packages made in ’03, week 45
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
FA: Process code
- 34 -
W39V040FC
20. PACKAGE DIMENSIONS
20.1 32L PLCC
Dimension in Inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
H E
E
0.140
3.56
A
0.020
0.105
0.026
0.016
0.008
0.50
2.67
0.66
0.41
0.20
A
A
b
b
c
D
E
e
G
G
H
H
L
y
1
2
1
4
1
32
30
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
0.115
0.032
0.022
0.014
2.80
0.71
2.93
0.81
0.56
0.35
0.46
5
29
0.25
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
13.89
11.35
1.12
14.05
11.51
1.42
13.97
11.43
1.27
12.45
9.91
12.95
10.41
14.99
12.45
2.29
13.46
10.92
15.11
12.57
2.41
D
G
D
E
D
E
D
HD
14.86
12.32
1.91
0.10
0
10
0
10
θ
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusio
3. Controlling dimension: Inches
14
20
c
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A
A
θ
e
1
b
b1
Seating Plane
y
E
G
20.2 32L STSOP
HD
D
c
Dimension in Inches Dimension in mm
Symbol
Max.
Min. Nom. Max. Min. Nom.
e
0.047
1.20
A
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
0.15
1
A
E
0.040
1.00
0.22
-----
A2
1.05
0.27
b
0.007 0.009 0.010
b
c
0.004
0.008
0.21
-----
0.488
12.40
8.00
D
E
0.315
0.551
0.020
14.00
D
H
e
0.50
0.60
0.80
0.50
0.70
0.020 0.024 0.028
0.031
L
L
θ
1
A
A
1 A
2
0.000
0.004
0.00
0
0.10
5
L
Y
Y
0
3
5
3
θ
L
1
Publication Release Date: Apr. 11, 2006
Revision A1
- 35 -
W39V040FC
21. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
Apr. 11, 2006
-
Initial Issued
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 36 -
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