W29C011A-15_技术文档

Preliminary W29C011A

128K ´ 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K ´ 8 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is

not required. The unique cell architecture of the W29C011A results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

· Single 5-volt program and erase operations

· Fast page-write operations

· Low power consumption

- Active current: 25 mA (typ.)

- Standby current: 20 mA (typ.)

- 128 bytes per page

- Page program cycle: 10 mS (max.)

- Effective byte-program cycle time: 39 mS

- Software-protected data write

· Fast chip-erase operation: 50 mS

· Read access time: 150 nS

· Automatic program timing with internal VPP

generation

· End of program detection

- Toggle bit

- Data polling

· Latched address and data

· TTL compatible I/O

· JEDEC standard byte-wide pinouts

· Page program/erase cycles: 1,000

· Ten-year data retention

· Software and hardware data protection

· Available packages: 32-pin 600 mil DIP, 450

mil SOP and PLCC

Publication Release Date: December 1997

- 1 -

Revision A1

Preliminary W29C011A

PIN CONFIGURATIONS

BLOCK DIAGRAM

V

DD

32

31

30

29

28

27

26

25

24

V_DD

NC

A16

A15

A12

1

2

3

4

5

6

7

8

9

V

SS

WE

NC

DQ0

CE

OE

WE

.

OUTPUT

BUFFER

CONTROL

A14

A13

A8

DQ7

A7

A6

A9

A5

A4

A3

32-pin

DIP

A11

OE

A2

A1

A0

10

11

12

23

22

21

A10

A0

.

CE

CORE

ARRAY

DQ7

DECODER

13

20

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

.

14

15

16

19

18

17

A16

GND

A

1

2

A

1

6

V

D

/

W

E

A

1

5

N

C

N

C

PIN DESCRIPTION

4

3

1

31 30

32

2

A14

29

28

27

26

25

24

23

22

21

SYMBOL

PIN NAME

5

6

A7

A13

A8

A6

A5

Address Inputs

7

A0- A16

8

A9

A4

32-pin

PLCC

Data Inputs/Outputs

Chip Enable

9

DQ0- DQ7

A11

A3

10

11

12

13

A2

OE

A10

A1

CE

OE

A0

CE

DQ7

Output Enable

Write Enable

Power Supply

Ground

DQ0

14

15

18

16 17

19 20

WE

VDD

GND

NC

D

Q

1

D

Q

2

G

D

Q

4

D

Q

5

D

Q

3

D

Q

6

N

D

No Connection

- 2 -

Preliminary W29C011A

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C011A is controlled by CE and OE, both of which have to be low for

the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29C011A is programmed on a page basis. Every page contains 128 bytes of data. If a byte of

data within a page is to be changed, data for the entire page must be loaded into the device. Any byte

that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists

of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.

Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously

written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,

whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200

mS, after the initial byte-load cycle, the W29C011A will stay in the page load cycle. Additional bytes

can then be loaded consecutively. The page load cycle will be terminated and the internal

programming cycle will start if no additional byte is loaded into the page buffer within 300 mS (TBLCO)

from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last

rising edge of WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer

must have the same page address. A0 to A6 specify the byte address within the page. The bytes may

be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written

simultaneously into the memory array. Before the completion of the internal programming cycle, the

host is free to perform other tasks such as fetching data from other locations in the system to prepare

to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved software-protected data write. Once this scheme is enabled,

any write operation requires a series of three-byte program commands (with specific data to a specific

address) to be performed before the data load operation. The three-byte load command sequence

begins the page load cycle, without which the write operation will not be activated. This write scheme

provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during

system power-up and power-down.

The W29C011A is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte program command cycle.

Publication Release Date: December 1997

- 3 -

Revision A1

Preliminary W29C011A

Hardware Data Protection

The integrity of the data stored in the W29C011A is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

3.8V.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ7)-Write Status Detection

The W29C011A includes a data polling feature to indicate the end of a programming cycle. When

the W29C011A is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded

during the page/byte-load cycle will receive the complement of the true data. Once the programming

cycle is completed. DQ7 will show the true data.

Toggle Bit (DQ6)-Write Status Detection

In addition to data polling, the W29C011A provides another method for determining the end of a

program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will

produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's

and 1's will stop. The device is then ready for the next operation.

5-Volt-Only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycles, the device enters the internal chip erase mode, which is automatically timed and will be

completed in 50 mS. The host system is not required to provide any control or timing during this

operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the

software access mode, a six-byte command sequence can be used to access the product ID. A read

from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the

device code (C1h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE

high, and raising A9 to 12 volts.

- 4 -

Preliminary W29C011A

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE

PINS

ADDRESS

DQ.

CE OE WE

Read

VIL VIL

VIL VIH

VIH AIN

VIL AIN

Dout

Din

Write

Standby

VIH

X

VIL

X

High Z

Write Inhibit

High Z/DOUT

High Z

X

VIH

X

Output Disable

X

VIH

5-Volt Software Chip Erase VIL VIH VIL AIN

DIN

Product ID

VIL VIL VIH A0 = VIL; A1-A16 = VIL;

A9 = VHH

Manufacturer Code

DA (Hex)

VIL VIL VIH A0 = VIH; A1-A16 = VIL;

A9 = VHH

Device Code

C1 (Hex)

Publication Release Date: December 1997

Revision A1

- 5 -

Preliminary W29C011A

Command Codes for Software Data Protection Write

BYTE SEQUENCE

0 Write

ADDRESS

5555H

DATA

AAH

55H

1 Write

2AAAH

5555H

2 Write

A0H

Software Data Protection Acquisition Flow

Software Data Protection

Write Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Load 0 to

128 bytes of

page data

Pause 10 mS

Exit

Notes for software program code:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

- 6 -

Preliminary W29C011A

Command Codes for Software Chip Erase

BYTE SEQUENCE

0 Write

ADDRESS

DATA

AAH

55H

5555H

2AAAH

5555H

2AAAH

5555H

1 Write

2 Write

80H

3 Write

AAH

55H

4 Write

5 Write

10H

Software Chip Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Notes for software chip erase:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

Publication Release Date: December 1997

Revision A1

- 7 -

Preliminary W29C011A

Command Codes for Product Identification

BYTE SEQUENCE

SOFTWARE PRODUCT

IDENTIFICATION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION EXIT

ADDRESS

5555H

DATA

AAH

55H

ADDRESS

DATA

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

5555H

AAH

2AAAH

5555H

2AAAH

55H

80H

5555H

F0H

5555H

AAH

55H

-

2AAAH

5555H

60H

Pause 10 mS

Software Product Identification Acquisition Flow

Product Identification Entry(1)

Product Identification Exit(1)

Product Identification Mode(2,3)

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data AA

to

address 5555

Load data 80

to

address 5555

Load data 55

to

address 2AAA

Read address = 0

data = DA

Load data AA

to

address 5555

Load data FO

to

address 5555

Load data 55

to

address 2AAA

Read address = 1

data = C1

Sm

m

Pause 10

(4)

Load data 60

to

address 5555

Normal Mode

Pause 10

S

m

Notes for software product identification:

(1) Data format: DQ7- DQ0 (Hex); address format: A14- A0 (Hex).

(2) A1- A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification mode if power down.

(4) The device returns to standard operation mode.

- 8 -

Preliminary W29C011A

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

-0.5 to +7.0

0 to +70

UNIT

V

Power Supply Voltage to Vss Potential

Operating Temperature

°C

V

Storage Temperature

-65 to +150

-0.5 to VDD +1.0

D.C. Voltage on Any Pin to Ground Potential except OE

¡ Õ

Transient Voltage ( 20 nS ) on Any Pin to Ground Potential

-1.0 to VDD +1.0

-0.5 to 12.5

V

Voltage on OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

Operating Characteristics

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

TYP.

-

UNIT

MIN.

MAX.

Power Supply

Current

ICC

-

50

mA

CE OE

WE

= VIH,

=

= VIL,

all I/Os open

Address inputs = VIL/VIH,

at f = 5 MHz

Standby VDD

ISB1

-

2

3

mA

CE

= VIH, all I/Os open

Other inputs = VIL/VIH

CE

Current (TTL input)

Standby VDD Current ISB2

(CMOS input)

20

100

mA

= VDD -0.3V, all I/Os open

Other inputs = VDD -0.3V/GND

VIN = GND to VDD

Input Leakage

Current

ILI

-

1

mA

Output Leakage

Current

ILO VIN = GND to VDD

10

Input Low Voltage

Input High Voltage

Output Low Voltage

VIL

-

-0.3

2.0

-

0.8

VDD +0.5

0.45

V

VIH

VOL IOL = 2.1 mA

Output High Voltage VOH IOH = -0.4 mA

2.4

-

Power-up Timing

PARAMETER

Power-up to Read Operation

Power-up to Write Operation

SYMBOL

TYPICAL

UNIT

TPU.READ

100

5

mS

TPU.WRITE

mS

Publication Release Date: December 1997

Revision A1

- 9 -

Preliminary W29C011A

CAPACITANCE

(VDD = 5.0V, TA = 25° C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CONDITIONS

VI/O = 0V

MAX.

12

UNIT

pF

CI/O

CIN

VIN = 0V

6

pF

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5V ±10%)

PARAMETER

Input Pulse Levels

CONDITIONS

0.45V to 2.4V

Input Rise/Fall Time

Input/Output Timing Level

Output Load

10 nS

0.8V/2.0V

1 TTL Gate and CL = 100 pF

AC Test Load and Waveforms

+5V

1.8K ohm

D

OUT

100 pF

1.3K ohm

Input/Output

2.4V

2.0V

0.8V

2.0V

0.8V

0.45V

Test Point

- 10 -

Preliminary W29C011A

Read Cycle Timing Parameters

(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)

PARAMETER

SYM.

W29C011A-15

UNIT

MIN.

MAX.

-

Read Cycle Time

TRC

TCE

TAA

TOE

150

nS

Chip Enable Access Time

Address Access Time

Output Enable Access Time

-

150

70

-

TCLZ

TOLZ

TCHZ

TOHZ

0

-

CE

OE

CE

OE

Low to Active Output

High to High-Z Output

0

-

nS

45

-

Output Hold from Address change TOH

0

Byte/Page-Write Cycle Timing Parameters

PARAMETER

Write Cycle (erase and program)

Address Setup Time

SYMBOL

MIN.

TYP.

MAX.

UNIT

TWC

TAS

TAH

TCS

-

0

-

10

-

mS

nS

Address Hold Time

50

0

-

WE and CE Setup Time

WE and CE Hold Time

OE High Setup Time

OE High Hold Time

CE Pulse Width

TCH

0

10

70

150

-

nS

TOES

TOEH

TCP

TWP

TWPH

WE Pulse Width

WE High Width

Data Setup Time

TDS

50

10

-

nS

mS

Data Hold Time

TDH

-

200

-

Byte Load Cycle Time

Byte Load Cycle Time-out

TBLC

TBLCO

0.22

300

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

Publication Release Date: December 1997

Revision A1

- 11 -

Preliminary W29C011A

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYM.

W29C011A-15

UNIT

MIN.

MAX.

TOEP

-

70

nS

OE

CE

OE

CE

to Data Polling Output Delay

to Toggle Bit Output Delay

TCEP

TOET

TCET

150

70

150

TIMING WAVEFORMS

Read Cycle Timing Diagram

T_RC

Address A16-0

CE

T_CE

T_OE

OE

T_OHZ

T_OLZ

V

IH

WE

T_CLZ

T

OH

T_CHZ

Data Valid

High-Z

DQ7-0

Data Valid

TAA

- 12 -

Preliminary W29C011A

Timing Waveforms, continued

Page Write Timing Diagram

TWC

Byte/page load

cycle starts

Three-byte sequence for

software data protection mode

Address A16-0

2AAA

5555

DQ6

CE

A0

AA

55

OE

TBLC

T

TWP

BLCO

WE

TWPH

Byte N

(last byte)

Byte 0

Byte N-1

SW1

SW2

SW0

Internal write starts

Note

Notes: Refer to "

( WE ) Controlled Write Cycle Timing Diagram" for a detailed timing diagram.

CE

WE Controlled Write Cycle Timing Diagram

T_BLCO

T_WC

T_AS

T_AH

Address A16-0

CE

T_CS

T_CH

T_OES

TOEH

OE

T_WP

T_WPH

WE

T_DS

DQ7-0

Data Valid

T_DH

Internal write starts

Publication Release Date: December 1997

Revision A1

- 13 -

Preliminary W29C011A

Timing Waveforms, continued

CE Controlled Write Cycle Timing Diagram

T_BLCO

AS

T

T_WC

TAH

Address A16-0

T_CPH

T_CP

CE

T_OES

T_OEH

OE

WE

T_DS

High Z

DQ7-0

Data Valid

T_DH

Internal Write Starts

DATA Polling Timing Diagram

Address A16-0

WE

TCEP

CE

OE

TOES

T

OEH

T

OEP

DQ7-0

X

TWC

- 14 -

Preliminary W29C011A

Timing Waveforms, continued

Toggle Bit Timing Diagram

Address A16-0

WE

CE

OE

TOES

TOEH

DQ6

T

WC

5 Volt-Only Software Chip Erase Timing Diagram

Six-byte code for 5V-only software

WC

T

chip erase

Address A16-0

5555

2AAA

55

5555

2AAA

DQ7-0

CE

80

AA

55

10

AA

OE

WP

T

BLC

T

BLCO

T

WE

WPH

T

SW0

SW2

SW3

SW5

SW4

SW1

Internal programming starts

Publication Release Date: December 1997

Revision A1

- 15 -

Preliminary W29C011A

ORDERING INFORMATION

PART NO.

ACCESS TIME

(nS)

POWER SUPPLY

CURRENT MAX. (mA)

STANDBY VDD

CURRENT MAX. (mA)

PACKAGE

W29C011A-15

W29C011AS-15

W29C011AP-15

150

50

100

600 mil DIP

450 mil SOP

32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

- 16 -

Preliminary W29C011A

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in inches

Min. Nom. Max. Min. Nom. Max.

Dimension in mm

Symbol

A

5.33

0.210

0.010

0.150 0.155 0.160 3.81

0.016 0.018 0.41

0.048 0.050 0.054 1.22

0.25

A

A₂

B

B1

c

D

1

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

0.022

0.20

0.010 0.014

1.650 1.660

0.008

D

17

32

41.91 42.16

15.49

14.10

2.79

0.610

15.24

13.97

2.54

0.590 0.600

14.99

13.84

E

E₁

e₁

0.545 0.550 0.555

0.110

0.090 0.100

2.29

3.05

0

E₁

0.120

0

0.140

15

3.30

L

a

0.130

3.56

15

e_A

17.02

0.630 0.650 0.670 16.00 16.51

0.085

2.16

S

16

1

Notes:

E

S

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

c

2.Dimension E1 does not include interlead flash.

2

A

L

A₁

Base Plane

3.Dimensions D & E1 include mold mismatch and

.

are determined at the mold parting line.

4.Dimension B1 does not include dambar

protrusion/intrusion.

Seating Plane

5.Controlling dimension: Inches.

6.General appearance spec. should be based on

final visual inspection spec.

B

e1

e_A

a

B₁

32-pin SO Wide Body

Dimension in mm

Dimension in Inches

Symbol

A

17

32

Nom.

Min.

Max. Min.

0.118

Max.

3.00

e₁

0.004

0.10

A

b

c

1

0.101 0.106 0.111

2.57

0.36

0.15

2.69

0.41

2.82

0.51

2

0.014

0.016

0.020

0.012

0.817

0.450

0.20

0.31

0.006 0.008

0.805

E H

E

20.45

20.75

11.43

1.42

D

E

e

11.18

1.12

0.440 0.445

11.30

1.27

0.044 0.050 0.056

L

0.546 0.556 0.556 13.87 14.12 14.38

E

H

L

Detail F

0.039

0.023 0.031

0.047 0.055

0.79

1.40

0.99

0.58

1.19

1

16

b

0.063

0.036

1.60

0.91

0.10

L_E

S

y

0.004

10

q

10

0

e₁

Notes:

D

1. Dimensions D Max. & S include mold flash

or tie bar burrs.

c

2. Dimension b does not include dambar

protrusion/intrusion.

A

A ₂

3. Dimensions D & E include mold mismatch

.

e

S

and determined at the mold parting line.

y

L

E

A ₁

4. Controlling dimension: Inches.

5. General appearance spec should be based

on final visual inspection spec.

See Detail F

Seating Plane

Publication Release Date: December 1997

Revision A1

- 17 -

Preliminary W29C011A

Package Dimensions, continued

32-pin PLCC

Dimension in Inches

Dimension in mm

Symbol

A

Min. Nom.

Max.

Min. Nom.

Max.

H

E

0.140

3.56

E

0.020

0.50

1

A

4

1

32

30

0.105

0.026

0.016

0.008

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.110

0.115

0.032

0.022

0.014

0.553

0.453

0.056

0.530

0.430

0.595

0.495

2.67

0.66

2.80

2.93

0.81

A

b

c

2

1

0.028

0.018

0.010

0.550

0.450

0.050

0.71

0.46

0.41

0.56

5

29

0.20

0.35

0.25

13.89

11.35

1.12

14.05

11.51

1.42

13.97

11.43

1.27

D

E

e

G_D

G_E

12.45

9.91

12.95

13.46

10.92

15.11

12.57

0.510

0.410

D

G

10.41

D

H

14.86

12.32

0.590

0.490

14.99

12.45

H

D

H_E

L

y

0.075

0.095

0.004

1.91

2.29

2.41

0.10

0.090

°

10

0

10

0

q

21

13

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

c

14

20

4. General appearance spec. should be based on final

visual inspection sepc.

L

2

1

A

e

b

1

Seating Plane

y

G

E

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

Dec. 1997

Initial Issued

- 18 -

Preliminary W29C011A

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-7197006

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: December 1997

Revision A1

- 19 -


型号：	W29C011A-15
厂家：	WINBOND
描述：	128K X 8 CMOS FLASH MEMORY 128K ×8 CMOS FLASH MEMORY
文件：	总19页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W29C011A-15 [WINBOND]

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