W29C020-70B [WINBOND]
256K X 8 CMOS FLASH MEMORY; 256K ×8 CMOS FLASH MEMORY
| 型号： | W29C020-70B |
| 厂家： | 
WINBOND |
| 描述： | 256K X 8 CMOS FLASH MEMORY |
| 文件： | 总21页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W29C020
256K ´ 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K ´ 8 bits. The
device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt
VPP is not required. The unique cell architecture of the W29C020 results in fast write (erase/program)
operations with extremely low current consumption compared to other comparable 5-volt flash
memory products. The device can also be written (erased and programmed) by using standard
EPROM programmers.
FEATURES
· Single 5-volt write (erase and program)
operations
· Software and hardware data protection
· Low power consumption
· Fast page-write operations
- 128 bytes per page
- Active current: 25 mA (typ.)
- Standby current: 20 mA (typ.)
- Page write (erase/program) cycle: 10 mS
(max.)
· Automatic write (erase/program) timing with
internal VPP generation
- Effective byte-write (erase/program) cycle
time: 39 mS
· End of write (erase/program) detection
- Toggle bit
- Optional software-protected data write
· Fast chip-erase operation: 50 mS
· Two 8 KB boot blocks with lockout
- Data polling
· Latched address and data
· All inputs and outputs directly TTL compatible
· JEDEC standard byte-wide pinouts
· Typical page write (erase/program) cycles:
100/1K/10K
· Available packages: 32-pin 600 mil DIP, 450 mil
SOP, TSOP, and 32-pin PLCC
· Read access time: 70/90/120 nS
· Ten-year data retention
Publication Release Date: February 1998
- 1 -
Revision A3
W29C020
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
32
1
DD
VDD
WE
NC
2
3
31
30
29
28
27
A16
A15
A12
A7
VSS
A17
A14
4
5
A13
CE
DQ0
.
.
6
A6
A8
7
26
25
24
23
22
21
20
19
OE
A9
OUTPUT
BUFFER
A5
32-pin
DIP
CONTROL
8
A11
A4
WE
9
A3
DQ7
OE
10
A10
A2
A1
11
12
13
CE
DQ7
A0
DQ0
DQ1
DQ2
GND
DQ6
DQ5
DQ4
DQ3
8K Byte Boot Block (Optional)
14
15
16
A0
.
18
17
CORE
ARRAY
.
DECODER
.
A
1
2
A
1
6
V
D
D
/
W
E
A
1
7
A
1
5
N
C
8K Byte Boot Block (Optional)
A17
4
3
1
2
32 31 30
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A14
A7
A6
A5
A4
A3
A2
A1
A0
A13
A8
32-pin
PLCC
A9
A11
10
11
12
13
OE
A10
CE
DQ7
DQ0
PIN DESCRIPTION
14 15 16 17 18 19 20
D
Q
1
D
Q
2
G
N
D
D
Q
3
D
Q
4
D
Q
5
D
Q
6
SYMBOL
PIN NAME
Address Inputs
A0- A17
1
2
32
31
30
29
28
27
26
25
OE
A10
A11
A9
A8
A13
A14
A17
Data Inputs/Outputs
Chip Enable
DQ0- DQ7
3
4
5
CE
DQ7
DQ6
DQ5
CE
OE
6
7
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
WE
VDD
32-pin
TSOP
8
Output Enable
Write Enable
Power Supply
Ground
9
24
23
22
21
20
19
18
17
NC
A16
10
11
12
13
14
15
16
A15
A12
A7
WE
VDD
GND
NC
A1
A6
A2
A3
A5
A4
No Connection
- 2 -
W29C020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C020 is controlled by CE and OE , both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C020 is written (erased/programmed) on a page basis. Every page contains 128 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.
The write operation is initiated by forcing CE and WE low and OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.
Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE ,
whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever
occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of
200 mS after the initial byte-load cycle, the W29C020 will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal write
(erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify
the page address. All bytes that are loaded into the page buffer must have the same page address.
A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required.
In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal write cycle, the host is
free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29C020 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection
Publication Release Date: February 1998
- 3 -
Revision A3
W29C020
will remain enabled unless the disable commands are issued. A power transition will not reset the
software data protection feature. To reset the device to unprotected mode, a six-byte command
sequence is required. For information about specific codes, see the Command Codes for Software
Data Protection in the Table of Operating Modes. For information about timing waveforms, see the
timing diagrams below.
Hardware Data Protection
The integrity of the data stored in the W29C020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD reaches its sense level, the device will automatically timeout for
5 mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory.
The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command
sequence.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will be disabled. In order to detect
whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes)
or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming
lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the
block can be programmed.
To return to normal operation, perform a three-byte command sequence to exit the identification
mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C020 includes a data polling feature to indicate the end of a write cycle. When the
W29C020 is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.
DQ7 will show the true data. See the DATA Polling Timing Diagram.
- 4 -
W29C020
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C020 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating
0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device
is then ready for the next operation. See Toggle Bit Timing Diagram.
Product Identification
The product ID operation outputs the manufacturer code and device code. The programming
equipment automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed through software or by hardware operation. In
the software access mode, a six-byte command sequence can be used to access the product ID. A
read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001
hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte
command sequence.
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.
TABLE OF OPERATING MODES
Operating Mode Selection
Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V
MODE
PINS
ADDRESS
DQ.
CE OE WE
Read
VIL VIL
VIL VIH
VIH AIN
VIL AIN
Dout
Din
Write
Standby
VIH
X
X
VIL
X
X
X
X
X
X
X
High Z
Write Inhibit
High Z/DOUT
High Z/DOUT
High Z
X
VIH
X
Output Disable
X
VIH
5-Volt Software Chip Erase VIL VIH VIL AIN
DIN
Product ID
VIL VIL
VIH
Manufacturer Code DA
(Hex)
A0 = VIL; A1- A17 = VIL;
A9 = VHH
VIL VIL
VIH
Device Code
45 (Hex)
A0 = VIH; A1- A17 = VIL;
A9 = VHH
Publication Release Date: February 1998
Revision A3
- 5 -
W29C020
Command Codes for Software Data Protection
BYTE SEQUENCE
TO ENABLE PROTECTION
TO DISABLE PROTECTION
ADDRESS
DATA
ADDRESS
5555H
DATA
AAH
55H
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
5555H
AAH
2AAAH
55H
2AAAH
5555H
5555H
A0H
80H
-
-
-
-
-
-
5555H
AAH
55H
2AAAH
5555H
20H
Software Data Protection Acquisition Flow
Software Data Protection
Enable Flow
Software Data Protection
Disable Flow
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data 80
to
address 5555
Load data AA
to
address 5555
Sequentially load
up to 128 bytes
of page data
(Optional page-load
operation)
Load data 55
to
Pause 10 mS
Exit
address 2AAA
Load data 20
to
address 5555
Pause 10 mS
Exit
Notes for software program code:
Data Format: DQ7- DQ0 (Hex)
Address Format: A14- A0 (Hex)
- 6 -
W29C020
Command Codes for Software Chip Erase
BYTE SEQUENCE
0 Write
ADDRESS
DATA
5555H
2AAAH
5555H
5555H
2AAAH
5555H
AAH
55H
80H
AAH
55H
10H
1 Write
2 Write
3 Write
4 Write
5 Write
Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Exit
Notes for software chip erase:
Data Format: DQ7- DQ0 (Hex)
Address Format: A14- A0 (Hex)
Publication Release Date: February 1998
Revision A3
- 7 -
W29C020
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE
ALTERNATE PRODUCT (7)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION EXIT
ADDRESS
DATA
ADDRESS
5555H
DATA
AAH
55H
ADDRESS
DATA
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
5555
AA
55
90
-
5555H
AAH
2AAA
2AAAH
5555H
2AAAH
55H
5555
80H
5555H
F0H
-
-
-
5555H
AAH
55H
-
-
-
-
-
-
-
2AAAH
5555H
-
60H
Pause 10 mS
Pause 10 mS
Pause 10 mS
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Product
Identification
Entry (1)
Product
Identification
Exit (1)
Identification
and Boot Block
Lockout Detection
Mode (3)
Load data AA
to
address 5555
(2)
(2)
(4)
(5)
Load data AA
Load data 55
to
Read address = 00000
data = DA
to
address 2AAA
address 5555
Load data 80
to
address 5555
Load data 55
to
address 2AAA
Read address = 00001
data = 45
Load data AA
to
address 5555
Load data F0
to
address 5555
Read address = 00002
data = FF/FE
Load data 55
to
address 2AAA
Read address = 3FFF2
data = FF/FE
Pause 10 mS
(6)
Load data 60
to
address 5555
Normal Mode
Pause 10 mS
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7- DQ0 (Hex); Address Format: A14- A0 (Hex)
(2) A1- A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if
power down.
(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is
inactivated and the block can be programmed.
(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new
designs, Winbond recommends that the 3 byte command code sequence be used.
- 8 -
W29C020
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE
BOOT BLOCK LOCKOUT FEATURE SET
ON FIRST 8K ADDRESS BOOT BLOCK
BOOT BLOCK LOCKOUT FEATURE SET
ON LAST 8K ADDRESS BOOT BLOCK
ADDRESS
5555H
DATA
AAH
55H
80H
AAH
55H
40H
00H
ADDRESS
5555H
DATA
AAH
55H
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
6 Write
2AAAH
5555H
2AAAH
5555H
80H
5555H
5555H
AAH
55H
2AAAH
5555H
2AAAH
5555H
40H
00000H
3FFFFH
FFH
Pause 10 mS
Pause 10 mS
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set on First 8K
Address Boot Block
Boot Block Lockout
Feature Set on Last 8K
Address Boot Block
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Load data 40
to
address 5555
Load data 00
to
address 00000
Load data FF
to
address 3FFFF
Pause 10 mS
Pause 10 mS
Notes for boot block lockout enable:
1. Data Format: DQ7- DQ0 (Hex)
2. Address Format: A14- A0 (Hex)
3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.
Publication Release Date: February 1998
- 9 -
Revision A3
W29C020
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
-0.5 to +7.0
0 to +70
UNIT
V
Power Supply Voltage to VSS Potential
Operating Temperature
°C
°C
V
Storage Temperature
-65 to +150
-0.5 to VDD +1.0
-1.0 to VDD +1.0
-0.5 to 12.5
D.C. Voltage on Any Pin to Ground Potential Except A9
Transient Voltage (<20 nS ) on Any Pin to Ground Potential
V
V
OE
Voltage on A9 and
Pin to Ground Potential
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
ICC
-
-
50
mA
CE OE
WE
= VIH,
Power Supply Current
=
= VIL,
all DQs open
Address inputs = VIL/VIH,
at f = 5 MHz
ISB1
ISB2
-
-
2
3
mA
CE
Standby VDD Current
(TTL input)
= VIH, all DQs open
Other inputs = VIL/VIH
20
100
mA
CE
open
Standby VDD Current
(CMOS input)
= VDD -0.3V, all DQs
ILI
VIN = GND to VDD
VIN = GND to VDD
-
-
-
-
-
-
-
-
-
10
10
0.8
-
mA
mA
V
Input Leakage Current
Output Leakage Current
Input Low Voltage
ILO
VIL
-
-
VIH
2.0
-
V
Input High Voltage
-
VOL
VOH1
VOH2
IOL = 2.0 mA
0.45
-
V
Output Low Voltage
Output High Voltage
2.4
4.2
V
IOH = -400 mA
-
V
IOH = -100 mA; VCC = 4.5V
Output High Voltage
CMOS
- 10 -
W29C020
Power-up Timing
PARAMETER
SYMBOL
TPU. READ
TPU. WRITE
TYPICAL
UNIT
mS
Power-up to Read Operation
Power-up to Write Operation
100
5
mS
CAPACITANCE
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
DQ Pin Capacitance
Input Pin Capacitance
SYMBOL
CDQ
CONDITIONS
VDQ = 0V
MAX.
12
UNIT
pF
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
AC Test Conditions
(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS)
PARAMETER
CONDITIONS
Input Pulse Levels
Input Rise/Fall Time
Input/Output Timing Level
Output Load
0V to 3V
<5 nS
1.5V/1.5V
1 TTL Gate and CL = 100 pF for 90/120 nS
CL = 30 pF for 70 nS
AC Test Load and Waveform
+5V
1.8K
W
DOUT
100 pF for 90/120 nS
30 pF for 70 nS
(Including Jig and Scope)
1.3K
W
Input
Output
3V
1.5V
1.5V
0V
Test Point
Test Point
Publication Release Date: February 1998
Revision A3
- 11 -
W29C020
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V ±10% for 90 nS and 120 nS; VDD = 5.0V ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM. W29C020-70 W29C020-90 W29C020-12 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
TRC
TCE
TAA
TOE
TCHZ
70
-
-
90
-
-
120
-
nS
nS
nS
nS
nS
Chip Enable Access Time
Address Access Time
70
70
35
25
90
90
40
25
-
-
-
-
120
120
50
-
-
Output Enable Access Time
-
-
-
-
30
CE
OE
High to High-Z Output
High to High-Z Output
TOHZ
TOH
-
25
-
-
25
-
-
30
-
nS
nS
Output Hold from Address change
0
0
0
Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (erase and program)
Address Setup Time
SYMBOL
TWC
MIN.
TYP.
MAX.
UNIT
mS
nS
-
0
-
-
-
-
10
-
TAS
Address Hold Time
TAH
50
0
-
nS
TCS
-
nS
WE and CE Setup Time
WE and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
TCH
0
0
-
-
-
-
-
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
TOES
TOEH
TCP
0
70
70
100
TWP
TWPH
WE Pulse Width
WE High Width
Data Setup Time
Data Hold Time
TDS
TDH
TBLC
50
0
-
-
-
-
-
nS
nS
mS
Byte Load Cycle Time
-
150
Note: All AC timing signals observe the following guideline for determining setup and hold times:
Reference level is VIH for high-level signal and VIL for low-level signal.
- 12 -
W29C020
AC Characteristics, continued
(1)
DA TA Polling Characteristics
PARAMETER
SYMBOL
TDH
MIN.
10
TYP.
MAX.
UNIT
nS
Data Hold Time
-
-
-
-
TOEH
10
nS
OE Hold Time
OE to Output Delay (2)
Write Recovery Time
Notes:
TOE
-
-
-
-
-
nS
nS
TWR
0
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.
(1)
Toggle Bit Characteristics
PARAMETER
Data Hold Time
SYMBOL
TDH
MIN.
10
TYP.
MAX.
UNIT
nS
-
-
-
-
TOEH
10
nS
OE Hold Time
OE to Output Delay (2)
TOE
-
150
0
-
-
-
-
-
-
nS
nS
nS
TOEHP
TWR
OE High Pulse
Write Recovery Time
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.
TIMING WAVEFORMS
Read Cycle Timing Diagram
TRC
Address A17-0
TCE
CE
TOE
OE
TOHZ
VIH
WE
TOH
TCHZ
High-Z
High-Z
DQ7-0
Data Valid
Data Valid
AA
T
Publication Release Date: February 1998
Revision A3
- 13 -
W29C020
Timing Waveforms, continued
WE Controlled Write Cycle Timing Diagram
T
WC
T
AS
T
AH
Address A17-0
CE
T
CS
T
CH
T
OES
T
OEH
WPH
OE
T
WP
T
WE
T
DS
DQ7-0
Data Valid
T
DH
Internal write starts
CE Controlled Write Cycle Timing Diagram
AS
T
TWC
AH
T
Address A17-0
CE
T
WPH
TCP
T
OES
T
OEH
OE
TCS
CH
T
WE
T
DS
High Z
DQ7-0
Data Valid
T
DH
Internal Write Starts
- 14 -
W29C020
Timing Waveforms, continued
Page Write Cycle Timing Diagram
TWC
Address A17-0
DQ7-0
CE
OE
TBLC
TWPH
WP
T
WE
Byte 0
Byte 1
Byte 2
Byte N-1
Byte N
Internal Write Start
DA TA Polling Timing Diagram
Address A15-0
WE
CE
T
OEH
OE
T
DH
T
WR
HIGH-Z
DQ7
T
OE
Publication Release Date: February 1998
Revision A3
- 15 -
W29C020
Timing Waveforms, continued
Toggle Bit Timing Diagram
WE
CE
T
OEH
OE
T
DH
T
OE
T
WR
HIGH-Z
DQ6
Page Write Timing Diagram Software Data Protection Mode
TWC
Byte/page load
Three-byte sequence for
cycle starts
software data protection mode
Address A15-0
2AAA
5555
5555
DQ7-0
CE
AA
55
A0
OE
TBLC
TWP
WE
TWPH
Word N
(last word)
SW2
Word 0
Word N-1
SW1
SW0
Internal write starts
- 16 -
W29C020
Timing Waveforms, continued
Reset Software Data Protection Timing Diagram
Six-byte sequence for resetting
software data protection mode
T
WC
Address A15-0
5555
80
5555
5555
2AAA
55
5555
AA
2AAA
55
DQ7-0
CE
AA
20
OE
T
WP
T
BLC
WE
T
WPH
SW0
SW2
SW3
SW5
SW4
SW1
Internal programming starts
Software Chip Erase Timing Diagram
Six-byte code for 5V-only software
chip erase
T
WC
Address A15-0
5555
80
5555
2AAA
55
5555
5555
AA
2AAA
55
DQ7-0
CE
AA
10
OE
T
WP
T
BLC
WE
T
WPH
SW0
SW2
SW3
SW5
SW1
SW4
Internal erasing starts
Publication Release Date: February 1998
Revision A3
- 17 -
W29C020
ORDERING INFORMATION
PART NO.
ACCESS
TIME
POWER
STANDBY
PACKAGE
CYCLING
SUPPLY CURRENT VDD CURRENT
(nS)
MAX. (mA)
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
MAX. (mA)
W29C020-70A
W29C020-90A
W29C020-12A
W29C020S-70A
W29C020S-90A
W29C020S-12A
W29C020T-70A
W29C020T-90A
W29C020T-12A
W29C020P-70A
W29C020P-90A
W29C020P-12A
W29C020-70
70
90
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
600 mil DIP
100
100
100
100
100
100
100
100
100
100
100
100
1K
600 mil DIP
120
70
600 mil DIP
450 mil SOP
450 mil SOP
450 mil SOP
Type one TSOP
Type one TSOP
Type one TSOP
32-pin PLCC
32-pin PLCC
32-pin PLCC
600 mil DIP
90
120
70
90
120
70
90
120
70
W29C020-90
90
600 mil DIP
1K
W29C020-12
120
70
600 mil DIP
1K
W29C020S-70
W29C020S-90
W29C020S-12
W29C020T-70
W29C020T-90
W29C020T-12
W29C020P-70
W29C020P-90
W29C020P-12
W29C020-70B
W29C020-90B
W29C020-12B
W29C020S-70B
W29C020S-90B
W29C020S-12B
W29C020T-70B
W29C020T-90B
W29C020T-12B
W29C020P-70B
W29C020P-90B
W29C020P-12B
450 mil SOP
450 mil SOP
450 mil SOP
Type one TSOP
Type one TSOP
Type one TSOP
32-pin PLCC
32-pin PLCC
32-pin PLCC
600 mil DIP
1K
90
1K
120
70
1K
1K
90
1K
120
70
1K
1K
90
1K
120
70
1K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
90
600 mil DIP
120
70
600 mil DIP
450 mil SOP
450 mil SOP
450 mil SOP
Type one TSOP
Type one TSOP
Type one TSOP
32-pin PLCC
32-pin PLCC
32-pin PLCC
90
120
70
90
120
70
90
120
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
- 18 -
W29C020
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in mm
Dimension in inches
Symbol
Min. Nom. Max. Min. Nom. Max.
5.33
0.210
A
A1
0.010
0.150 0.155 0.160 3.81
0.25
3.94
0.46
1.27
0.25
4.06
0.56
1.37
0.36
A
B
B
c
D
E
E
2
0.016 0.018
0.41
1.22
0.022
0.054
0.050
0.048
0.008
1
0.010 0.014 0.20
1.650 1.660
D
17
32
41.91 42.16
15.49
14.10
2.79
0.610
0.555
15.24
13.97
2.54
0.590 0.600
14.99
13.84
2.29
0.545
0.550
1
0.090 0.100 0.110
e 1
L
E1
3.05
0
0.120
0
0.140
15
3.30
0.130
3.56
15
a
17.02
2.16
0.630 0.650 0.670 16.00 16.51
0.085
A
e
S
16
1
Notes:
E
S
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
c
2.Dimension E1 does not include interlead flash.
A
2
A
L
A1
Base Plane
3.Dimensions D & E1 include mold mismatch and
.
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
Seating Plane
5.Controlling dimension: Inches.
6.General appearance spec. should be based on
B
1
e
eA
a
B1
final visual inspection spec.
32-pin SO Wide Body
Dimension in Inches
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.118
Max.
3.00
17
32
e1
0.004
0.101
0.10
A
A
b
1
0.106
0.111
2.57
0.36
0.15
2.69
0.41
2.82
0.51
2
0.014 0.016
0.006 0.008
0.805
0.020
0.012
0.817
0.20
0.31
c
20.75
11.43
1.42
E HE
20.45
D
E
e
11.18
1.12
0.440 0.445
0.044 0.050
0.450
0.056
11.30
1.27
0.556
0.039
0.546 0.556
13.87
0.58
1.19
14.12 14.38
L
H
L
L
E
0.023
0.031
0.79
1.40
0.99
Detail F
0.063
0.036
1
16
0.047 0.055
1.60
0.91
0.10
E
b
S
y
q
0.004
10
10
0
0
Notes:
e1
D
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
c
A
A2
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
4. Controlling dimension: Inches.
.
e
S
y
LE
A 1
5. General appearance spec should be based
on final visual inspection spec.
See Detail F
Seating Plane
Publication Release Date: February 1998
Revision A3
- 19 -
W29C020
Package Dimensions, continued
32-pin PLCC
HE
E
4
1
32
30
Dimension in Inches
Dimension in mm
Symbol
A
Min. Nom. Max.
Min. Nom. Max.
5
29
0.140
3.56
0.020
0.50
A
1
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.115
0.032
0.022
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
2.67
0.66
2.80
0.71
2.93
0.81
A2
b 1
b
c
D
E
0.41
0.56
0.46
0.20
0.35
0.25
D
G
D
H
D
13.89
11.35
1.12
14.05
11.51
1.42
13.97
11.43
1.27
e
12.95
12.45
9.91
13.46
10.92
15.11
12.57
2.41
G
D
10.41
14.99
12.45
2.29
G E
H D
H E
L
y
21
13
14.86
12.32
1.91
0.090
14
c
20
0.10
°
0
°
0
°
10
°
10
q
Notes:
L
A
A
2
1
A
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final
visual inspection sepc.
q
e
b
b
1
Seating Plane
y
E
G
32-pin TSOP
D
H
D
Dimension in Inches
Min. Nom. Max.
Dimension in mm
Symbol
Min.
__
Max.
Nom.
__
__
__
A
1.20
0.15
1.05
0.047
0.006
c
__
__
0.002
0.037
0.05
0.95
A 1
0.041
0.009
1.00
0.20
0.15
0.039
2
A
M
e
0.007 0.008
0.17
0.12
0.23
0.17
b
c
E
0.005 0.006
0.720 0.724
0.007
0.728
0.10(0.004)
18.30 18.40 18.50
D
E
b
0.311 0.315
0.780 0.787
7.90
8.00
8.10
0.319
19.80
__
20.00 20.20
0.795
__
HD
e
__
__
0.020
0.50
0.016 0.020
0.40
__
0.50
0.60
__
0.024
__
L
__
0.031
0.80
__
L
1
A
__
0.000
0.004
5
0.10
5
0.00
1
Y
A2
1
3
3
q
q
L
A1
Y
L1
Note:
Controlling dimension: Millimeters
- 20 -
W29C020
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Apr. 1997
Nov. 1997
Initial Issued
4, 8
9
Correct the address from 3FFF2 to 7FFF2
Correct the boot block from 8K to 16K
Modify page write cycle timing diagram waveform
Delete cycling 100K item
15
1, 18
6
A3
Feb. 1998
Add. pause 10 mS
7
Add. pause 50 mS
8
Correct the time from 10 mS to 10 mS
Add. cycling 100 item
1, 18
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Headquarters
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
TEL: 408-9436666
FAX: 408-5441798
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: February 1998
Revision A3
- 21 -
相关型号：
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