W25X10CLZPIG [WINBOND]
2.5 / 3 / 3.3 V 512K / 1M / 2M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI;型号: | W25X10CLZPIG |
厂家: | WINBOND |
描述: | 2.5 / 3 / 3.3 V 512K / 1M / 2M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL I/O SPI |
文件: | 总51页 (文件大小:1221K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W25X05CL/10CL/20CL
2.5 / 3 / 3.3 V
512K / 1M / 2M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL I/O SPI
Publication Release Date: March 23, 2012
Revision B
- 1 -
W25X05CL/10CL/20CL
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION......................................................................................................4
FEATURES.............................................................................................................................4
PIN CONFIGURATION SOIC 150-MIL, VSOP 150-MIL, TSSOP 173-MIL ...............................5
PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM...............................................5
PIN DESCRIPTION SOIC 150-MIL, VSOP 150-MM AND USON 2X3-MM...............................5
5.1
5.2
5.3
5.4
5.5
5.6
Package Types ...........................................................................................................6
Chip Select (/CS) ........................................................................................................6
Serial Data Input, Output and IOs (DIO, DO, IO0 and IO1)...........................................6
Write Protect (/WP) .....................................................................................................6
HOLD (/HOLD)............................................................................................................6
Serial Clock (CLK).......................................................................................................6
6.
7.
BLOCK DIAGRAM ..................................................................................................................7
FUNCTIONAL DESCRIPTION ................................................................................................8
7.1
SPI OPERATIONS......................................................................................................8
7.1.1 Standard SPI Instructions.................................................................................................8
7.1.2 Dual SPI Instructions........................................................................................................8
7.1.3 Hold Function ...................................................................................................................8
WRITE PROTECTION ................................................................................................9
7.2.1 Write Protect Features......................................................................................................9
7.2
8.
CONTROL AND STATUS REGISTERS................................................................................10
8.1
STATUS REGISTER.................................................................................................10
8.1.1 BUSY..............................................................................................................................10
8.1.2 Write Enable Latch (WEL)..............................................................................................10
8.1.3 Block Protect Bits (BP1, BP0) ........................................................................................10
8.1.4 Top/Bottom Block Protect (TB).......................................................................................10
8.1.5 Reserved Bits.................................................................................................................11
8.1.6 Status Register Protect (SRP)........................................................................................11
8.1.7 Status Register Memory Protection................................................................................12
INSTRUCTIONS .......................................................................................................13
8.2.1 Manufacturer and Device Identification ..........................................................................13
8.2.2 Instruction Set ................................................................................................................14
8.2.3 Write Enable (06h)..........................................................................................................15
8.2.4 Write Enable for Volatile Status Register (50h) ..............................................................15
8.2.5 Write Disable (04h).........................................................................................................16
8.2.6 Read Status Register (05h)............................................................................................16
8.2.7 Write Status Register (01h)............................................................................................17
8.2.8 Read Data (03h).............................................................................................................18
8.2.9 Fast Read (0Bh).............................................................................................................19
8.2.10 Fast Read Dual Output (3Bh).......................................................................................20
8.2.11 Fast Read Dual I/O (BBh).............................................................................................21
8.2.12 Continuous Read Mode Bits (M7-0) .............................................................................23
8.2.13 Continuous Read Mode Reset (FFFFh) .......................................................................23
8.2.14 Page Program (02h).....................................................................................................24
8.2.15 Sector Erase (20h) .......................................................................................................25
8.2
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.16 32KB Block Erase (52h)...............................................................................................26
8.2.17 Block Erase (D8h) ........................................................................................................27
8.2.18 Chip Erase (C7h or 60h)...............................................................................................28
8.2.19 Power-down (B9h)........................................................................................................29
8.2.20 Release Power-down / Device ID (ABh).......................................................................30
8.2.21 Read Manufacturer / Device ID (90h) ...........................................................................32
8.2.22 Read Manufacturer / Device ID Dual I/O (92h).............................................................33
8.2.23 Read Unique ID Number (4Bh) ....................................................................................34
8.2.24 JEDEC ID (9Fh) ...........................................................................................................35
ELECTRICAL CHARACTERISTICS......................................................................................36
9.
9.1
9.2
9.3
9.4
9.5
9.6
Absolute Maximum Rating.........................................................................................36
Operating Ranges.....................................................................................................36
Power-up Timing and Write Inhibit Threshold.............................................................37
DC Electrical Characteristics .....................................................................................38
AC Measurement Conditions.....................................................................................39
AC Electrical Characteristics......................................................................................40
AC Electrical Characteristics (cont’d).....................................................................................41
9.7
9.8
9.9
Serial Output Timing..................................................................................................42
Serial Input Timing ....................................................................................................42
HOLD Timing ............................................................................................................42
9.10 WP Timing ................................................................................................................42
PACKAGE SPECIFICATION.................................................................................................43
10.1 8-Pin SOIC 150-mil (Package Code SN)....................................................................43
10.2 8-Pin VSOP8 150-mil (Package Code SV).................................................................44
10.3 8-Pin TSSOP8 173-mil (Package Code SD) ..............................................................45
10.4 8-Contact 6x5mm WSON (Package Code ZP)...........................................................46
8-Pad WSON 6x5mm Cont’d.................................................................................................47
10.5 8-Pad USON 2x3-mm (Package Code UX)................................................................48
ORDERING INFORMATION .................................................................................................49
11.1 Valid Part Numbers and Top Side Marking ................................................................50
REVISION HISTORY............................................................................................................51
10.
11.
12.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
1. GENERAL DESCRIPTION
The W25X05CL (512K-bit), W25X10CL (1M-bit) and W25X20CL (2M-bit) Serial Flash memories
provide a storage solution for systems with limited space, pins and power. The 25X series offers
flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code
download applications as well as storing voice, text and data. The devices operate on a single 2.3V
to 3.6V power supply with current consumption as low as 1mA active and 1µA for power-down. All
devices are offered in space-saving packages.
The W25X05CL/10CL/20CL arrays are organized into 256/512/1,024 programmable pages of 256-
bytes each. Up to 256 bytes can be programmed at a time. The W25X05CL/10CL/20CL have
16/32/64 erasable sectors, 2/4/8 erasable 32KB blocks and 1/2/4 erasable 64KB blocks respectively.
The small 4KB sectors allow for greater flexibility in applications that require data and parameter
storage. (See figure 2.)
The W25X05CL/10CL/20CL support the standard Serial Peripheral Interface (SPI), and a high
performance dual output as well as Dual I/O SPI: Serial Clock, Chip Select, Serial Data DIO (I/O0),
DO (I/O1). SPI clock frequencies up to 104MHz are supported allowing equivalent clock rates of
208MHz when using the Fast Read Dual Output instruction. These transfer rates are comparable to
those of 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 16-clocks of instruction-overhead to read a 24-bit address, allowing
true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control
features, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of Serial Flash Memories
Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
– W25X05CL: 512K-bit/64K-byte (65,536)
– W25X10CL: 1M-bit/128K-byte (131,072)
– W25X20CL: 2M-bit/256K-byte (262,144)
– 256-bytes per programmable page
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4/32/64-kbytes)
– Page program up to 256 bytes <1ms
– More than 100,000 erase/write cycles
– More than 20-year data retention
– Uniform erasable 4KB, 32KB & 64KB regions.
SPI with Single / Dual Outputs / I/O
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
Data Transfer up to 208M-bits / second
– Clock operation to 104MHz
Low Power, Wide Temperature Range
– Single 2.3V to 3.6V supply
– 208MHz equivalent Dual I/O SPI
– Auto-increment Read capability
– 1mA active current, <1µA Power-down(typ.)
– -40° to +85°C operating range
Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read
Space Efficient Packaging
– 8-pin SOIC / VSOP 150-mil
– 8-pin TSSOP 173-mil
– As few as 16 clocks to address memory
– Allows true XIP (execute in place) operation
– 8-pad WSON 6x5-mm
– 8-pad USON 2x3-mm
– Contact Winbond for KGD and other options
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
3. PIN CONFIGURATION SOIC 150-MIL, VSOP 150-MIL, TSSOP 173-MIL
Figure 1a. W25X05CL/10CL/20CL Pin Assignments, 8-pin SOIC 150-mil, VSOP 150-mil and TSSOP8 173-mil
(Package Code SN, SV and SD)
4. PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM
Figure 1b. W25X05CL/10CL/20CL Pad Assignments, 8-pad WSON 6x8-MM and USON 2x3-MM (Package Code ZP & UX)
5. PIN DESCRIPTION SOIC\VSOP 150-MIL, WSON 6X5-MM AND USON 2X3-MM
PIN NO.
PIN NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
/CS
DO (IO1)
/WP
I
I/O
I
Chip Select Input
Data Input / Output(1)
Write Protect Input
Ground
GND
DIO (IO0)
CLK
I/O
Data Input / Output(1)
Serial Clock Input
Hold Input
I
I
/HOLD
VCC
Power Supply
Note:
1 IO0 and IO1 are used for Standard and Dual SPI instructions
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
5.1
Package Types
W25X05CL/10CL/20CL are offered in 8-pin plastic 150-mil width SOIC (package code SN), 150-mil
width VSOP8 (package code SV) and 173-mil width TSSOP (package code SD). 8-pad 6x5-mm
WSON (package code ZP) and 2x3-mm USON (package code UX). Refer to see figures 1a and 1b,
respectively.
5.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase,
program or write status register cycle is in progress. When /CS is brought low the device will be
selected, power consumption will increase to active levels and instructions can be written to and data
read from the device. After power-up, /CS must transition from high to low before a new instruction will
be accepted. The /CS input must track the VCC supply level at power-up (see “Power-up Timing and
Write inhibit threshold” and Figure 26). If needed, a pull-up resister on /CS can be used to accomplish
this.
5.3 Serial Data Input, Output and IOs (DIO, DO, IO0 and IO1)
The W25X05CL/10CL/20CL support standard SPI and Dual SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output)
to read data or status from the device on the falling edge of CLK.
Dual SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the
device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
5.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (TB, BP1 and BP0) bits and Status Register
Protect (SRP) bit, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
5.5 HOLD (/HOLD)
The Hold (/HOLD) pin allows the device to be paused while it is actively selected. When /HOLD is
brought low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK
pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The
/HOLD function can be useful when multiple devices are sharing the same SPI signals.
5.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
6. BLOCK DIAGRAM
Figure 2. W25X05CL/10CL/20CL Serial Flash Memory Block Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
7.
FUNCTIONAL DESCRIPTION
7.1 SPI OPERATIONS
7.1.1 Standard SPI Instructions
The W25X05CL/10CL/20CL are accessed through an SPI compatible bus consisting of four signals:
Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on
the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling
edge CLK.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the
falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising
edges of /CS.
7.1.2 Dual SPI Instructions
The W25X05CL/10CL/20CL support Dual SPI operation when using the “Fast Read Dual Output (3Bh)”
and “Fast Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from
the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read
instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for
executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions,
the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
7.1.3 Hold Function
The /HOLD signal allows the W25X05CL/10CL/20CL operation to be paused while it is actively
selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock
signals are shared with other devices. For example, consider if the page buffer was only partially
written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save
the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept
active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the
device.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
7.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern, the
W25X05CL/10CL/20CL provide several means to protect data from inadvertent writes.
7.2.1 Write Protect Features
Device resets when VCC is below threshold.
Time delay write disable after Power-up.
Write enable/disable instructions.
Automatic write disable after program and erase.
Software and Hardware (/WP pin) write protection using Status Register.
Write Protection using Power-down instruction.
Upon power-up or at power-down, the W25X05CL/10CL/20CL will maintain a reset condition while
VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 26).
While reset, all operations are disabled and no instructions are recognized. During power-up and after
the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a
time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip
Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the
VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed, a
pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared
to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (TB, BP1 and BP0) bits. These allow a portion
small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under
hardware control. See Status Register for further information. Additionally, the Power-down instruction
offers an extra level of write protection as all instructions are ignored except for the Release Power-
down instruction.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.
CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the device write protection features.
8.1 STATUS REGISTER
8.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During
this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
8.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A
write disable state occurs upon power-up or after any of the following instructions finished: Write
Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
8.1.3 Block Protect Bits (BP1, BP0)
The Block Protect Bits (BP1 and BP0) are non-volatile read/write bits in the status register (S3 and S2)
that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected. The Block Protect
bits cannot be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP)
pin is low.
8.1.4 Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP1, BP0) protect from the Top (TB=0) or
the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit is
non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write Status
Register Instruction provided that the Write Enable instruction has been issued. The TB bit cannot be
written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.1.5 Reserved Bits
Status register bit location S6 and S4 are reserved for future use. Current devices will read 0 for this
bit location. It is recommended to mask out the reserved bit when testing the Status Register. Doing
this will ensure compatibility with future devices.
8.1.6 Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be
used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP
bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP
pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the
/WP pin is high the Write Status Register instruction is allowed.
Status
Register
SRP
/WP
Description
Software
Protection
/WP pin has no control, The Status register can be written to
after a Write Enable instruction WEL = 1. [Factory Default]
0
1
1
X
0
1
Hardware
Protected
When /WP pin is low the Status Register locked and can’t be
written to.
Hardware
When /WP pin is high the status register is unlocked and can
Unprotected be written to after a Write Enable instruction WEL = 1.
S7
S6
(R)
S5
TB
S4
(R)
S3
S2
S1
S0
STATUS REGISTER PROTECT
(Non-volatile)
RESERVED
TOP/BOTTOM PROTECT
(Non-volatile)
BLOCK PROTECT BITS
(Non-volatile)
WRITE ENABLE LATCH
(volatile)
ERASE/WRITE IN PROGRESS
(volatile)
Figure 3. Status Register Bit Locations
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.1.7 Status Register Memory Protection
STATUS REGISTER(1)
W25X20CL (2M-BIT) MEMORY PROTECTION
TB
x
0
0
1
BP1
0
0
1
0
BP0
0
1
0
1
BLOCK(S)
NONE
3
2 and 3
0
ADDRESSES
NONE
DENSITY
NONE
64KB
128KB
64KB
PORTION
NONE
030000h - 03FFFFh
020000h - 03FFFFh
000000h - 00FFFFh
000000h - 01FFFFh
000000h - 03FFFFh
Upper 1/4
Upper 1/2
Lower 1/4
Lower 1/2
ALL
1
x
1
1
0
1
0 and 1
0 thru 3
128KB
256KB
STATUS REGISTER(1)
W25X10CL (1M-BIT) MEMORY PROTECTION
TB
x
0
1
x
BP1
0
0
0
1
BP0
0
1
1
x
BLOCK(S)
ADDRESSES
NONE
010000h - 01FFFFh
000000h - 00FFFFh
000000h - 01FFFFh
DENSITY
NONE
64KB
64KB
128KB
PORTION
NONE
Upper 1/2
Lower 1/2
ALL
NONE
1
0
0 and 1
STATUS REGISTER(1)
W25X05CL (512K-BIT) MEMORY PROTECTION
TB
BP1
0
0
1
1
BP0
0
1
0
1
BLOCK(S)
ADDRESSES
NONE
000000h - 00FFFFh
000000h - 00FFFFh
000000h - 00FFFFh
DENSITY
NONE
64KB
64KB
64KB
PORTION
NONE
ALL
x
x
x
NONE
0
0
0
ALL
ALL
x
Note:
1. x = don’t care
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2 INSTRUCTIONS
The instruction set of the W25X05CL/10CL/20CL consists of twenty basic instructions that are fully
controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DIO input provides the instruction
code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 25. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
8.2.1 Manufacturer and Device Identification
MANUFACTURER ID
(M7-M0)
Winbond Serial Flash
EFh
(ID15-ID0)
9Fh
Device ID
(ID7-ID0)
ABh, 90h, 92h
05h
Instruction
W25X05CL
W25X10CL
W25X20CL
3010h
3011h
3012h
10h
11h
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.2 Instruction Set (1)
INSTRUCTION
NAME
BYTE 1 BYTE 2
(CODE)
BYTE 3
BYTE 4
BYTE 5
BYTE 6
N-BYTES
Write Enable
06h
Write Enable for
Volatile Status
Register
50h
Write Disable
04h
05h
01h
03h
(2)
Read Status Register
Write Status Register
Read Data
(S7–S0)(1)
(S7–S0)
A23–A16
A15–A8
A15–A8
A7–A0
A7–A0
(D7–D0)
(Next byte)
continuous
(Next Byte)
continuous
(one byte per
4 clocks,
Fast Read
0Bh
A23–A16
dummy
(D7–D0)
Fast Read Dual
Output
3Bh
A23–A16
A15–A8
A7–A0
dummy
(D7-D0, …)(5)
continuous)
A7-A0, M7-
M0(6)
Fast Read Dual I/O
Page Program
BBh
02h
A23-A8(6)
(D7-D0, …)(5)
A7–A0
Up to 256
bytes
A23–A16
A15–A8
(D7–D0)
(Next byte)
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Chip Erase
20h
52h
A23–A16
A23–A16
A23–A16
A15–A8
A15–A8
A15–A8
A7–A0
A7–A0
A7–A0
D8h
C7h/60h
B9h
Power-down
Release Power-down
/ Device ID
ABh
90h
dummy
dummy
dummy
dummy
dummy
00h
(ID7-ID0)(4)
(M7-M0)
Manufacturer/
Device ID (3)
(ID7-ID0)
Manufacturer/Device
ID by Dual I/O
A7-A0,
M[7:0]
(MF[7:0],
ID[7:0])
92h
A23-A8
(ID15-ID8)
Memory
Type
(M7-M0)
(ID7-ID0)
Capacity
JEDEC ID
9Fh
4Bh
Manufacturer
Read Unique ID
dummy
dummy
dummy
dummy
(ID63-ID0)
Notes:
1
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from
the device on the DO pin.
2
3
4
5
The Status Register contents will repeat continuously until /CS terminates the instruction.
See Manufacturer and Device Identification table for Device ID information.
The Device ID will repeat continuously until /CS terminates the instruction.
Dual Output and Dual I/O data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
6
Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.3 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase
and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,
shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then
driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (06h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 4. Write Enable Instruction Sequence Diagram
8.2.4 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits.
This gives more flexibility to change the system configuration and memory protection schemes quickly
without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status
Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)
instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable
Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status
Register bit values.
Instruction (50h)
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.5 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”
into the DIO pin and then driving /CS high. WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
instructions. Write Disable instruction can also be used to invalidate the Write Enable for Volatile
Status Register instruction
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (04h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 6. Write Disable Instruction Sequence Diagram
8.2.6 Read Status Register (05h)
The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge of
CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and
include the BUSY, WEL, BP1, BP0, TB and SRP bits (see description of the Status Register earlier in
this datasheet).
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 7. The instruction is completed by driving /CS high.
Figure 7. Read Status Register Instruction Sequence Diagram
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.7 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable
instruction must previously have been executed for the device to accept the Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by
driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as
illustrated in figure 8. The Status Register bits are shown in figure 3 and described earlier in this
datasheet.
Only non-volatile Status Register bits SRP, TB, BP1 and BP0 (bits 7, 5, 3 and 2) can be written to. All
other Status Register bit locations are read-only and will not be affected by the Write Status Register
instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a
0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (TB, BP1 and BP0) to be set for
protecting all, a portion, or none of the memory from erase and program instructions. Protected areas
become read-only (see Status Register Memory Protection table). The Write Status Register
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is
high the Write Status Register instruction is allowed.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Figure 8. Write Status Register Instruction Sequence Diagram
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.8 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory.
The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h”
followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.
The address is automatically incremented to the next higher address after each byte of data is shifted
out allowing for a continuous stream of data. This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in figure 9. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of
fR (see AC Electrical Characteristics).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (03h)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
Data Out 1
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
= MSB
*
*
Figure 9. Read Data Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.9 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks the
data value on the DIO pin is a “don’t care”.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (0Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
DI
(IO0)
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 10. Fast Read Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.10 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins, IO0 and IO1. This allows data to be transferred from the
W25X05CL/10CL/20CL at twice the rate of standard SPI devices. The Fast Read Dual Output
instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications
that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the
first data out clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (3Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
IO0 switches from
Dummy Clocks
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
High Impedance
DO
(IO1)
7
5
3
1
7
7
7
Data Out 1
Data Out 2
Data Out 3
Data Out 4
*
*
*
*
Figure 11. Fast Read Dual Output Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.11 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for
code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after
/CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset
(M7-0) before issuing normal instructions (See 9.2.12 for detail descriptions).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10)
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.12 Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with the “Fast Read Dual I/O” instruction to
provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus
allow true XIP (execute in place) to be performed on serial flash devices.
M7-0 need to be set by the Dual I/O Read instruction. M5-4 are used to control whether the 8-bit SPI
instruction code BBh is needed or not for the next command. When M5-4 = (1,0), the next command
will be treated same as the current Dual I/O Read command without needing the 8-bit instruction code;
when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can be
accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.
8.2.13 Continuous Read Mode Reset (FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in figure 13.
Mode Bit Reset
for Dual I/O
/CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
Mode 3
Mode 0
CLK
IO0
FFFFh
Don’t Care
IO1
Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O
Since W25X05CL/10CL/20CL does not have a hardware Reset pin, so if the controller resets while
W25X05CL/10CL/20CL are set to Continuous Mode Read, the W25X05CL/10CL/20CL will
not recognize any initial standard SPI instructions from the controller. To address this possibility, it is
recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a
system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard
SPI instructions to be recognized.
To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh”.
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.14 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed
at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL = 1). The instruction is
initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address
(A23-A0) and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire
length of the instruction while data is being sent to the device.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less
than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the
same page. One condition to perform a partial page program is that the number of clocks cannot
exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will
wrap to the beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (BP1, and BP0) bits (see Status Register Memory
Protection table).
Figure 14. Page Program Instruction Sequence Diagram
Publication Release Date: March 23, 2012
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Revision B
W25X05CL/10CL/20CL
8.2.15 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state
of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2).
The Sector Erase instruction sequence is shown in figure 15.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector
Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,
BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (20h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 15. Sector Erase Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.16
32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2).
The Block Erase instruction sequence is shown in figure 16.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and
BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (52h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 16. 32KB Block Erase Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.17 Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block
Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS
pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2).
The Block Erase instruction sequence is shown in figure 17.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and
BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (D8h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 17. Block Erase Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.18 Chip Erase (C7h or 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 18.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (TB, BP1 and BP0) bits (see Status Register Memory
Protection table).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (C7h/60h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 18. Chip Erase Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
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W25X05CL/10CL/20CL
8.2.19 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in figure 19.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-
down instruction will not be executed. After /CS is driven high, the power-down state will entered
within the time duration of tDP (See AC Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction makes the Power
Down state a useful condition for securing maximum write protection. The device always powers-up in
the normal operation with the standby current of ICC1.
/CS
tDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (B9h)
DI
(IO0)
Stand-by current
Power-down current
Figure 19. Deep Power-down Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
- 29 -
W25X05CL/10CL/20CL
8.2.20 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, obtain the devices electronic identification (ID) number
or do both.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in figure 20. Release from power-
down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 20. The Device ID values for the W25X05CL/10CL/20CL are listed in Manufacturer
and Device Identification table. The Device ID can be read continuously. The instruction is completed
by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction
is the same as previously described, and shown in figure 21, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the
device will resume normal operation and other instructions will be accepted.
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write
cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on
the current cycle
/CS
tRES1
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (ABh)
DI
(IO0)
Power-down current
Stand-by current
Figure 20. Release Power-down Instruction Sequence
Publication Release Date: March 23, 2012
Revision B
- 30 -
W25X05CL/10CL/20CL
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
tRES2
CLK
Instruction (ABh)
3 Dummy Bytes
DI
(IO0)
23 22
2
1
0
Device ID
*
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
*
= MSB
Power-down current
Stand-by current
*
Figure 21. Release Power-down / Device ID Instruction Sequence Diagram
Publication Release Date: March 23, 2012
Revision B
- 31 -
W25X05CL/10CL/20CL
8.2.21 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/
Device ID instruction that provides both JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in figure 22. The Device ID values for the W25X05CL/10CL/20CL are listed in Manufacturer
and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be
read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (90h)
Address (000000h)
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Mode 3
Mode 0
CLK
DI
(IO0)
0
DO
(IO1)
7
6
5
4
3
2
1
0
Manufacturer ID (EFh)
Device ID
*
Figure 22. Read Manufacturer / Device ID Diagram
Publication Release Date: March 23, 2012
Revision B
- 32 -
W25X05CL/10CL/20CL
8.2.22 Read Manufacturer / Device ID Dual I/O (92h)
The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by
a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input
the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the
Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB)
first as shown in figure 28. The Device ID values for the W25X05CL/10CL/20CL are listed in
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device
ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can
be read continuously, alternating from one to the other. The instruction is completed by driving /CS
high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
A23-16
A15-8
A7-0 (00h)
M7-0
Instruction (92h)
High Impedance
DI
(IO0)
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
DO
(IO1)
7
5
3
7
5
3
7
5
3
7
5
3
= MSB
*
*
*
*
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
DO
(IO1)
7
3
1
7
7
7
MFR ID
(repeat)
Device ID
(repeat)
*
*
*
*
MFR ID
Device ID
Figure 23. Read Manufacturer / Device ID Dual I/O Diagram
“Continuous Read Mode” bits M7-0 must be set to FXh to be compatible with Fast Read Dual I/O instruction.
Note:
1.
Publication Release Date: March 23, 2012
Revision B
- 33 -
W25X05CL/10CL/20CL
8.2.23 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique
to each W25X05CL/10CL/20CL device. The ID number can be used in conjunction with user software
methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by
driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy
clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 24.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (4Bh)
Dummy Byte 1
Dummy Byte 2
DI
(IO0)
High Impedance
DO
(IO1)
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Mode 3
Mode 0
CLK
Dummy Byte 3
Dummy Byte 4
DI
(IO0)
High Impedance
DO
(IO1)
63 62 61
2
1
0
= MSB
64-bit Unique Serial Number
*
*
Figure 24. Read Unique ID Number Instruction Sequence
Publication Release Date: March 23, 2012
Revision B
- 34 -
W25X05CL/10CL/20CL
8.2.24 JEDEC ID (9Fh)
For compatibility reasons, the W25X05CL/10CL/20CL provide several instructions to electronically
determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC
standard for SPI compatible serial memories that was adopted in 2003.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The
JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type
(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant
bit (MSB) first as shown in figure 25. For memory type and capacity values refer to Manufacturer and
Device Identification table.
Figure 25. Read JEDEC ID
Publication Release Date: March 23, 2012
- 35 -
Revision B
W25X05CL/10CL/20CL
9. ELECTRICAL CHARACTERISTICS
(1)
9.1 Absolute Maximum Rating
PARAMETERS
SYMBOL
VCC
CONDITIONS
RANGE
UNIT
V
Supply Voltage
–0.6 to +4.6
–0.6 to VCC +0.4
VIO
Voltage Applied to Any Pin
Relative to Ground
V
<20nS Transient
Relative to Ground
VIOT
Transient Voltage on any Pin
–2.0V to VCC+2.0V
V
TSTG
TLEAD
VESD
°C
°C
V
Storage Temperature
Lead Temperature
–65 to +150
See Note (2)
Electrostatic Discharge Voltage
Human Body Model(3) –2000 to +2000
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings
may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive
on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
SPEC
PARAMETER
SYMBOL CONDITIONS
UNIT
MIN
MAX
FR
=
80MHz, fR = 33MHz
2.3
2.7
2.7
3.6
VCC
TA
Supply Voltage
V
FR = 104MHz, fR = 50MHz
Ambient Temperature,
Operating
Industrial
–40
+85
°C
Publication Release Date: March 23, 2012
Revision B
- 36 -
W25X05CL/10CL/20CL
9.3 Power-up Timing and Write Inhibit Threshold
SPEC
UNIT
PARAMETER
SYMBOL
MIN
10
1
MAX
tVSL(1)
tPUW(1)
VWI(1)
VCC (min) to /CS Low
µs
ms
V
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
10
2
1
Note:
1. These parameters are characterized only.
Figure 26. Power-up Timing and Voltage Levels
Publication Release Date: March 23, 2012
Revision B
- 37 -
W25X05CL/10CL/20CL
9.4 DC Electrical Characteristics
SPEC
UNIT
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
CIN(1)
Cout(1)
ILI
Input Capacitance
Output Capacitance
Input Leakage
VIN = 0V(2)
6
pF
pF
µA
µA
VOUT = 0V(2)
8
±2
±2
ILO
I/O Leakage
/CS = VCC,
VIN = GND or VCC
ICC1
ICC2
ICC3
ICC3
ICC3
ICC3
Standby Current
10
1
50
5
µA
µA
/CS = VCC,
VIN = GND or VCC
Power-down Current
Current Read Data /
Dual Output 1MHz(2)
C = 0.1 VCC / 0.9 VCC
DO = Open
1/3
4/5
5/6
6/7
4/8
mA
mA
mA
mA
Current Read Data /
Dual Output 33MHz(2)
C = 0.1 VCC / 0.9 VCC
DO = Open
8/10
10/12
12/14
Current Read Data /
Dual Output 80MHz(2)
C = 0.1 VCC / 0.9 VCC
DO = Open
Current Read Data /
C = 0.1 VCC / 0.9 VCC
DO = Open
Dual Output 104MHz(2)
Current Write Status
Register
ICC4
ICC5
ICC6
/CS = VCC
/CS = VCC
/CS = VCC
/CS = VCC
8
12
15
15
mA
mA
mA
Current Page Program
10
10
10
Current Sector/Block
Erase
ICC7
VIL
Current Chip Erase
Input Low Voltage
Input High Voltage
Output Low Voltage
15
mA
V
–0.5
VCCx0.3
VIH
VCCx0.7
V
VOL
VOH
IOL = 100 µA
0.4
V
Output High Voltage
IOH = –100 µA
VCC–0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC=3.0V.
2. Checker Board Pattern.
Publication Release Date: March 23, 2012
Revision B
- 38 -
W25X05CL/10CL/20CL
9.5 AC Measurement Conditions
SPEC
UNIT
PARAMETER
SYMBOL
MIN
MAX
CL
TR, TF
VIN
Load Capacitance
30
pF
ns
V
Input Rise and Fall Times
Input Pulse Voltages
5
0.1 VCC to 0.9 VCC
0.3 VCC to 0.7 VCC
0.5 VCC to 0.5 VCC
IN
Input Timing Reference Voltages
Output Timing Reference Voltages
Note:
V
OUT
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Input Levels
0.9 VCC
Input and Output Timing
Reference Levels
0.5 VCC
0.1 VCC
Figure 27. AC Measurement I/O Waveform
Publication Release Date: March 23, 2012
Revision B
- 39 -
W25X05CL/10CL/20CL
9.6 AC Electrical Characteristics
SPEC
DESCRIPTION
SYMBOL
ALT
fc
UNIT
MIN
TYP
MAX
Clock frequency for all instructions,
except Read Data (03h)
FR
D.C.
104
MHz
2.7V-3.6V VCC & Industrial Temperature
Clock frequency for all instructions,
except Read Data (03h)
FR
fc
D.C.
D.C.
80
MHz
MHz
2.3V-2.7V VCC & Industrial Temperature
Clock freq. Read Data instruction 03h
2.7V-3.6V VCC & Industrial Temperature
fR
50
33
Clock freq. Read Data instruction 03h
2.3V-2.7V VCC & Industrial Temperature
fR
D.C.
4
MHz
ns
tCLH,
Clock High, Low Time, for Fast Read (0Bh, 3Bh) /
other instructions except Read Data (03h)
(1)
tCLL
tCRLH,
tCRLL
Clock High, Low Time for Read Data (03h)
instruction
6
ns
(1)
(2)
tCLCH
Clock Rise Time peak to peak
Clock Fall Time peak to peak
/CS Active Setup Time relative to CLK
/CS Not Active Hold Time relative to CLK
Data In Setup Time
0.1
0.1
5
V/ns
V/ns
ns
(2)
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL1
tCSS
5
ns
tDSU
tDH
2
ns
Data In Hold Time
5
ns
/CS Active Hold Time relative to CLK
/CS Not Active Setup Time relative to CLK
5
ns
5
ns
/CS Deselect Time (for Array Read Array
Read)
tCSH
tCSH
50
ns
tSHSL2
/CS Deselect Time (for Erase/Program Read
SR) Volatile Status Register Write Time
100
50
ns
(2)
tSHQZ
Output Disable Time
tDIS
tV1
tV2
7
8
8
ns
ns
ns
tCLQV1
tCLQV2
Clock Low to Output Valid
Clock Low to Output Valid (for Read ID instructions)
Continued – next page
Publication Release Date: March 23, 2012
Revision B
- 40 -
W25X05CL/10CL/20CL
AC Electrical Characteristics (cont’d)
SPEC
DESCRIPTION
SYMBOL ALT
UNIT
MIN
0
TYP
MAX
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
Output Hold Time
tHO
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
/HOLD Active Setup Time relative to CLK
/HOLD Active Hold Time relative to CLK
/HOLD Not Active Setup Time relative to CLK
/HOLD Not Active Hold Time relative to CLK
/HOLD to Output Low-Z
5
5
5
5
(2)
tHHQX
tLZ
7
(2)
tHLQZ
tWHSL
tSHWL
/HOLD to Output High-Z
tHZ
12
(3)
(3)
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Power-down Mode
20
100
(2)
tDP
3
3
tRES1(2)
tRES2(2)
/CS High to Standby Mode without Electronic
Signature Read
/CS High to Standby Mode with Electronic
Signature Read
1.8
µs
tW
tBP1
tBP2
tPP
tSE
Write Status Register Time
Byte Program Time (First Byte) (4)
Additional Byte Program Time (After First Byte) (4)
Page Program Time
10
15
15
30
ms
µs
µs
ms
ms
ms
ms
s
2.5
0.4
30
5
0.8
300
800
1,000
2
Sector Erase Time (4KB)
tBE
Block Erase Time (32KB)
120
150
0.5
1
tBE
Block Erase Time (64KB)
2
Chip Erase Time W25X20CL
tCE
tCE
Chip Erase Time W25X10CL & W25X05CL
0.25
1
s
Notes:
1.
2.
3.
4.
Clock high + Clock low must be less than or equal to 1/fC.
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction when SRP is set to 1.
For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number
of bytes programmed.
Publication Release Date: March 23, 2012
- 41 -
Revision B
W25X05CL/10CL/20CL
9.7 Serial Output Timing
/CS
tCLH
CLK
tCLQV
tCLQX
tCLQV
tCLL
tSHQZ
tCLQX
IO
output
MSB OUT
LSB OUT
9.8 Serial Input Timing
/CS
tSHSL
tSHCH
tCHSL
tSLCH
tCHSH
CLK
tDVCH
tCHDX
tCLCH
tCHCL
IO
input
MSB IN
LSB IN
9.9 /HOLD Timing
/CS
tHLCH
tCHHL
tHHCH
CLK
tCHHH
/HOLD
tHLQZ
tHHQX
IO
output
IO
input
9.10 /WP Timing
/CS
tWHSL
/WP
tSHWL
CLK
IO
input
Write Status Register is allowed
Write Status Register is not allowed
Publication Release Date: March 23, 2012
Revision B
- 42 -
W25X05CL/10CL/20CL
10. PACKAGE SPECIFICATION
10.1 8-Pin SOIC 150-mil (Package Code SN)
c
8
5
E
H
E
L
1
4
θ
0.25
D
A
Y
e
SEATING PLANE
GAUGE PLANE
A1
b
MILLIMETERS
INCHES
SYMBOL
Min
Max
Min
Max
A
A1
b
1.35
0.10
0.33
0.19
3.80
4.80
1.75
0.25
0.51
0.25
4.00
5.00
0.053
0.004
0.013
0.008
0.150
0.188
0.069
0.010
0.020
0.010
0.157
0.196
c
E(3)
D(3)
e(2)
1.27 BSC
0.050 BSC
5.80
-
0.40
6.20
0.10
1.27
0.228
-
0.016
0.244
0.004
0.050
H
E
Y(4)
L
∘
0°
10°
0°
10°
Notes:
1. Controlling dimensions: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
Publication Release Date: March 23, 2012
- 43 -
Revision B
W25X05CL/10CL/20CL
10.2 8-Pin VSOP8 150-mil (Package Code SV)
MILLIMETER
SYMBOL
INCHES
MIN
TYP.
MAX
1
MIN
―
TYP.
―
MAX
0.039
0.006
0.033
0.0083
0.020
A
―
―
0.1
A1
0.05
0.75
0.19
0.33
0.15
0.85
0.21
0.51
0.002
0.030
0.0075
0.013
0.004
0.031
0.0079
―
A2
0.8
Q
0.2
b
―
c
0.125 BSC
4.9
0.005 BSC
0.193
0.236
0.154
0.050 BSC
0.0280
―
D
4.8
5.8
3.8
5
6.2
4
0.189
0.228
0.150
0.197
0.244
0.157
E
6
E1
3.9
e
L
1.27BSC
0.71
―
0.4
1.27
0.016
0.050
∘
0°
10°
0°
10°
Publication Release Date: March 23, 2012
Revision B
- 44 -
W25X05CL/10CL/20CL
10.3 8-Pin TSSOP8 173-mil (Package Code SD)
MILLIMETER
SYMBOL
INCHES
MIN
TYP.
MAX
1.20
0.15
1.05
3.10
MIN
―
TYP.
―
MAX
0.047
0.006
0.041
0.122
A
A1
A2
D
―
―
0.05
0.80
2.90
―
0.002
0.030
0.114
―
1.00
3.00
6.40 BSC
4.40
0.60
―
0.040
0.118
0.252 BSC
0.173
0.0236
―
E
E1
L
4.30
0.45
0°
4.50
0.75
8°
0.169
0.0177
0°
0.177
0.295
8°
∘
b
0.19
0.09
―
0.30
0.20
0.007
0.003
―
0.012
0.008
c
―
―
e
0.65 BSC
1.00 REF
0.026 BSC
0.039 REF
L1
Publication Release Date: March 23, 2012
Revision B
- 45 -
W25X05CL/10CL/20CL
10.4 8-Contact 6x5mm WSON (Package Code ZP)
MILLIMETERS
SYMBOL
INCHES
MIN
0.70
0.00
TYP.
0.75
0.02
MAX
0.80
0.05
MIN
TYP.
0.0295
0.0007
MAX
0.0314
0.0019
A
A1
b
0.0275
0.0000
0.35
―
0.40
0.20 REF.
6.00
0.48
―
0.0137
―
0.0157
0.0078 REF.
0.2362
0.0188
―
C
D
5.90
3.35
4.90
4.25
6.10
3.45
5.10
4.35
0.2322
0.1318
0.1929
0.1673
0.2401
0.1358
0.2007
0.1712
D2
E
3.40
0.1338
5.00
0.1968
4.30
0.1692
E2
E(2)
1.27 BSC
0.0500 BSC
L
y
0.55
0.00
0.60
0.65
0.75
0.0216
0.0000
0.0236
0.0255
0.0029
―
―
Publication Release Date: March 23, 2012
Revision B
- 46 -
W25X05CL/10CL/20CL
8-Pad WSON 6x5mm Cont’d.
MILLIMETERS
TYP.
INCHES
SYMBOL
MIN
MAX
MIN
TYP.
MAX
SOLDER PATTERN
M
N
P
―
―
―
―
―
3.40
4.30
6.00
0.50
0.75
―
―
―
―
―
―
―
―
―
―
0.1338
0.1692
0.2360
0.0196
0.0255
―
―
―
―
―
Q
R
Notes:
1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
Publication Release Date: March 23, 2012
- 47 -
Revision B
W25X05CL/10CL/20CL
10.5 8-Pad USON 2x3-mm (Package Code UX)
A
PIN
1
L1
A1
e
b
D2
D
L3
E
L
C
E
y
Note: Exposed pad dimension D2 & E2 may be different by die size.
MILLIMETER
INCHES
SYMBOL
MIN
0.50
0.00
0.20
―
TYP.
0.55
0.02
0.25
0.15 REF
2.00
1.60
3.00
0.20
0.50
0.45
0.10
0.35
―
MAX
0.60
0.05
0.30
―
MIN
0.020
0.000
0.008
―
TYP.
0.022
0.001
0.010
MAX
0.024
0.002
0.012
―
A
A1
b
C
0.006 REF
0.079
0.063
0.118
0.008
0.020
0.018
0.004
0.014
―
D
1.90
1.55
2.90
0.15
―
2.10
1.65
3.10
0.25
―
0.075
0.061
0.114
0.006
―
0.083
0.065
0.122
0.010
―
D2
E
E2
e
L
0.40
―
0.50
―
0.016
―
0.020
―
L1
L3
y
0.30
0.00
0.40
0.075
0.012
0.000
0.016
0.003
Publication Release Date: March 23, 2012
Revision B
- 48 -
W25X05CL/10CL/20CL
11. ORDERING INFORMATION(1)
W 25X xxC L xx(2)
W
=
Winbond
25X
=
SpiFlash Serial Flash Memory with 4KB sectors, Dual SPI
20C
10C
05C
=
=
=
2M-bit
1M-bit
512K-bit
L
=
2.3V to 3.6V
SN
ZP
=
8-pin SOIC 150-mil
SV
UX
=
8-pin VSOP 150-mil
8-pad USON 2x3-mm
SD
=
8-pin TSSOP 173-mil
=
8-pad WSON 6x5-mm
=
I
=
Industrial (-40°C to +85°C)
G
=
Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
Notes:
1a. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel
(shape T) or Tray (shape S), when placing orders.
1b. The “W” prefix is not included on the part marking.
2. Only the 2nd letter is used for the part marking, package type ZP is not used for the part marking.
Publication Release Date: March 23, 2012
- 49 -
Revision B
W25X05CL/10CL/20CL
11.1 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25X05CL/10CL/20CL SpiFlash
Memories. Please contact Winbond for specific availability by density and package type. Winbond
SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the
Top Side Marking on all packages uses an abbreviated number less than 10-digit.
PACKAGE TYPE
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
512K-bit
1M-bit
W25X05CLSNIG
W25X10CLSNIG
W25X20CLSNIG
W25X05CLSVIG
W25X10CLSVIG
W25X20CLSVIG
W25X05CLSDIG
W25X10CLSDIG
W25X20CLSDIG
W25X05CLZPIG
W25X10CLZPIG
W25X20CLZPIG
25X05CLNIG
25X10CLNIG
25X20CLNIG
25X05CLVIG
25X10CLVIG
25X20CLVIG
25X05CLDIG
25X10CLDIG
25X20CLDIG
25X05CLIG
25X10CLIG
25X20CLIG
SN
SOIC-8 150-mil
2M-bit
512K-bit
1M-bit
SV
VSOP-8 150-mil
2M-bit
512K-bit
1M-bit
SD
TSSOP 173-mil
2M-bit
512K-bit
1M-bit
ZP(1)
WSON-8 6x5mm
2M-bit
0Hxxx
0Gxxx
1Hxxx
0Gxxxx
2Hxxx
0Gxxxx
512K-bit
1M-bit
W25X05CLUXIG
W25X10CLUXIG
W25X20CLUXIG
UX(2)
USON-8 2X3mm
2M-bit
Notes:
1. WSON package type ZP is not used in the top side marking.
2. USON package type UX has special top marking due to size limitation.
Publication Release Date: March 23, 2012
Revision B
- 50 -
W25X05CL/10CL/20CL
12. REVISION HISTORY
VERSION
DATE
PAGE
All
DESCRIPTION
New Create
A
B
2011/12/27
2012/3/23
5
Fixed Figure 1a & 1b
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Further more, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document and
the products and services described herein at any time, without notice.
Publication Release Date: March 23, 2012
- 51 -
Revision B
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