WED3C7558M350BI [WEDC]
RISC Microprocessor Multichip Package; RISC微处理器的多芯片封装
| 型号： | WED3C7558M350BI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | RISC Microprocessor Multichip Package |
| 文件： | 总13页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3C7558M-XBX
White Electronic Designs
RISC Microprocessor Multichip Package
OVERVIEW
The WEDC 755/SSRAM multichip package is targeted for
high performance, space sensitive, low power systems and
supports the following power management features: doze,
nap, sleep and dynamic power management.
The WED3C7558M-XBX is offered in Commercial (0°C
to +70°C), industrial (-40°C to +85°C) and military (-55°C
to +125°C) temperature ranges and is well suited for
embedded applications such as missiles, aerospace,
flight computers, fire control systems and rugged critical
systems.
The WED3C7558M-XBX multichip package consists of:
ꢀ
ꢀ
755 RISC processor
Dedicated 1MB SSRAM L2 cache, configured as
128Kx72
* This product is subject to change without notice.
ꢀ
ꢀ
21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
FEATURES
Core Frequency/L2 Cache Frequency (300MHz/
150MHz, 350MHz/175MHz)
ꢀ
Footprint compatible with WED3C750A8M-200BX
Footprint compatible with Motorola MPC 745
ꢀ
ꢀ
Maximum 60x Bus frequency = 66MHz
FIGURE 1 – MULTI-CHIP PACKAGE DIAGRAM
August 2002
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FIGURE 2 – BLOCK DIAGRAM
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FIGURE 3 – BLOCK DIAGRAM, L2 INTERCONNECT
SSRAM 1
L20VCC
U1
L2pin_DATA
L2pin_DATA
L2pin_DATA
L2pin_DATA
L2DP0-3
DQa
DQb
DQc
FT#
SBd#
SBc#
SBb#
SBa#
SW#
DQd
DP0-3
ADSP#
ADV#
SE2
L2 CLK_OUT A
L2WE#
K
SGW#
SE1#
L2CE#
ADSC#
SE3#
LBO#
G#
SA0-16
ZZ
A0-16
µP
755
SSRAM 2
L20VCC
U2
SA0-16
FT#
SBd#
SBc#
SBb#
SBa#
SW#
SGW#
SE1#
K
ADSP#
ADV#
L2CLK_OUT B
L2pin_DATA
L2pin_DATA
L2pin_DATA
L2pin_DATA
L2DP4-7
DQa
DQb
DQc
DQd
SE2
ADSC#
SE3#
LBO#
G#
DP0-3
ZZ
L2ZZ
FIGURE 4 – BLOCK DIAGRAM, L2 INTERCONNECT
TDI
L2 Cache
SSRAM
U1
L2 Cache
SSRAM
U2
STDI
STDO
755
TDO
TMS TCK TRST
STMS STCK
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FIGURE 5 – PIN ASSIGNMENTS
Ball assignments of the 255 CBGA package as viewed from the top surface.
Side profile of the CBGA package to indicate the direction of the top surface view.
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PACKAGE PINOUT LISTING
Signal Name
Pin Number
Active
I/O
2.0V (7)
3.3V (7)
A[0-31]
C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1,
High
I/O
F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1
AACK#
ABB#
AP[0-3]
ARTRY#
AVCC
BG#
BR#
BVSEL (4, 5, 6)
CI#
L2
K4
Low
Low
High
Low
—
Low
Low
High
Low
Low
Low
—
Low
Low
Low
Low
High
Input
I/O
C1, B4, B3, B2
I/O
J4
I/O
A10
—
2.0V
GND
2.0V
3.3V
L1
Input
Output
Input
Output
Input
Ouput
Output
I/O
B6
B1
E1
CKSTP_IN#
CKSTP_OUT#
CLK_OUT
DBB#
D8
A6
D7
J14
DBG#
N1
Input
Input
Input
I/O
DBDIS#
DBWO#
DH[0-31]
H15
G4
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9,
P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4
DL[0-31]
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16,
High
I/O
P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4
DP[0-7]
DRTRY#
GBL#
M2, L3, N2, L4, R1, P2, M4, R2
G16
High
Low
Low
—
I/O
Input
I/O
F1
GND
C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7,
—
GND
GND
H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9,
M11, M14, P5, P12
HRESET#
INT#
A7
Low
Low
High
High
—
Input
Input
Input
Input
—
B15
L1_TSTCLK (1)
L2_TSTCLK (1)
L2AVCC (8)
L2OVCC (9)
L2VSEL (4, 5, 6, 7)
LSSD_MODE# (1)
MCP#
NC (No-connect)
OVCC (2)
PLL_CFG[0-3]
QACK#
QREQ#
D11
D12
L11
2.0V
2.0V
*—
2.0V
3.3V
3.3V
E10, E12, M12, G12, G14, K12, K14
—
—
B5
B10
C13
High
Low
Low
—
Input
Input
Input
—
C3, C6, D5, D6, H4, A4, A5, A2, A3
C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10
—
—
A8, B9, A9, D9
High
Low
Low
Low
Low
Low
Input
Input
Output
Output
Input
Input
Input
Input
Output
D3
J3
RSRV#
SMI#
D1
A16
B14
B7
C8
J16
SRESET#
STCK (10)
STDI
—
—
—
—
—
—
STDO
* Not supported on this version
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PACKAGE PINOUT LISTING (continued)
Signal Name
STMS
SYSCLK
TA#
TBEN
TBST#
TCK
TDI (6)
TDO
TEA#
TLBISYNC#
TMS (6)
TRST# (6)
TS#
TSIZ[0-2]
TT[0-4]
WT
Pin Number
B8
C9
H14
C2
A14
C11
A11
A12
H13
C4
B11
C10
J13
A13, D10, B12
Active
I/O
Input
Input
Input
Input
I/O
Input
Input
Output
Input
Input
Input
Input
I/O
2.0V (7)
3.3V (7)
—
Low
High
Low
High
High
High
Low
Low
High
Low
Low
High
High
Low
—
Output
I/O
Output
—
B13, A15, B16, C14, C15
D2
VCC (2)
F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9
F3
2.0V
—
2.0V
—
VOLDET (3)
Low
Output
NOTES:
1. These are test signals for factory use only and must be pulled up to OVCC for
normal machine operation.
8. Uses one of 20 existing VCC pins in WEDC's WED3C750A8M-200BX, no board
level design changes are necessary. For new designs of WED3C7558M-XBX refer
to PLL power supply filtering.
9. L20VCC for future designs that will require 2.0V L2 cache power supply - compatible
with existing design using WED3C750A8M-200BX.
10. To disable SSRAM TAP controllers without interfering with the normal operation of
the devices, STCK should be tied low (GND) to prevent clocking the devices.
11. STDI and STMS are internally pulled up and may be left unconnected. Upon
power-up the SSRAM devices will come up in a reset state which will not interfere
with the operation of the device.
2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the
processor core.
3. Internally tied to GND in the BGA package to indicate to the power supply that a
low-voltage processor is present. This signal is not a power supply pin.
4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL
and L2VSEL independently to either OVCC (Selects 3.3V Interface) or to GND
(Selects 2.0V Interface).
5. Uses one of 15 existing no-connects in WEDC’s WED3C750A8M-200BX.
6. Internal pull up on die.
7. OVCC supplies power to the processor bus, JTAG, and all control signals except
the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2
cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT)
and the L2 control signals and the SSRAM power supplies; and VCC supplies power
to the processor core and the PLL and DLL (after filtering to become AVCC and
L2AVCC respectively). These columns serve as a reference for the nominal voltage
supported on a given signal as selected by the BVSEL/L2VSEL pin configurations
and the voltage supplied. For actual recommended value of Vin or supply voltages
see Recommended Operating Conditions.
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ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Value
Unit
V
Notes
(4)
Core supply voltage
PLL supply voltage
L2 DLL supply voltage
60x bus supply voltage
L2 bus supply voltage
Input supply
-0.3 to 2.5
AVCC
L2AVCC
OVCC
L2OVCC
VIN
-0.3 to 2.5
V
(4)
-0.3 to 2.5
V
(4)
-0.3 to 3.465
-0.3 to 3.465
-0.3 to 0VCC +0.3
-0.3 to L20VCC +0.3
-0.3 to 3.6
V
(3)
V
(3)
Processor Bus
L2 bus
V
(2)
VIN
V
(2)
JTAG Signals
VIN
V
(2)
Storage temperature range
TSTG
-55 to 150
°C
NOTES:
1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is
not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVCC by more than 0.3V at any time including during power-on reset.
3. Caution: OVCC/L2OVCC must not exceed VCC/AVCC/L2AVCC by more than 1.6 V at any time including during power-on reset.
4. Caution: VCC/AVCC/L2AVCC must not exceed L2OVCC/OVCC by more than 0.4 V at any time including during power-on reset.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
VCC
Recommended Value
2.0 100mV
2.0 100mV
2.0 100mV
2.0 100mV
3.3 165mV
3.3 165mV
GND to OVCC
GND to OVCC
Unit
V
Core supply voltage
PLL supply voltage
AVCC
L2AVCC
OVCC
OVCC
L20VCC
VIN
V
L2 DLL supply voltage
Processor bus supply voltage
V
BVSEL = 0
BVSEL = 1
V
V
L2 bus supply voltage
Input Voltage
L2VSEL = 1
Processor bus
JTAG Signals
V
V
VIN
V
NOTE: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
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POWER CONSUMPTION
VCC = AVCC = 2.0 0.1V Vdc, OVCC = 3.3V 5ꢀ Vdc, GND = 0 Vdc, 0 ꢁ TJ < 105°C
Processor (CPU) Frequency/L2 Frequency
300/150 MHz
350/175MHz
4.6
Unit
W
W
Notes
1, 3
1, 2
1, 2
1, 2
1, 2
1, 2
Full-on Mode
Typical
4.1
6.7
2.5
1700
1200
500
Maximum
Maximum
Maximum
Maximum
Maximum
7.9
2.8
1800
1300
500
Doze Mode
Nap Mode
Sleep Mode
Sleep Mode–PLL and DLL Disabled
W
mW
mW
mW
NOTES:
1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system dependent, but is typically
<10ꢀ of VCC power. Worst case power consumption, for AVCC=15mW and L2AVCC=15mW.
2. Maximum power is measured at VCC=2.1V while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally busy.
3. Typical power is an average value measured at VCC=AVCC=L2AVCC=2.0V, OVCC=L2OVCC=3.3V in a system, executing typical applications and benchmark sequences.
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure
and operate the L2 cache. It is cleared by hard reset or power-on reset.
FIGURE 5 – L2 CACHE CONTROL REGISTER (L2CR)
L2WT
L2DF
L2CS
L2PE
L2E
L2DO L2CTL L2TS
L2SL L2BYP
L2IO L2DRO
L2IP
L2SIZ L2CLK L2RAM
L2I
L20H
0
0
L2CTR
0
1
2
3
4
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
30 31
The L2CR bits are described in Table 1.
Reserved
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TABLE 1: L2CR BIT SETTINGS
Bit
0
Name
L2E
Function
L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache unit receives. Before
enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the L2 DLL must stabilize. All other L2CR bits
must be set appropriately. The L2 cache may need to be invalidated globally.
1
L2PE
L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When disabled, generated
parity is always zeros. L2 Parity is supported by WEDC’s WED3C7558M-XBX, but is dependent on application.
2–3
4–6
L2SIZ
L2CLK
L2 size — Should be set according to the size of the L2 data RAMs used.
11 1 Mbyte - Setting for WED3C7558M-XBX
L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock frequency that the L2 data
RAM interface is to operate at. When these bits are cleared, the L2 clock is stopped and the on-chip DLL for the L2 interface is
disabled. For nonzero values, the processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen,
the DLL must stabilize before the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower than the clock
frequency of the 60x bus interface.
000 L2 clock and DLL disabled
001 ÷ 1
010 ÷ 1.5
011 Reserved
100 ÷ 2
101 ÷ 2.5
110 ÷ 3
111 Reserved
7–8
9
L2RAM
L2DO
L2 RAM type — Configures the L2 RAM interface for the type of synchronous SRAMs used:
• Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out
The 755 does not burst data into the L2 cache, it generates an address for each access.
10 Pipelined (register-register) synchronous burst SRAM – Setting for WED3C7558M-XBX
L2 data only. Setting this bit enables data-only operation in the L2 cache. For this operation, instruction transactions from the L1
Instruction cache already cached in the L2 cache can hit in the L2, but new instruction transactions from the L1 instruction cache are
treated as cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO adn L2IO are set, the L2 cache is effectively
locked (cache misses do not cause new entries to be allocated but write hits use the L2).
10
11
L2I
L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must not be set while the L2
cache is enabled. See Motorola’s User manual for L2 Invalidation procedure.
L2CTL
L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode) signal for cache RAMs.
Sleep mode is supported by the WED3C7558M-XBX. While L2CTL is asserted, L2ZZ asserts automatically when the device enters
nap or sleep mode and negates automatically when the device exits nap or sleep mode. This bit should not be set when the device is
in nap mode and snooping is to be performed through deassertion of QACK#.
12
13
L2WT
L2TS
L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all writes to the L2 cache also
write through to the system bus. For these writes, the L2 cache entry is always marked as exclusive rather than modified. This bit
must never be asserted after the L2 cache has been enabled as previously-modified lines can get remarked as exclusive during
normal operation.
L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from dcbf and dcbst instructions to be
written only into the L2 cache and marked valid, rather than being written only to the system bus and marked invalid in the L2 cache
in case of hit. This bit allows a dcbz/dcbf instruction sequence to be used with the L1 cache enabled to easily initialize the L2 cache
with any address and data information. This bit also keeps dcbz instructions from being broadcast on the system and single-beat
cacheable store misses in the L2 from being written to the system bus.
0: Setting for the L2 Test support as this bit is reserved for tests.
14–15
L2OH
L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2 data RAMs.
00: Least Hold Time – Setting for WED3C7558M-XBX
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TABLE 1: L2CR BIT SETTINGS
Bit
16
Name
L2SL
Function
L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the delay through the DLL
to accommodate slower L2 RAM bus frequencies.
0: Setting for WED3C7558M-XBX because L2 RAM interface is operated above 100 MHz.
17
18
L2DF
L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.
0: Setting for WED3C7558M-XBX because late-write SRAMs are not used.
L2BYP
L2 DLL bypass is reserved.
0: Setting for WED3C7558M-XBX
19-20
21
—
Reserved. These bits are implemented but not used; keep at 0 for future compatibility.
L2IO
L2 Instruction-only. Setting this bit enables instruction-only operation in the L2 cache. For this operation, data transactions from the L1
data cache already cached in the L2 cache can hit in the L2 (including writes), but new data transactions (transactions that miss in the
L2) from the L1 data cashe are treated as cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO and L2IO are
set, the L2 cache is effectively locked (cache misses do not cause new entries to be allocated but write hits use the L2). Note that this
bit can be programmed dynamically.
22
23
L2CS
L2 Clock Stop. Setting this bit causes the L2 clocks to the SRAMs to automatically stop whenever the MPC755 enters nap or sleep
modes, and automatically restart when exiting those modes (including for snooping during nap mode). It operates by asynchronously
gating off the L2CLK_OUT [A:B] signals while in nap or sleep mode. The L2SYNC_OUT/SYNC_IN path remains in operation, keeping
the DLL synchronized. This bit is provided as a power-saving alternative to the L2CTL bit and its corresponding ZZ pin, which may not
be useful for dynamic stopping/restarting of the L2 interface from nap and sleep modes due to the relatively long recovery time from
ZZ negation that the SRAM requires.
L2DRO
L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a checkstop for the
processor. A potential rollover condition occurs when the DLL is selecting the last tap of the delay line, and thus may risk rolling over
to the first tap with one adjustment while in the process of keeping synchronized. Such a condition is improper operation for the DLL,
and, while this condition is not expected, it allows detection for added security. This bit can be set when the DLL is first enabled (set
with the L2CLK bits) to detect rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E bit)
after the DLL has achieved its initial lock.
24–30
31
L2CTR
L2IP
L2 DLL counter (read-only). These bits indicate the current value of the DLL counter (0 to 127). They are asynchronously read when
the L2CR is read, and as such should be read at least twice with the same value in case the value is asynchronously caught in
transition. These bits are intended to provide observability of where in the 128-bit delay chain the DLL is at any given time. Generally,
the DLL operation should be considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap
128).
L2 global invalidate in progress (read only)—See the Motorola user’s manual for L2 Invalidation procedure.
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PLL POWER SUPPLY FILTERING
The AVCC and L2AVCC power signals are provided on
are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the
AVCC pin to minimize noise coupled from nearby circuits.
An identical but separate circuit should be placed as close
as possible to the L2AVCC pin. It is often possible to route
directly from the capacitors to theAVCC pin, which is on the
periphery of the 255 BGAfootprint, without the inductance
of vias. The L2AVCC pin may be more difficult to route but
is proportionately less critical.
the WED3C7558M-XBX to provide power to the clock
generation phase-locked loop and L2 cache delay-locked
loop respectively. To ensure stability of the internal clock,
the power supplied to the AVCC input signal should be
filtered of any noise in the 500kHz to 10 MHz resonant
frequency range of the PLL. A circuit similar to the
one shown in Figure 6 using surface mount capacitors
with minimum Effective Series Inductance (ESL) is
recommended. Multiple small capacitors of equal value
FIGURE 6 – POWER SUPPLY FILTER CIRCUIT
10 Ω
Vcc
AVcc (or L2AVcc)
2.2 µF
2.2 µF
Low ESL surface mount capacitors
GND
August 2002
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PACKAGE DESCRIPTION
Package Outline
21x25mm
Interconnects
Pitch
255 (16x16 ball array less one)
1.27mm
3.90mm
0.8mm
Maximum module height
Ball diameter
PACKAGE DIMENSIONS 255 BALL GRID ARRAY
TOP VIEW
BOTTOM VIEW
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 111213141516
NOTES:
1. Dimensions in millimeters and paranthetically in inches.
2. A1 corner is designated with a ball missing the array.
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Ordering Information
WED 3 C 755 8M X B X
DEVICE GRADE:
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
B = 255 Ceramic Ball Grid Array
CORE FREQUENCY (MHz)
350 = 350MHz/175MHz L2 cache
300 = 300MHz/150MHz L2 cache
L2 CACHE DENSITY:
8Mbits = 128K x 72 SSRAM
PowerPC™:
Type 755 (D - Die Revision)
C = MULTICHIP PACKAGE
3 = PowerPC™
WHITE ELECTRONIC DESIGNS CORP.
PowerPC™ is a trademark of International Business Machine Corp.
August 2002
Rev. 7
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
WED3C755E8M-300BH9C
RISC Microprocessor, 32-Bit, 300MHz, CMOS, CBGA255, 21 X 25 MM, 3.90 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-255
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WED3C755E8M-300BH9M
RISC Microprocessor, 32-Bit, 300MHz, CMOS, CBGA255, 21 X 25 MM, 3.90 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-255
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