WED3C755BM300BC_技术文档

The WED3C7558M-XBX is offered in Commercial (0°C to

+70°C), industrial (-40°C to +85°C) and military (-55°C to

+125°C) temperature ranges and is well suited for embed-

ded applications such as missiles, aerospace, flight com-

puters, fire control systems and rugged critical systems.

The WEDC 755/SSRAM multichip package is targeted for

high performance, space sensitive, low power systems and

supports the following power management features: doze,

nap, sleep and dynamic power management.

*This data sheet describes a product that is subject to change without notice.

The WED3C7558M-XBX multichip package consists of:

• 755 RISC processor

• Dedicated 1MB SSRAM L2 cache, configured as

128Kx72

n Footprint compatible with WED3C750A8M-200BX

n Footprint compatible with Motorola MPC 745

• 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)

• Core Frequency/L2 Cache Frequency (300MHz/

150MHz, 350MHz/175MHz)

• Maximum 60x Bus frequency = 66MHz

April 2002 Rev. 6

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White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

Ball assignments of the 255 CBGA package as viewed from the top surface.

Side profile of the CBGA package to indicate the direction of the top surface view.

White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520

C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14,

High

I/O

A[0-31]

AACK

J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1

L2

Low

High

Low

—

Input

Output

I/O

ABB/AMONO (8)

AP[0-3]

ARTRY

K4

C1, B4, B3, B2

J4

I/O

AVDD

A10

—

2.0V

BG

L1

Low

High

Low

—

Input

Output

Input

Output

Input

Ouput

Output

Input

I/O

BR

B6

BVSEL (4, 5, 6)

CI

B1

HRESET OVDD

E1

CKSTP_IN

CKSTP_OUT

CLK_OUT

DBB

D8

A6

D7

J14

Low

High

DBG

N1

DBDIS

H15

DBWO

G4

P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8,

DH[0-31]

N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4

K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,

High

I/O

DL[0-31]

DP[0-7]

DRTRY

GBL

R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4

M2, L3, N2, L4, R1, P2, M4, R2

High

Low

—

I/O

Input

I/O

—

G16

F1

GND

C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12,

GND

J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12

HRESET

A7

Low

High

—

Input

—

INT

B15

L1_TSTCLK (1)

L2_TSTCLK (1)

L2AVDD (8)

L2OVDD (9)

L2VSEL (4, 5, 6, 7)

LSSD_MODE (1)

MCP

D11

D12

L11

2.0V

*—

2.0V

3.3V

E10, E12, M12, G12, G14, K12, K14

—

B5

High

Low

—

Input

—

B10

3.3V

C13

NC (No-connect)

OVDD (2)

PLL_CFG[0-3]

QACK

C3, C6, D5, D6, H4, A4, A5, A2, A3

C7, E5, G3, G5, K3, K5, P7, P10, E07, M05, M07, M10

—

A8, B9, A9, D9

High

Low

Input

Output

Input

Output

D3

QREQ

J3

RSRV

D1

SMI

A16

B14

B7

SRESET

STCK (10)

STDI

C8

—

STDO

J16

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STMS

B8

Input

I/O

SYSCLK

TA

C9

—

H14

Low

High

Low

High

Low

High

Low

High

—

TBEN

C2

TBST

A14

TCK

C11

Input

Output

Input

I/O

TDI (6)

TDO

A11

A12

TEA

H13

TLBISYNC

TMS (6)

TRST (6)

TS

C4

B11

C10

J13

TSIZ[0-2]

TT[0-4]

VDD (2)

VOLDET (3)

A13, D10, B12

Output

I/O

B13, A15, B16, C14, C15

F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9

F3

—

2.0V

—

2.0V

—

Low

Output

NOTES:

1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.

2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.

3. Internally tied to GND in the BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply pin.

4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVdd (Selects 3.3V Interface) or to GND

(Selects 2.0V Interface).

5. Uses one of 15 existing no-connects in WEDC’s WED3C750A8M-200BX.

6. Internal pull up on die.

7. OVdd supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies

power to the L2 cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals and the SSRAM power supplies; and Vdd

supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal

voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations and the voltage supplied. For actual recommended value of Vin or supply

voltages see Recommended Operating Conditions.

8. Uses one of 20 existing Vdd pins in WEDC's WED3C750A8M-200BX, no board level design changes are necessary. For new designs of WED3C7558M-XBX refer to PLL

power supply filtering.

9. L20Vdd for future designs that will require 2.0V L2 cache power supply - compatible with existing design using WED3C750A8M-200BX.

10. To disable SSRAM TAP controllers without interfering with the normal operation of the devices, STCK should be tied low (GND) to prevent clocking the devices.

11. STDI and STMS are internally pulled up and may be left unconnected. Upon power-up the SSRAM devices will come up in a reset state which will not interfere with

the operation of the device.

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Core supply voltage

PLL supply voltage

L2 DLL supply voltage

60x bus supply voltage

L2 bus supply voltage

Input supply

Vdd

-0.3 to 2.5

V

°C

(4)

(3)

(2)

AVdd

L2AVDD

OVdd

L2OVdd

Vin

-0.3 to 2.5

-0.3 to 3.465

-0.3 to 0Vdd +0.3

-0.3 to L20Vdd +0.3

-0.3 to 3.6

Processor Bus

L2 bus

Vin

JTAG Signals

Vin

Storage temperature range

Tstg

-55 to 150

NOTES:

1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage

to the device.

2.

3.

4.

Vin must not exceed OVdd by more than 0.3V at any time including during power-on reset.

OVdd/L2OVDD must not exceed Vdd/AVdd/L2AVdd by more than 1.6 V at any time including during power-on reset.

Vdd/AVdd/L2AVDD must not exceed L2OVdd/OVdd by more than 0.4 V at any time including during power-on reset.

Core supply voltage

Vdd

AVdd

L2AVdd

OVdd

L20Vdd

Vin

2.0v 100mV

2.0 100mV

V

PLL supply voltage

L2 DLL supply voltage

Processor bus supply

voltage

BVSEL = 0

BVSEL = 1

3.3v 165mV

GND to OVdd

L2 bus supply voltage

Input Voltage

L2VSEL = 1

Processor bus

JTAG Signals

Vin

NOTE:

These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed

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£

Full-on Mode

Typical

4.3

7.4

W

1, 3

1, 2

Maximum

Doze Mode

2.6

W

Nap Mode

1.3

W

Sleep Mode

1.26

500

W

Sleep Mode–PLL and DLL Disabled

mW

NOTES:

1. These values apply for all valid system bus and L2 bus ratios. The values do not include OVdd; AVdd and L2AVdd suppling power. OVdd power is

system dependent, but is typically <10% of Vdd power. Worst case power consumption, for AVdd=15mW and L2AVdd=15mW.

2. Maximum power is measured at Vdd=2.1V while running an entirely cache-resident, contrived sequence of instructions which keep the execution

units maximally busy.

3. Typical power is an average value measured at Vdd=AVdd=L2AVdd=2.0V, OVdd=L2OVdd=3.3V in a system, executing typical applications and

benchmark sequences.

The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure and

operate the L2 cache. It is cleared by hard reset or power-on reset.

L2WT

L2DF

L2BYP

L2CS

L2IO L2DRO

L2PE

L2DO

L2CTL L2TS

L2SL

L2IP

L2E

L2SIZ

L2CLK

L2RAM

L2I

L20H

0

L2CTR

0

1

2

3

4

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

30 31

The L2CR bits are described in Table 1.

Reserved

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0

L2E

L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache unit receives. Before

enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the L2 DLL must stabilize. All other L2CR bits must

be set appropriately. The L2 cache may need to be invalidated globally.

1

L2PE

L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When disabled, generated

parity is always zeros. L2 Parity is supported by WEDC’s WED3C7558M-XBX, but is dependent on application.

2–3

L2SIZ

L2 size—Should be set according to the size of the L2 data RAMs used.

4–6

L2CLK

L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock frequency that the

L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is stopped and the on-chip DLL for the L2

interface is disabled. For nonzero values, the processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock

ratio is chosen, the DLL must stabilize before the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower

than the clock frequency of the 60x bus interface.

000 L2 clock and DLL disabled

001 ¸ 1

010 ¸ 1.5

011 Reserved

¸

101 ¸ 2.5

110 ¸ 3

111 Reserved

7–8

L2RAM

L2DO

L2 RAM type—Configures the L2 RAM interface for the type of synchronous SRAMs used:

• Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out

The 755 does not burst data into the L2 cache, it generates an address for each access.

9

L2 data only. Setting this bit enables data-only operation in the L2 cache. For this operation, instruction transactions from the L1 Instruction

cache already cached in the L2 cache can hit in the L2, but new instruction transactions from the L1 instruction cache are treated as

cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO adn L2IO are set, the L2 cache is effectively locked (cache

misses do not cause new entries to be allocated but write hits use the L2).

10

11

L2I

L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must not be set while the L2

cache is enabled. See Motorola’s User manual for L2 Invalidation procedure.

L2CTL

L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode) signal for cache RAMs.

Sleep mode is supported by the

. While L2CTL is asserted, L2ZZ asserts automatically when the device

enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. This bit should not be set when the

device is in nap mode and snooping is to be performed through deassertion of QACK.

12

13

L2WT

L2TS

L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all writes to the L2 cache also write

through to the system bus. For these writes, the L2 cache entry is always marked as exclusive rather than modified. This bit must never be

asserted after the L2 cache has been enabled as previously-modified lines can get remarked as exclusive during normal operation.

L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from

written only into the L2 cache and marked valid, rather than being written only to the system bus and marked invalid in the L2 cache

in case of hit. This bit allows a z/ instruction sequence to be used with the L1 cache enabled to easily initialize the L2 cache

with any address and data information. This bit also keeps instructions from being broadcast on the system and single-beat

and

instructions to be

cacheable store misses in the L2 from being written to the system bus.

14–15

L2OH

L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2 data RAMs.

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16

L2SL

L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the delay through the DLL to

accommodate slower L2 RAM bus frequencies.

because L2 RAM interface is operated above 100 MHz.

L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.

because late-write SRAMs are not used.

17

18

L2DF

L2BYP

L2 DLL bypass is reserved.

19-20

21

—

Reserved. These bits are implemented but not used; keep at 0 for future compatibility.

L2IO

L2 Instruction-only. Setting this bit enables instruction-only operation in the L2 cache. For this operation, data transactions from the L1 data cache

already cached in the L2 cache can hit in the L2 (including writes), but new data transactions (transactions that miss in the L2) from the L1 data

cashe are treated as cache-inhibited (bypass L2 cache, no L2 checking done). When both L2DO and L2IO are set, the L2 cache is effectively

locked (cache misses do not cause new entries to be allocated but write hits use the L2). Note that this bit can be programmed dynamically.

22

23

L2CS

L2 Clock Stop. Setting this bit causes the L2 clocks to the SRAMs to automatically stop whenever the MPC755 enters nap or sleep modes, and

automatically restart when exiting those modes (including for snooping during nap mode). It operates by asynchronously gating off the

L2CLK_OUT [A:B] signals while in nap or sleep mode. The L2SYNC_OUT/SYNC_IN path remains in operation, keeping the DLL synchronized. This

bit is provided as a power-saving alternative to the L2CTL bit and its corresponding ZZ pin, which may not be useful for dynamic stopping/

restarting of the L2 interface from nap and sleep modes due to the relatively long recovery time from ZZ negation that the SRAM requires.

L2DRO

L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a checkstop for the processor.

A potential rollover condition occurs when the DLL is selecting the last tap of the delay line, and thus may risk rolling over to the first tap with

one adjustment while in the process of keeping synchronized. Such a condition is improper operation for the DLL, and, while this condition is

not expected, it allows detection for added security. This bit can be set when the DLL is first enabled (set with the L2CLK bits) to detect

rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E bit) after the DLL has achieved its initial lock.

24–30

31

L2CTR

L2IP

L2 DLL counter (read-only). These bits indicate the current value of the DLL counter (0 to 127). They are asynchronously read when the L2CR is

read, and as such should be read at least twice with the same value in case the value is asynchronously caught in transition. These bits are

intended to provide observability of where in the 128-bit delay chain the DLL is at any given time. Generally, the DLL operation should be

considered at risk if it is found to be within a couple of taps of its beginning or end point (tap 0 or tap 128).

L2 global invalidate in progress (read only)—See the Motorola user’s manual for L2 Invalidation procedure.

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The AVdd and L2AVdd power signals are provided on

the WED3C7558M-XBX to provide power to the clock

generation phase-locked loop and L2 cache delay-locked

loop respectively. To ensure stability of the internal clock,

the power supplied to the AVdd input signal should be

filtered of any noise in the 500kHz to 10 MHz resonant

frequency range of the PLL. A circuit similar to the one

shown in Figure 6 using surface mount capacitors with

minimum Effective Series Inductance (ESL) is recom-

mended. Multiple small capacitors of equal value are

recommended over a single large value capacitor. The

circuit should be placed as close as possible to the

AVdd pin to minimize noise coupled from nearby circuits.

An identical but separate circuit should be placed as

close as possible to the L2AVdd pin. It is often possible

to route directly from the capacitors to the AVdd pin,

which is on the periphery of the 255 BGA footprint,

without the inductance of vias. The L2AVdd pin may be

more difficult to route but is proportionately less critical.

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Package Outline

Interconnects

Pitch

21x25mm

255 (16x16 ball array less one)

1.27mm

3.90mm

0.8mm

Maximum module height

Ball diameter

NOTES:

1. Dimensions in millimeters and paranthetically in inches.

2. A1 corner is designated with a ball missing the array.

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M = Military Screened

I = Industrial

-55°C to +125°C

-40°C to +85°C

0°C to +70°C

C = Commercial

B = 255 Ceramic Ball Grid Array

350 = 350MHz/175MHz L2 cache

300 = 300MHz/150MHz L2 cache

8Mbits = 128K x 72 SSRAM

Ô

Type 755

Ô

PowerPCÔ is a trademark of International Business Machine Corp.

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型号：	WED3C755BM300BC
厂家：	ETC
描述：	Microprocessor 微处理器\n 微处理器
文件：	总13页 (文件大小：373K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

WED3C755BM300BC [ETC]

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