EDI2AG272129V12D1
更新时间：2024-09-18 05:55:05
品牌：WEDC
描述：2 Megabyte Sync/Sync Burst, Small Outline DIMM
概述
数据手册EDI2AG272129V12D1 概述
2 Megabyte Sync/Sync Burst, Small Outline DIMM 2兆字节同步/同步突发，小外形DIMM
EDI2AG272129V12D1 数据手册
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PDF下载EDI2AG272129V
White Electronic Designs
ADVANCED*
2 Megabyte Sync/Sync Burst, Small Outline DIMM
DESCRIPTION
FEATURES
The EDI2AG272129VxxD1 is a Synchronous/
Synchronous Burst SRAM, 72 position SO DIMM (144
contacts) Module, organized as 2x128Kx72. The Module
contains four (4) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Substrate. The
module architecture is defined as a Sync/Sycn Burst,
Flow-Through, with support for sequential burst. This
module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high performance cost advantage
over BiCMOS aysnchronous device architectures.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Sequential Burst MODE
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables
(BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally self-timed Write
Gold Lead Finish
3.3V 1ꢀ0 Operation
Access Speed(s): TKHQV=8.5, 9, 1ꢀ, 12ns
Common Data I/O
High Capacitance (3ꢀpf) drive, at rated Access Speed
Single total array Clock
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Synchronous Only operations are performed via
strapping ADSC# Low, and ADSP# / ADV# High, which
provides for Ultra Fast Accesses in Read Mode while
providing for internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in
relation to an externally supplied clock, Registered
Address, Registered Global Write, Registered Enables
as well as anAsynchronous Output enable. This Module
has been defined with full flexibility, which allows
individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
Multiple Vcc and Gnd
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN SYMBOLS
PIN NAMES
PIN FUNCTION PIN FUNCTION
PIN FUNCTION PIN
FUNCTION
DQ41
DQ46
DQ42
DQ45
DQ43
DQ44
VSS
DQꢀ-DQ63
Input/Output Bus
1
VSS
VSS
37
38
39
4ꢀ
41
42
43
44
45
46
47
48
49
5ꢀ
51
52
53
54
55
56
57
58
59
6ꢀ
61
62
63
64
65
66
67
68
69
7ꢀ
71
72
DQꢀ
DQ7
DQ1
DQ6
DQ2
DQ5
DQ3
DQ4
VSS
73
74
VSS
VSS
1ꢀ9
11ꢀ
111
112
113
114
115
116
117
118
119
12ꢀ
121
122
123
124
125
126
127
128
129
13ꢀ
131
132
133
134
135
136
137
138
139
14ꢀ
141
142
143
144
DQPꢀ-DQP7 Parity Bits
2
Aꢀ-A16
E1#, E2#
BWE#
Address Bus
3
Aꢀ
75
BW4#
DQP3
VCC
Synchronous Bank Enables
Byte Write Mode Enable
4
RFU
A16
A1
76
5
77
BW1#-BW8# Byte Write Enables
6
78
VCC
CK
Array Clock
7
A2
79
DQ24
DQ31
DQ25
DQ3ꢀ
DQ26
DQ29
DQ27
DQ28
VSS
8
A15
A14
A3
8ꢀ
VSS
GW#
Synchronous Global write
Enable
9
81
BW7#
DQP6
VCC
1ꢀ
11
12
13
14
15
16
17
18
19
2ꢀ
21
22
23
24
25
26
27
28
29
3ꢀ
31
32
33
34
35
36
VSS
82
G#
Asynchronous Output
Enable
A4
BW2#
DQP1
VCC
83
Vcc
Vss
3.3V Power Supply
Gnd
A13
A12
A5
84
VCC
85
DQ48
DQ55
DQ49
DQ54
DQ5ꢀ
DQ53
DQ51
DQ52
VSS
VCC
86
A6
DQ8
DQ15
DQ9
DQ14
DQ1ꢀ
DQ13
DQ11
DQ12
VSS
87
A11
A1ꢀ
A7
88
VSS
89
BW5#
DQP4
VCC
9ꢀ
A8
91
A9
92
VCC
VCC
VCC
G#
93
DQ32
DQ39
DQ33
DQ38
DQ34
DQ37
DQ35
DQ36
VSS
94
VSS
95
BW8#
DQP7
VCC
RFU
GW#
ADV#
ADSP#
ADSC#
E1#
VSS
96
BW3#
DQP2
VCC
97
98
VCC
99
DQ56
DQ63
DQ57
DQ62
DQ58
DQ61
DQ59
DQ6ꢀ
VSS
VCC
1ꢀꢀ
1ꢀ1
1ꢀ2
1ꢀ3
1ꢀ4
1ꢀ5
1ꢀ6
1ꢀ7
1ꢀ8
DQ16
DQ23
DQ17
DQ22
DQ18
DQ21
DQ19
DQ2ꢀ
CK
VSS
E2#
BW6#
DQP5
VCC
BWE#
BW1#
DQPꢀ
VCC
VCC
VCC
DQ4ꢀ
DQ47
VSS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
A0-16
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
ADSC#
ADSP#
ADV#
BWE#
CK
DQ0-31
DQP0-3
DQ
G#
GW#
E1#
BW1-4#
E#
BW#
U1
ADSC#
ADSP#
ADV#
BWE#
CK
DQ0-31
DQP0-3
DQ
G#
GW#
E#
BW#
E2#
U2
ADSC#
ADSP#
ADV#
BWE#
CK
DQ32-63
DQP4-7
DQ
G#
GW#
E#
BW#
U3
BW5-8#
ADSC#
ADSP#
ADV#
BWE#
CK
DQ32-63
DQP4-7
DQ
G#
GW#
E#
BW#
U4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
PIN DESCRIPTIONS
DIMM
Pins
Symbol
Type
Description
3, 6, 7, 1ꢀ, 11, 14
15, 18, 19, 2ꢀ, 17
16, 13, 12, 9, 8, 5
Aꢀ-A16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with Aꢀ and A1, during burst and wait cycle.
33, 47, 61, 75,
BW1#, BW2#,
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BWꢀ# controls DQꢀ-7 and DQPꢀ, BW1# controls DQ8-15 and DQP1. BW2#
controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ4ꢀ-47 and DQP5.
BW6#controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
89, 1ꢀ3, 117, 131 BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
32
25
BWE#
GW#
Input
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
Synchronous
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times
around the rising edge of CK.
3ꢀ
CK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
29, 31
23
E1#, E2#
G#
Input
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
Synchronous
Input
Output Enable: This active LOW asynchronous input enables the data output
drivers.
26
ADV#
ADSP#
Input
Address Status Processor: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address advance)
Synchronous
27
Input
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
28
ADSC#
DQꢀ-63
DQPꢀ-7
Input
Address Status Controller: This active LOW input causes device to be de-selected
or selected along with new external address to be registered.
Synchronous
A READ or WRITE cycle is initiated depending upon write control inputs.
Various
Input/Output
Input/Output
Data Inputs/Outputs: First byte is DQꢀ-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ4ꢀ-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
38, 48, 62,
76, 9ꢀ, 1ꢀ4,
118, 132
Parity Inputs/Outputs: DQPꢀ is parity bit for DQꢀ-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ32-39. DQP5 is parity bit for DQ4ꢀ-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as
a 128K x 64, the parity bits need to be tied to Vss through a 1ꢀK ohm resistor.
Various
Various
Vcc
Vss
Supply
Ground
Core power supply: +3.3V -50/ + 1ꢀ0
Ground
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
H
X
L
E2#
X
H
H
H
L
ADSP# ADSC# ADV# GW#
G#
X
X
L
CK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Addr. Used
None
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
High-Z
High-Z
None
X
X
X
X
L
Q
External
External
External
External
External
External
External
External
External
External
Next
L
L
H
L
High-Z
H
H
L
L
Q
L
L
H
X
X
L
High-Z
H
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
X
H
X
H
H
H
H
X
X
X
X
H
X
H
X
D
H
L
L
L
D
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
L
Q
L
L
H
L
High-Z
H
H
X
X
H
H
H
H
H
H
X
H
H
H
X
X
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Q
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
L
High-Z
Next
L
Q
Next
L
H
X
X
X
X
L
High-Z
Next
L
D
Next
L
L
D
Next
L
L
D
Next
L
L
D
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
L
High-Z
Q
H
L
High-Z
Q
H
L
High-Z
Q
H
X
X
X
X
High-Z
D
D
D
D
L
L
L
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1#
L
E2#
H
GW#
G#
H
L
ZZ
L
CK
DQ
High-Z
ꢀ
ꢀ
ꢀ
ꢀ
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
L
H
L
L
H
L
H
H
L
L
H
L
L
L
High-Z
H
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Voltage on VCC Relative to VSS
VIN
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
-ꢀ.5V to +4.6V
-ꢀ.5V to VCC +ꢀ.5V
-55°C to +125°C
ꢀ°C to +7ꢀ°C
-4ꢀ°C to +85°C
1ꢀ mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
VCC
VSS
VIH
VIL
ILI
3.14
ꢀ.ꢀ
1.1
-ꢀ.3
-2
3.3
ꢀ.ꢀ
3.ꢀ
ꢀ.ꢀ
1
3.6
ꢀ.ꢀ
VCC+ꢀ.3
ꢀ.3
2
V
V
V
V
µA
µA
ILO
-2
1
2
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
SYM
Typ
Units
8.5
9
10
12
Power Supply Current
Power Supply Current Device
Selected, No Operation
Icc1
Icc
1.6
2.2
2.1
2.1
2.ꢀ
A
A
75ꢀ
1.5
1.5
1.ꢀ
1.ꢀ
CMOS Standby
Clock Running-Deselect
Icc3
IccK
25ꢀ
6ꢀꢀ
3ꢀꢀ
1ꢀꢀꢀ
3ꢀꢀ
1ꢀꢀꢀ
3ꢀꢀ
75ꢀ
3ꢀꢀ
75ꢀ
mA
mA
AC TEST LOAD
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.ꢀV
1.25V
DQ
Input and Output Timing Ref.
Output Test equivalencies
Z
= 50 Ω
0
50 Ω
Fig. 1
Output Load Equivalent
Vt = 1.25V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
BURST ADDRESS TABLE (MODE=NC/VCC)
BURST ADDRESS TABLE (MODE=GND)
First
Second
Address
(internal)
A-Aꢀ1
A-Aꢀꢀ
A-A11
A-A1ꢀ
Third
Fourth
First
Second
Address
(internal)
A-Aꢀ1
A-A1ꢀ
A-A11
A-Aꢀꢀ
Third
Fourth
Address
Address
Address
Address
Address
(external)
A-Aꢀꢀ
Address
(external)
A-Aꢀꢀ
(internal)
A-A1ꢀ
A-A11
A-Aꢀꢀ
A-Aꢀ1
(internal)
A-A11
A-A1ꢀ
A-Aꢀ1
A-Aꢀꢀ
(internal)
A-A1ꢀ
A-A11
A-Aꢀꢀ
A-Aꢀ1
(internal)
A-A11
A-Aꢀꢀ
A-Aꢀ1
A-A1ꢀ
A-Aꢀ1
A-A1ꢀ
A-A11
A-Aꢀ1
A-A1ꢀ
A-A11
READ CYCLE TIMING PARAMETERS
8.5ns
9ns
10ns
12ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
Sym
tKHKH
Min
Max
Min
1ꢀ
4
Max
Min
12
5
Max
Min Max
15
5
*
*
*
*
*
*
*
*
*
*
*
*
*
*
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
*
*
*
*
*
*
*
*
*
*
*
*
4
5
5
9
1ꢀ
12
3
2
3
2
3
2
4
4
4
4
5
ꢀ
ꢀ
ꢀ
5
2.5
2.5
1.ꢀ
1.ꢀ
2.5
2.5
1.ꢀ
1.ꢀ
2.5
2.5
1.ꢀ
1.ꢀ
*TBD
SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KLKH
t
KHKL
CK
t
AVKH
EX#
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G#
GW#
DQ
t
GLQV
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
SYNC-BURST READ CYCLE
tKHKH
tKHKL
tKLKH
CK
t
SPVKH
tKHSPX
ADSP#
t
SCVKH
tKHSCX
ADSC#
ADDR
t
AVKH
t
KHAX
BWx#,
GW#
tEVKH
tKHEX
EX#
tAVVKH
tKHAVX
ADV#
G#
tGHQX
tKHQV
tGLQV
t
GHQZ
tGLQX
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
WRITE CYCLE TIMING PARAMETERS
8.5ns
Min Max
9ns
10ns
Max
12ns
Min Max
Units
ns
Description
Clock Cycle Time
Sym
tKHKH
Min
1ꢀ
Max
Min
12
15
Clock High Time
tKHKL
4
5
5
ns
Clock Low Time
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
4
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
2.5
1.ꢀ
Data Hold
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
SYNC (NON-BURST) WRITE CYCLE
t
KHKH
t
AVKH
t
KHKL
tKLKH
t
KHAX
CK
Ex#
ADDR
Addr 1
Addr 1
Addr 2
t
KHGWH
KHGH
t
GWLKH
GW#
G#
t
DQ
t
KHDX
t
DVKH
t
GHKH
Write Cycle
Back to Back Writes
SYNCBURST WRITE CYCLE
t
KHKH
t
KHKL
tKLKH
CK
ADSP#
ADSC#
ADDR
t
AVKH
t
KHAX
BWx#
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
t
DVKH
t
KHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write - Cycle
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
SYNC (NON-BURST) READ/WRITE CYCLE
t
KHKH
t
KHKL
t
KLKH
CK
t
AVKH
CE#
Addr 1
Addr 2
ADDR
tKHQV
tKHDX
G#
GW#
t
KHQX
DQ
Q (Addr 1)
D (Addr 2)
t
KHDX
t
DVKH
Read Cycle
Write Cycle
Back to Back Cycles
G# Controlled
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V
White Electronic Designs
ADVANCED
PACKAGE DESCRIPTION
Package No. 409
144 Lead
SO DIMM
2.667 MAX.
0.175
MAX.
0.157
R18
R17
1.000
MAX.
U1
U3
0.788
P1
0.181 TYP
0.913
1.112
1.291
1.490
ORDERING INFORMATION
Part Number
Organization
Voltage
Speed (ns)
Package
2x128Kx72
2x128Kx72
2x128Kx72
2x128Kx72
144 SO-DIMM
144 SO-DIMM
144 SO-DIMM
144 SO-DIMM
EDI2AG272129V85D1*
EDI2AG272129V9D1*
EDI2AG272129V1ꢀD1
EDI2AG272129V12D1
*Consult Factory for Availability
3.3
3.3
3.3
3.3
8.5
9
1ꢀ
12
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI2AG272129V12D1 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| EDI2AG272129V85D1 | WEDC | 2 Megabyte Sync/Sync Burst, Small Outline DIMM | 获取价格 |
|
| EDI2AG272129V9D1 | WEDC | 2 Megabyte Sync/Sync Burst, Small Outline DIMM | 获取价格 |
|
| EDI2AG27264V10D1 | WEDC | SRAM Module, 128KX72, 10ns, CMOS, PDMA144, | 获取价格 |
|
| EDI2AG27264V12D1 | WEDC | SRAM Module, 128KX72, 12ns, CMOS, PDMA144, | 获取价格 |
|
| EDI2AG27264V85D1 | WEDC | SRAM Module, 128KX72, CMOS, PDMA144, | 获取价格 |
|
| EDI2CG264128V15D1 | WEDC | SRAM Module, 256KX64, 15ns, CMOS, SODIMM-144 | 获取价格 |
|
| EDI2CG264128V85D1 | WEDC | SRAM Module, 256KX64, 8.5ns, CMOS, SODIMM-144 | 获取价格 |
|
| EDI2CG272128V | WEDC | 2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM | 获取价格 |
|
| EDI2CG272128V-D1 | ETC | SSRAM Modules | 获取价格 |
|
| EDI2CG272128V12D1 | WEDC | 2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM | 获取价格 |
|
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