5962-9559504H9X [WEDC]
SRAM Module, 128KX32, 70ns, CMOS, CQMA68, CERAMIC, LQFP-68;
| 型号： | 5962-9559504H9X |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | SRAM Module, 128KX32, 70ns, CMOS, CQMA68, CERAMIC, LQFP-68 静态存储器 |
| 文件： | 总10页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WS128K32-XXX
128Kx32 SRAM MODULE, SMD 5962-93187
FEATURES
n Access Times of 70, 85, 100, 120ns
n MIL-STD-883 Compliant Devices Available
n Packaging
n Commercial, Industrial and Military Temperature
Ranges
n 5 Volt Power Supply
n Low Power CMOS
66-pin, PGA Type, 19075 inch square, Hermetic
Ceramic HIP (Package 400)9
n TTL Compatible Inputs and Outputs
68 lead, 40mm Low Profile CQFP, 3956mm
(09140")(Package 502)9
n Built in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation
68 lead, Hermetic CQFP (G2U), 2294mm
(09880 inch) square, 4957mm (09140 inch)
high, (Package 510)
n Weight
WS128K32-XG1U - 5 grams typical
WS128K32-XG2UX - 8 grams typical
WS128K32-XH1X - 13 grams typical
WS128K32-XG4TX - 20 grams typical
68 lead, Hermetic CQFP (G1U), 239ꢀmm
(09ꢀ40 inch) square, 4957mm (09140inch) high,
(Package 51ꢀ)
n All devices are upgradeable to 512Kx32
n Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
FIGꢀ 1 PIN CONFIGURATION FOR WS128K32N-XH1X
TOP VIEW
PINDESCRIPTION
I/O0-31
A0-16
WE1-4
CS1-4
OE
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
1
12
23
34
45
56
I/O
I/O
8
9
WE
CS
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
2
CS
4
Output Enable
Power Supply
Ground
I/O10
GND
I/O11
WE
4
VCC
A
A
A
A
14
16
11
0
A
7
I/O27
GND
NC
Not Connected
A
A
A
V
10
9
A12
A
A
4
5
6
3
3
A
A
A
1
2
3
NC
NC
BLOCKDIAGRAM
15
CC
WE
1
A13
A
NC
I/O
I/O
I/O
I/O
7
A
8
WE
CS
I/O23
I/O22
I/O21
I/O20
I/O
I/O
I/O
0
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
1
2
5
4
GND
I/O19
3
11
22
33
44
55
66
September2001Revꢀ3
WhiteElectronicDesignsCorporation(602)437-1520wwwꢀwhiteedcꢀcom
1
WS128K32-XXX
FIGꢀ 2 PIN CONFIGURATION FOR WS128K32-XG4TX
TOP VIEW
PINDESCRIPTION
I/O0-31
A0-16
WE
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
CS1-4
OE
VCC
GND
NC
Not Connected
BLOCKDIAGRAM
CS3
CS4
CS1
CS2
WE
OE
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIGꢀ3 PIN CONFIGURATION FOR WS128K32-XG1UX
AND WS128K32-XG2UX
TOP VIEW
PINDESCRIPTION
I/O0-31
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
A0-16
WE1-4
CS1-4
OE
Output Enable
Power Supply
Ground
VCC
GND
NC
Not Connected
BLOCKDIAGRAM
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2
WS128K32-XXX
TRUTHTABLE
ABSOLUTEMAXIMUMRATINGS
Parameter
Symbol
TA
Min
-55
Max
+125
+150
Vcc+0$5
150
Unit
°C
°C
V
CS
H
L
OE
X
WE
X
Mode
Standby
Read
Data I/O
High Z
Power
Standby
Active
Active
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
L
H
Data Out
High Z
TSTG
VG
-65
L
H
X
H
Out Disable
Write
-0$5
L
L
Data In
TJ
°C
V
VCC
-0$5
7$0
CAPACITANCE
(TA = +25°C)
RECOMMENDEDOPERATINGCONDITIONS
Parameter
Symbol
VCC
Min
4$5
Max
5$5
Unit
V
Parameter
Symbol
COE
Conditions
IN = 0 V, f = 1$0 MHz
VIN = 0 V, f = 1$0 MHz
Max Unit
Supply Voltage
Input High Voltage
Input Low Voltage
OE capacitance
V
50
pF
pF
VIH
2$2
VCC + 0$3
+0$8
V
WE1-4 capacitance
HIP (PGA)
CWE
VIL
-0$5
V
20
50
20
15
CQFP G4T
CQFP G1U
CQFP G2U
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1$0 MHz
I/O = 0 V, f = 1$0 MHz
IN = 0 V, f = 1$0 MHz
20
20
50
pF
pF
pF
Data I/O capacitance
Address input capacitance
V
V
This parameter is guaranteed by design but not tested$
DCCHARACTERISTICS
(VCC = 590V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Sym
Conditions
-70
-85
-100
Max
-120
Units
Min
Max
Min
Max
Min
Min
Max
Input Leakage Current
ILI VCC = 5ꢀ5, VIN = GND to VCC
10
10
10
10
µA
µA
mA
2
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC
Operating Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5ꢀ5
10
120
2
10
10
10
120
120
120
Standby Current
ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5ꢀ5
VOL IOL = 2ꢀ1mA, Vcc = 4ꢀ5
0
2
0
0
Output Low Voltage
Output High Voltage
0ꢀ4
0ꢀ4
0ꢀ4
0ꢀ4
V
VOH IOH = -1ꢀ0mA, Vcc = 4ꢀ5
2ꢀ4
2ꢀ4
2ꢀ4
2ꢀ4
V
NOTE: DC test conditions: VIH = VCC -0$3V, VIL = 0$3V
DATARETENTIONCHARACTERISTICS
(TA = -55°C to +125°C)
Parameter
Symbol
Conditions
-70
-85
-100
Min Max
-120
Units
Min Max Min Max
Min Max
Data Retention
Supply Voltage
VDR
CS³VCC -0$2V
VCC = 3V
2$0
5$5
4
2$0
5$5
4
2$0
5$5
4
2$0
5$5
4
V
Data Retention
Current
ICCDR1
mA
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WS128K32-XXX
ACCHARACTERISTICS
(VCC = 590V, TA = -55°C To +125°C)
Parameter
Symbol
-70
-85
-100
-120
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tAA
70
85
100
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
85
100
120
Output Hold from Address Change
Chip Select Access Time
tOH
3
3
3
3
tACS
tOE
70
35
85
45
100
50
120
60
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tCLZ1
tOLZ1
tCHZ1
tOHZ1
3
0
3
0
3
0
3
0
25
25
25
25
35
35
35
35
1$ This parameter is guaranteed by design but not tested$
ACCHARACTERISTICS
(VCC = 590V, TA = -55°C To +125°C)
Parameter
Symbol
-70
-85
-100
-120
Units
Write Cycle
Min
70
60
60
30
50
5
Max
Min
85
75
75
35
55
5
Max
Min
100
80
80
40
70
5
Max
Min
120
100
100
50
80
5
Max
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
tAH
5
5
5
5
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tOW1
tWHZ1
tDH
5
5
5
5
25
25
35
35
0
0
0
0
1$ This parameter is guaranteed by design but not tested$
ACTESTCONDITIONS
FIGꢀ4
Parameter
Typ
Unit
ACTESTCIRCUIT
Input Pulse Levels
VIL = 0, VIH = 3ꢀ0
V
ns
V
IOL
Input Rise and Fall
5
Current Source
Input and Output Reference Level
Output Timing Reference Level
1$5
1$5
V
D.U.T.
VZ 1.5V
NOTES:
(Bipolar Supply)
VZ is programmable from -2V to +7V$
Ceff = 50 pf
IOL & IOH programmable from 0 to 16mA$
Tester Impedance Z0 = 75W$
VZ is typically the midpoint of VOH and VOL$
IOL & IOH are adjusted to simulate a typical resistive load circuit$
IOH
Current Source
ATE tester includes jig capacitance$
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WS128K32-XXX
FIGꢀ5
TIMINGWAVEFORM-READCYCLE
FIGꢀ6
WRITECYCLE-WECONTROLLED
FIGꢀ7
WRITECYCLE-CSCONTROLLED
tWC
ADDRESS
WS32K32-XHX
tAW
tAH
tAS
tCW
CS
tWP
WE
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
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WS128K32-XXX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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WS128K32-XXX
PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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7
WS128K32-XXX
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The White 68 lead G2U
CQFP fills the same fit
and function as the
JEDEC 68 lead CQFJ or
68 PLCC9 But the G2U
has the TCE and lead
inspection advantage of
the CQFP form9
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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WS128K32-XXX
ORDERINGINFORMATION
W S 128K 32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGETYPE:
H1 = 1$075" sq$ Ceramic Hex-In-line Package, HIP (Package 400)
G1U = 23$9mm Ceramic Quad Flat Pack, CQFP (Package 519)
G2U = 22$4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
G4T = 40 mm Low Profile CQFP (Package 502)
ACCESS TIME (ns)
IMPROVEMENT MARK:
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrades
ORGANIZATION, 128Kx32
User configurable as 256Kx16 or 512Kx8
SRAM
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WS128K32-XXX
DEVICE TYPE
SPEED
PACKAGE
SMD NOꢀ
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
120ns
100ns
85ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-93187 01H5X
5962-93187 02H5X
5962-93187 03H5X
5962-93187 04H5X
70ns
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
120ns
100ns
85ns
68 lead CQFP/J (G1U)
68 lead CQFP/J (G1U)
68 lead CQFP/J (G1U)
68 lead CQFP/J (G1U)
5962-95595 01H9X
5962-95595 02H9X
5962-95595 03H9X
5962-95595 04H9X
70ns
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
120ns
100ns
85ns
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
5962-95595 01HNX
5962-95595 02HNX
5962-95595 03HNX
5962-95595 04HNX
70ns
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
128K x 32 SRAM Module
120ns
100ns
85ns
68 lead CQFP Low Profile (G4T) 5962-95595 01HYX
68 lead CQFP Low Profile (G4T) 5962-95595 02HYX
68 lead CQFP Low Profile (G4T) 5962-95595 03HYX
68 lead CQFP Low Profile (G4T) 5962-95595 04HYX
70ns
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