SIRA10BDP-T1-GE3 [VISHAY]
MOSFET N-CHAN 30V;
| 型号： | SIRA10BDP-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | MOSFET N-CHAN 30V |
| 文件： | 总13页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiRA10BDP
Vishay Siliconix
www.vishay.com
N-Channel 30 V (D-S) MOSFET
FEATURES
• TrenchFET® Gen IV power MOSFET
PowerPAK® SO-8 Single
D
D
7
8
D
6
• 100 % Rg and UIS tested
D
5
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
1
2
S
S
APPLICATIONS
D
3
4
G
S
1
• High power density DC/DC
• Synchronous rectification
Top View
Bottom View
PRODUCT SUMMARY
VDS (V)
• VRMs and embedded DC/DC
G
30
R
DS(on) max. () at VGS = 10 V
0.0036
0.0050
11.7
RDS(on) max. () at VGS = 4.5 V
Qg typ. (nC)
S
I
D (A)
60 a, g
N-Channel MOSFET
Configuration
Single
ORDERING INFORMATION
Package
PowerPAK SO-8
Lead (Pb)-free and halogen-free
SiRA10BDP-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
SYMBOL
LIMIT
30
+20, -16
60 g
UNIT
VDS
VGS
V
TC = 25 °C
C = 70 °C
TA = 25 °C
TA = 70 °C
T
60 g
Continuous drain current (TJ = 150 °C)
ID
30 b, c
24 b, c
150
39
4.6 b, c
A
Pulsed drain current (t = 100 μs)
IDM
IS
TC = 25 °C
Continuous source-drain diode current
TA = 25 °C
L = 0.1 mH
TC = 25 °C
Single pulse avalanche current
Single pulse avalanche energy
IAS
EAS
20
20
43
mJ
W
TC = 70 °C
28
Maximum power dissipation
PD
TA = 25 °C
TA = 70 °C
5 b, c
3.2 b, c
-55 to +150
260
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d, e
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SMYBOL
RthJA
RthJC
TYPICAL
MAXIMUM
UNIT
Maximum junction-to-ambient b, f
t 10 s
Steady state
20
2.3
25
2.9
°C/W
Maximum junction-to-case (drain)
Notes
a. Based on TC = 25 °C
b. Surface mounted on 1" x 1" FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 70 °C/W
g. Package limited
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiRA10BDP
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
Drain-source breakdown voltage (c)
(transient)
VDS
VGS = 0 V, ID = 250 μA
30
36
-
-
-
-
V
VGS = 0 V, ID(aval) = 70 A,
VDSt
ttranscient 50 ns
V
DS temperature coefficient
VDS/TJ
VGS(th)/TJ
VGS(th)
-
-
18
-
ID = 250 μA
mV/°C
VGS(th) temperature coefficient
Gate-source threshold voltage
Gate-source leakage
-3.8
-
VDS = VGS, ID = 250 μA
VDS = 0 V, VGS = +20, -16 V
VDS = 30 V, VGS = 0 V
1.2
-
-
2.4
V
IGSS
-
100
nA
-
-
1
Zero gate voltage drain current
On-state drain current a
IDSS
ID(on)
RDS(on)
gfs
μA
A
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS 5 V, VGS = 10 V
-
-
-
10
25
-
-
VGS = 10 V, ID = 10 A
0.0023
0.0035
68
0.0036
0.0050
-
Drain-source on-state resistance a
S
VGS = 4.5 V, ID = 7 A
-
Forward transconductance a
Dynamic b
VDS = 10 V, ID = 20 A
-
Input capacitance
Ciss
Coss
Crss
-
-
1710
655
68
-
-
Output capacitance
Reverse transfer capacitance
pF
VDS = 15 V, VGS = 0 V, f = 1 MHz
VDS = 15 V, VGS = 10 V, ID = 10 A
-
-
Crss/Ciss ratio
-
0.040
24.1
11.7
4.2
2.8
18
0.080
36.2
17.6
-
-
Total gate charge
Qg
-
Gate-source charge
Gate-drain charge
Output charge
Gate resistance
Turn-on delay time
Rise time
Qgs
Qgd
Qoss
Rg
VDS = 15 V, VGS = 4.5 V, ID = 10 A
-
nC
-
-
VDS = 15 V, VGS = 0 V
f = 1 MHz
-
-
0.3
-
1.3
7
2.6
15
40
50
20
35
70
60
30
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
-
20
VDD = 15 V, RL = 1.5
ID 10 A, VGEN = 10 V, Rg = 1
Turn-off delay time
Fall time
-
25
-
10
ns
Turn-on delay time
Rise time
-
17
-
35
VDD = 15 V, RL = 1.5
ID 10 A, VGEN = 4.5 V, Rg = 1
Turn-off delay time
Fall time
-
30
-
15
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulse diode forward current a
Body diode voltage
IS
ISM
VSD
trr
TC = 25 °C
IS = 10 A
-
-
-
-
-
-
-
-
-
39
150
1.1
70
70
-
A
0.75
38
36
20
18
V
Body diode reverse recovery time
Body diode reverse recovery charge
Reverse recovery fall time
ns
nC
Qrr
ta
IF = 10 A, di/dt = 100 A/μs,
TJ = 25 °C
ns
Reverse recovery rise time
tb
-
Notes
a. Pulse test: pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
c. Based on characterization, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiRA10BDP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
100
80
60
40
20
0
10000
1000
100
100
80
60
40
20
0
10000
1000
100
VGS = 10 V thru 4 V
TC = 25 °C
VGS = 3 V
TC = 125 °C
TC = -55 °C
10
10
0
0
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
2nd line
VGS - Gate-to-Source Voltage (V)
2nd line
Output Characteristics
Transfer Characteristics
Axis Title
Axis Title
Ciss
0.005
0.004
0.003
0.002
0.001
0
10000
1000
100
2500
2000
1500
1000
500
10000
1000
100
VGS = 4.5 V
Coss
VGS = 10 V
Crss
10
0
10
20
40
60
80
100
0
5
10
15
20
25
30
ID - Drain Current (A)
2nd line
VDS - Drain-to-Source Voltage (V)
2nd line
On-Resistance vs. Drain Current
Capacitance
Axis Title
Axis Title
10
8
10000
1000
100
1.6
1.4
1.2
1.0
0.8
0.6
10000
1000
100
ID = 10 A
ID = 10 A
VDS = 15 V
VGS = 10 V
6
VDS = 7.5 V
VGS = 4.5 V
4
VDS = 24 V
2
0
10
10
5
10
15
20
25
-50 -25
0
25
50
75 100 125 150
Qg - Total Gate Charge (nC)
2nd line
TJ - Junction Temperature (°C)
2nd line
Gate Charge
On-Resistance vs. Junction Temperature
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
3
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiRA10BDP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
ID = 10 A
100
10
1
10000
1000
100
0.010
0.008
0.006
0.004
0.002
0
10000
1000
TJ = 150 °C
TJ = 25 °C
TJ = 125 °C
100
TJ = 25 °C
0.1
10
10
0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
6
8
10
VSD - Source-to-Drain Voltage (V)
2nd line
VGS - Gate-to-Source Voltage (V)
2nd line
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Axis Title
Axis Title
1.8
1.6
1.4
1.2
1.0
0.8
10000
1000
100
100
80
60
40
20
0
10000
1000
100
10
ID = 250 μA
10
-50 -25
0
25
50
75 100 125 150
0.001 0.01
0.1
1
10
100
1000
TJ - Temperature (°C)
2nd line
Time (s)
2nd line
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
Axis Title
1000
100
10
10000
(1)
I
DM Limited
Limited by RDS(on)
I
D(ON) Limited
1000
100
10
100 μs
1 ms
10 ms
100 ms
1
1 s
10 s
DC
0.1
TA = 25 °C
Single pulse
BVdss Limited
0.01
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
> minimum VGS at which RDS(on) is specified
(1)
V
GS
Safe Operating Area
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
4
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiRA10BDP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
Axis Title
100
80
60
40
20
0
10000
1000
100
60
50
40
30
20
10
0
10000
1000
100
Package limited
10
10
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TC - Case Temperature (°C)
2nd line
TC - Case Temperature (°C)
2nd line
Current Derating a
Power, Junction-to-Case
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiRA10BDP
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Axis Title
1
10000
1000
100
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.01
0.0001
10
1000
0.001
0.1
1
10
100
Square Wave Pulse Duration (s)
2nd line
Normalized Thermal Transient Impedance, Junction-to-Ambient
Axis Title
1
10000
1000
100
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001
10
0.001
0.01
0.1
Square Wave Pulse Duration (s)
2nd line
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?76396.
S18-0315-Rev. A, 19-Mar-18
Document Number: 76396
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8, (Option B)
A
D2
D
A1
C
D1
D4
8
7
6
5
5
6
7
8
H
E3
E2
E1
E
W
K
L
1
2
3
4
4
3
2
1
e
b
Top view
Side view
Bottom view
Notes:
1. Inch will govern
2
Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
MILLIMETERS
DIM.
INCHES
NOM.
0.039
MIN.
0.90
0.00
0.35
0.23
5.00
4.75
4.11
0.515
5.95
5.60
3.59
3.25
NOM.
1.00
MAX.
1.10
0.05
0.50
0.33
5.30
5.05
4.31
0.575
6.25
5.90
3.79
3.35
MIN.
0.035
0.000
0.014
0.009
0.197
0.187
0.162
0.020
0.234
0.220
0.141
0.128
MAX.
0.043
0.002
0.020
0.013
0.209
0.199
0.170
0.023
0.246
0.232
0.149
0.132
A
A1
b
0.01
0.000
0.40
0.016
c
0.28
0.011
D
5.15
0.203
D1
D2
D4
E
4.90
0.193
4.21
0.166
0.545
6.10
0.021
0.240
E1
E2
E3
e
5.75
0.226
3.69
0.145
3.30
0.130
1.27 BSC
1.20 typ.
0.65
0.050 BSC
0.047 typ.
0.026
K
H
0.55
0.51
0.75
0.71
0.022
0.020
0.030
0.028
L
0.56
0.022
θ
12°
12°
W
0.21
0.26
0.31
0.008
0.010
0.012
ECN: S21-0002-Rev. B, 18-Jan-2021
DWG: 6068
Revison: 18-Jan-2021
Document Number: 76657
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VISHAY SILICONIX
www.vishay.com
Power MOSFETs
Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
by Wharton McDaniel
PowerPAK SO-8 SINGLE MOUNTING
MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.
Standard SO-8
PowerPAK SO-8
Fig. 2
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index
of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in2 to 0.5 in2 of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.
Fig. 1 PowerPAK 1212 Devices
Revision: 16-Mai-13
Document Number: 71622
1
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
For
the
lead
(Pb)-free
solder
profile,
see
PowerPAK SO-8 DUAL
www.vishay.com/doc?73257.
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
Fig. 3 Solder Reflow Temperature Profile
Ramp-Up Rate
+ 3 °C /s max.
120 s max.
REFLOW SOLDERING
Temperature at 150 - 200 °C
Temperature Above 217 °C
Maximum Temperature
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
60 - 150 s
255 + 5/- 0 °C
reflow as
a
test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
Time at Maximum
Temperature
30 s
Ramp-Down Rate
+ 6 °C/s max.
30 s
260 °C
3 °C(max)
6 °C/s (max.)
217 °C
150 - 200 °C
150 s (max.)
60 s (min.)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Fig. 4 Solder Reflow Temperatures and Time Durations
Revision: 16-Mai-13
Document Number: 71622
2
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
THERMAL PERFORMANCE
Introduction
Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.
A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, RthJC, or the
junction-to-foot thermal resistance, RthJF This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.
TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE
Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
PowerPAK
SO-8
Standard
SO-8
DPAK
Thermal
Resistance RthJC
1.2 °C/W
1 °C/W
16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.
additional
thermal
performance
improvement.
A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.
R
th
vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
56
51
46
41
36
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
60
50
40
Si4874DY
30
100 %
Si7446DP
0 %
20
50 %
10
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq in)
0
Fig. 6 Spreading Copper Junction-to-Ambient Performance
0.0001
0.01
1
10000
100
Pulse Duration (sec)
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path
Revision: 16-Mai-13
Document Number: 71622
3
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note AN821
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
Suppose each device is dissipating 2.7 W. Using the
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on RDS(on) whereas a
In any design, one must take into account the change in
MOSFET RDS(on) with temperature (figure 7).
On-Resistance vs. Junction Temperature
1.8
43 °C difference has a significant effect on RDS(on)
.
V
= 10 V
= 23 A
GS
1.6
1.4
1.2
1.0
0.8
0.6
I
D
Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep rDS(on) low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
-50
-25
0
25
50
75
100 125 150
T
J
- Junction Temperature (°C)
Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.
PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
PowerPAK SO-8
Standard SO-8
107 °C
148 °C
0.8 °C/W
PC Board at 105 °C
16 C/W
Fig. 8 Temperature of Devices on a PC Board
Revision: 16-Mai-13
Document Number: 71622
4
For technical questions, contact: powermosfettechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.260
(6.61)
0.150
(3.81)
0.024
(0.61)
0.026
(0.66)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72599
Revision: 21-Jan-08
www.vishay.com
15
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