SI9181DQ-30-T1-E3 [VISHAY]
Micropower 350-mA CMOS LDO Regulator With Error Flag/Power-On-Reset; 微功耗350 mA的CMOS LDO稳压器，错误标记/上电复位
| 型号： | SI9181DQ-30-T1-E3 |
| 厂家： | 
VISHAY |
| 描述： | Micropower 350-mA CMOS LDO Regulator With Error Flag/Power-On-Reset |
| 文件： | 总10页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9181
Vishay Siliconix
Micropower 350-mA CMOS LDO Regulator
With Error Flag/Power-On-Reset
FEATURES
D Low 150-mV Dropout at 350-mA Load
D Guaranteed 350-mA Output Current
D 600-mA Peak Output Current Capability
D Uses Low ESR Ceramic Output Capacitor
D Fast Load and Line Transient Response
D Fixed 1.5-V, 1.8-V, 2.0-V, 2.5-V, 2.8-V, 2.85-V, 2.9 V,
3.0-V, 3.3-V, 5.0-V, or Adjustable Output Voltage
Options
D Other Output Voltages Available by Special Order
APPLICATIONS
D Only 100-mV(rms) Noise With Noise Bypass
Capacitor
D Cellular Phones
D 1-mA Maximum Shutdown Current
D Laptop and Palm Computers
D PDA, Digital Still Cameras
D Built-in Short Circuit and Thermal Protection
D Out-Of-Regulation Error Flag (Power Good or POR)
DESCRIPTION
The Si9181 is a 350-mA CMOS LDO (low dropout) voltage
regulator. The device features ultra low ground current and
dropout voltage to prolong battery life in portable electronics.
The Si9181 offers line/load transient response and ripple
rejection superior to that of bipolar or BiCMOS LDO regulators.
The device is designed to maintain regulation while delivering
600-mA peak current. This is useful for systems that have high
surge current upon turn-on. The Si9181 is designed to drive
the lower cost ceramic, as well as tantalum, output capacitors.
The device is guaranteed stable from maximum load current
down to 0-mA load. In addition, an external noise bypass
capacitor connected to the device’s CNOISE pin will lower the
LDO’s output noise for low noise applications.
The Si9181 also includes an out-of-regulation error flag. When
the output voltage is 5% below its nominal output voltage, the
error flag output goes low. If a capacitor is connected to the
device’s delay pin, the error flag output pin will generate a
delayed power-on-reset signal.
The Si9181 is available in both standard and lead (Pb)-free
packages.
TYPICAL APPLICATIONS CIRCUITS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
C
C
SD
SD
NOISE
NOISE
DELAY
ERROR
DELAY
ERROR
GND SENSE/ADJ
GND SENSE/ADJ
V
OUT
V
IN
V
V
IN
V
OUT
V
IN
V
IN
OUT
V
OUT
2.2 mF
GND
2.2 mF
2.2 mF
GND
2.2 mF
Si9181
Si9181
FIGURE 1. Fixed Output
FIGURE 2. Adjustable Output
1
2
3
4
8
7
6
5
SD
ON/OFF
C
NOISE
DELAY
ERROR
POR
0.1 mF
0.1 mF
1 MW
GND SENSE/ADJ
V
OUT
V
IN
V
OUT
V
IN
2.2 mF
2.2 mF
Si9181
GND
FIGURE 3. Low Noise, Full Features Application
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
1
Si9181
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
a
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Power Dissipation (Package)
8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 mW
IN
SD Input Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
IN
SD
Output Current, I
Output Voltage, V
Maximum Junction Temperature, T
Storage Temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
Thermal Impedance (Q
)
JA
OUT
b
8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120_C/W
. . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
OUT
O(nom)
Notes
. . . . . . . . . . . . . . . . . . . . . . . 150_C
J(max)
a. Device mounted with all leads soldered or welded to PC board.
. . . . . . . . . . . . . . . . . . . . . . . . . . −55_C to 150_C
STG
b. Derate 8.3 mW/_C above T = 25_C
A
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V
Operating Ambient Temperature, T . . . . . . . . . . . . . . . . . . . . −40_C to 85_C
IN
A
Output Voltage, V
(Adjustable Version) . . . . . . . . . . . . . . . . . . 1.5 V to 5 V
Operating Junction Temperature, T . . . . . . . . . . . . . . . . . . . −40_C to 125_C
OUT
J
SD Input Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
SD
IN
C
IN
= 2.2 mF, C
= 2.2 mF (ceramic, X5R or X7R type) , C = 0.1 mF (ceramic)
NOISE
OUT
C
OUT
Range = 1 mF to 10 mF ("10%, x5R or x7R type)
C
IN
w C
OUT
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
−40 to 85_C
V
IN
= V
+ 1 V, I
= 1 mA
OUT(nom)
OUT
C
IN
= 2.2 mF, C = 2.2 mF, V = 1.5 V
OUT SD
Parameter
Symbol
Tempa
Minb
Typc
Maxb
Unit
Output Voltage Range
Adjustable Version
1 mA v I v 350 mA
Full
Room
Full
1.5
5
V
−1.5
1.5
V
OUT
Output Voltage Accuracy
(Fixed Versions)
% V
OUT
O(nom)
−2.5
2.5
Room
Full
1.191
1.179
1.215
1.239
1.251
Feedback Voltage (ADJ Version)
V
ADJ
V
Line Regulation
(Except 5-V Version)
From V = V
+ 1 V
IN
OUT(nom)
Full
−0.18
0.18
to V
+ 2 V
OUT(nom)
DV
100
Line Regulation (5-V Version)
Line Regulation (ADJ Version)
From V = 5.5 V to 6 V
Full
Full
Full
−0.18
−0.18
−0.18
0.18
0.18
0.18
OUT
IN
%/V
V
V
OUT(nom)
IN
V
= 1.5 V, From V = 2.5 V to 3.5 V
IN
OUT
V
OUT
= 5 V, From V = 5.5 V to 6 V
IN
I
= 10 mA
Room
Room
Room
Full
5
20
OUT
I
= 200 mA
85
180
400
550
250
425
575
OUT
d
Dropout Voltage
(@V
w 2 V)
OUT
150
I
I
= 350 mA
= 200 mA
OUT
V
IN
− V
mV
OUT
Room
Room
Full
170
290
OUT
d
Dropout Voltage
(@V t 2 V, V w 2 V)
OUT
IN
I
= 350 mA
OUT
I
= 0 mA
Room
Room
Full
150
OUT
1000
I
I
= 200 mA
= 350 mA
OUT
1500
2800
Ground Pin Current
I
mA
GND
Room
Full
1500
OUT
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
2
Si9181
Vishay Siliconix
SPECIFICATIONS
Parameter
Test Conditions
Unless Otherwise Specified
Limits
−40 to 85_C
V
= V
+ 1 V, I
= 1 mA
IN
OUT(nom)
OUT
Tempa
Minb
Typc
Maxb
Unit
C
= 2.2 mF, C
= 2.2 mF, V = 1.5 V
Symbol
IN
OUT
SD
Shutdown Supply Current
ADJ Pin Current
I
V
= 0 V
Room
Room
Room
Room
Room
Room
Room
Room
0.1
5
1
mA
nA
IN(off)
SD
I
ADJ = 1.2 V
w 0.95 x V , t = 2 ms
OUT(nom) pw
100
ADJ
Peak Output Current
I
V
600
mA
O(peak)
OUT
w/o C
200
100
60
NOISE
BW = 50 Hz to 100 kHz
Output Noise Voltage
e
N
mV (rms)
I
I
= 150 mA
OUT
C
= 0.1 mF
NOISE
f = 1 kHz
f = 10 kHz
60
Ripple Rejection
DV
/DV
= 150 mA
dB
OUT
IN
OUT
f = 100 kHz
40
V
: V
+ 1 V to V
+ 2 V
IN
OUT(nom)
OUT(nom)
Dynamic Line Regulation
Dynamic Load Regulation
DV
Room
10
O(line)
t /t = 5 ms, I = 350 mA
OUT
R
F
mV
DV
O(load)
I
: 1 mA to 150 mA, t /t = 2 ms
Room
Room
Room
30
5
OUT
R F
w/o C
Cap
ms
NOISE
V
IN
= 4.3 V
V
OUT
Turn-On-Time
t
ON
V
OUT
= 3.3 V
C
= 0.1 mF
2
mS
NOISE
Thermal Shutdown
Thermal Shutdown Junction Temp
Thermal Hysteresis
t
Room
Room
Room
165
20
J(s/d)
_C
t
HYST
Short Circuit Current
I
V
OUT
= 0 V
800
mA
SC
Shutdown Input
V
High = Regulator ON (Rising)
Low = Regulator OFF (Falling)
Full
Full
1.5
V
IN
IH
SD Input Voltage
V
V
0.4
IL
I
V
= 0 V, Regulator OFF
= 6 V, Regulator ON
Room
Room
Full
0.01
1.0
IH
SD
e
SD Input Current
mA
I
V
SD
IL
Shutdown Hysteresis
V
100
mV
HYST
Error Output
Output High Leakage
I
ERROR = V
Full
Full
0.01
2
mA
OFF
OUT(nom)
g
Output Low Voltage
V
I
= 2 mA
0.4
OL
SINK
f, h
Power_Good Trip Threshold
(Rising)
0.93 x
OUT
0.95 x
OUT
0.97 x
OUT
V
TH
Full
V
V
V
V
2% x
OUT
f
Hysteresis
V
Room
Room
HYST
V
Delay Pin Current Source
I
1.2
2.2
3.0
mA
DELAY
Notes
a. Room = 25_C, Full = −40 to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at V
w 2 V are measured at
OUT
V
= 3.3 V, while typical values for dropout voltage at V
< 2 V are measured at V
= 1.8 V.
OUT
OUT
OUT
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V does not not drop below 2.0 V.
IN
e. The device’s shutdown pin includes a typical 6-MW internal pull-down resistor connected to ground.
f.
V
OUT
is defined as the output voltage of the DUT at 1 mA.
g. The Error Output (Low) function is guaranteed from V
= 2.0 V to V
= 5.0 V.
OUT
OUT
h. The Power_Good trip threshold function is guaranteed from V
= 1.5 V to V
= 5.0 V and V w 2.0 V.
OUT
OUT IN
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
3
Si9181
Vishay Siliconix
TIMING WAVEFORMS
V
IN
t
ON
V
NOM
0.95 V
NOM
V
OUT
ERROR
t
DELAY
FIGURE 4. Timing Diagram for Power-Up
PIN CONFIGURATION
TSSOP-8
C
1
2
3
4
8
7
6
5
SD
NOISE
DELAY
GND
ERROR
SENSE or ADJ
V
IN
V
OUT
Top View
PIN DESCRIPTION
Pin Number
Name
Function
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
1
C
NOISE
Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin 7) output.
Refer to Figure 4.
2
DELAY
GND
3
4
5
Ground pin. Local ground for C
and C
.
NOISE
OUT
V
IN
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Output voltage. Connect C between this pin and ground.
V
OUT
OUT
For fixed output voltage versions, this pin should be connected to V
(Pin 5). For adjustable output voltage version,
OUT
6
SENSE or ADJ
this voltage feedback pin sets the output voltage via an external resistor divider.
This open drain output is an error flag output which goes low when V drops 5% below its nominal voltage. This pin
OUT
7
8
ERROR
SD
also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V if unused.
IN
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
4
Si9181
Vishay Siliconix
ORDERING INFORMATION
Lead (Pb)-Free
Part Number
Part Number
Marking Voltage Temperature Range
Package
Si9181DQ-15-T1
Si9181DQ-18-T1
Si9181DQ-20-T1
Si9181DQ-25-T1
Si9181DQ-28-T1
Si9181DQ-285-T1
Si9181DQ-29-T1
Si9181DQ-30-T1
Si9181DQ-33-T1
Si9181DQ-50-T1
Si9181DQ-AD-T1
Si9181DQ-15-T1—E3
Si9181DQ-18-T1—E3
Si9181DQ-20-T1—E3
Si9181DQ-25-T1—E3
Si9181DQ-28-T1—E3
Si9181DQ-285-T1—E3
Si9181DQ-29-T1—E3
Si9181DQ-30-T1—E3
Si9181DQ-33-T1—E3
Si9181DQ-50-T1—E3
Si9181DQ-AD-T1—E3
115
118
120
125
128
285
129
130
133
150
1AD
1.5 V
1.8 V
2.0 V
2.5 V
2.8 V
2.85 V
2.9 V
−40 to 85_C
TSSOP-8
3.0 V
3.3 V
5.0 V
Adjustable
* Additional voltage options are available.
Eval Kit
Temperature Range
Board Type
Si9181DB
−40 to 85_C
Surface Mount
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
Dropout Voltage vs. Load Current
Dropout Characteristic
300
250
200
150
100
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
OUT
= 3.3 V
R
LOAD
= 16.5 W
0
0
100
200
300
(mA)
400
500
600
0
1
2
3
4
5
6
I
V
(V)
LOAD
IN
Dropout Voltage vs. Temperature
Dropout Voltage vs. V
OUT
300
250
200
150
100
50
200
175
150
125
100
75
I
I
= 350 mA
OUT
V
= 3.3 V
OUT
= 300 mA
OUT
I
= 350 mA
OUT
I
= 300 mA
OUT
50
25
I
= 10 mA
OUT
I
I
= 10 mA
= 0 mA
OUT
0
0
OUT
−50 −25
0
25
50
75
100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Junction Temperature (_C)
V
OUT
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
5
Si9181
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
Normalized Output Voltage vs. Load Current
Normalized V
vs. Temperature
OUT
0.30
0.15
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
I
= 0 mA
OUT
0.00
I
= 100 mA
OUT
−0.15
−0.30
−0.45
−0.60
−0.75
I
= 200 mA
OUT
I
= 300 mA
OUT
I
= 350 mA
OUT
0
50
100 150 200 250 300 350 400
Load Current (mA)
−40 −20
0
20
40
60
80 100 120 140
Junction Temperature (_C)
GND Current vs. Load Current
No Load GND Pin Current vs. Input Voltage
0.0
−0.3
−0.6
−0.9
−1.2
−1.5
300
250
200
150
100
50
V
= 5 V
OUT
85_C
25_C
25_C
−40_C
0
0
50
100
150
200
250
300
350
0
1
2
3
4
5
6
7
Load Current (mA)
Input Voltage (V)
Power Supply Rejection
GND Pin Current vs. Temperature and Load
0
−20
−40
−60
−80
2000
1500
1000
500
0
V
OUT
= 5 V
C
C
LOAD
= 10 mF
IN
OUT
= 2.2 mF
I
= 350 mA
= 200 mA
OUT
OUT
I
= 150 mA
I
I
= 0 mA
OUT
−40 −20
0
20
40
60
80 100 120 140
10
100
1000
10000
100000 1000000
Frequency (Hz)
Junction Temperature (_C)
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
6
Si9181
Vishay Siliconix
TYPICAL WAVEFORMS
Load Transient Response-1
Load Transient Response-2
V
OUT
10 mV/div
V
OUT
10 mV/div
I
LOAD
100 mA/div
I
LOAD
100 mA/div
5.00 ms/div
5.00 ms/div
V
= 3.3 V
OUT
OUT
OUT
OUT
C
= 2.2 mF
C
= 2.2 mF
I
t
= 1 to 150 mA
= 2 msec
I
t
= 150 to 1 mA
LOAD
rise
LOAD
= 2 msec
fall
Load Transient Response-3
Load Transient Response-4
1
1
10
5.00 ms/div
V
= 3.3 V
V
= 3.3 V
OUT
OUT
OUT
OUT
C
= 1.0 mF
C
= 1.0 mF
I
t
= 1 to 150 mA
= 2 msec
I
t
= 150 to 1 mA
LOAD
rise
LOAD
= 2 msec
fall
LineTransient Response-1
LineTransient Respons-2
V
IN
2 V/div
V
V
OUT
10 mV/div
OUT
10 mV/div
5.00 ms/div
5.00 ms/div
V
V
C
C
= 4.3 to 5.3 V
V
OUT
C
C
= 5.3 to 4.3 V
INSTEP
INSTEP
OUT
OUT
IN
= 3.3 V
V
= 3.3 V
= 2.2 mF
= 2.2 mF
OUT
= 10 mF
= 10 mF
IN
I
t
= 350 mA
I
t
= 350 mA
LOAD
rise
LOAD
= 5 msec
fall
= 5 msec
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
7
Si9181
Vishay Siliconix
TYPICAL WAVEFORMS
Turn-On Sequence
Turn-Off Sequence
V
2 V/div
2 V/div
IN
V
OUT
C
delay
2 V/div
ERROR 2 V/div
V
C
C
V
C
C
IN
IN
= 3.3 V
= 3.3 V
OUT
delay
OUT
delay
= 0.1 mF
= 0.1 mF
= 0.1 mF
= 0.1 mF
NOISE
NOISE
I
= 350 mA
I
= 350 mA
LOAD
LOAD
Output Noise
Noise Spectrum
10.0
Ǹ
mVń Hz
500 mV/div
0.01
100 Hz
1 ms/div
1 MHz
V
OUT
C
V
V
= 4.1 V
IN
IN
OUT
C
= 3.3 V
= 3.3 V/10 mA
= 0.1 mF
OUT
I
= 150 mA
NOISE
= 0.1 mF
NOISE
BW = 10 Hz to 1 MHz
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
8
Si9181
Vishay Siliconix
BLOCK DIAGRAMS
Switches shown for device in normal operating mode (SD = HIGH)
6
SENSE
1
C
NOISE
4
V
IN
C
IN
2.2 mF
8
SD
ON
+
−
RFB2
RFB1
OFF
To V
5
2
IN
V
OUT
60 mV
6 MW
2 mA
C
OUT
2.2 mF
+
+
R
EXT
−
C
DELAY
0.1 mF
ERROR
7
+
−
1.215 V
+
V
REF
−
3
GND
FIGURE 5. 350-mA CMOS LDO Regulator (Fixed Output)
6
ADJ
1
C
NOISE
4
8
V
IN
C
IN
2.2 mF
R
R
2
V
ADJ
SD
ON
1
+
OFF
−
To V
5
2
IN
V
OUT
6 MW
2 mA
C
OUT
60 mV
2.2 mF
+
+
R
EXT
−
C
DELAY
0.1 mF
ERROR
7
+
−
1.215 V
+
V
REF
−
3
GND
FIGURE 6. 350-mA CMOS LDO Regulator (Adjustable Output)
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
www.vishay.com
9
Si9181
Vishay Siliconix
DETAILED DESCRIPTION
The Si9181 is a low drop out, low quiescent current, and very
linear regulator family with very fast transient response. It is
primarily designed for battery powered applications where
battery run time is at a premium. The low quiescent current
allows extended standby time while low drop out voltage
enables the system to fully utilize battery power before
recharge. The Si9181 is a very fast regulator with bandwidth
exceeding 50 kHz while maintaining low quiescent current at
light load conditions. With this bandwidth, the Si9181 is the
fastest LDO available today. The Si9181 is stable with any
output capacitor type from 1 mF to 10.0 mF. However, X5R or
X7R ceramic capacitors are recommended for best output
noise and transient performance.
The formula below calculates the value of R1, given the
desired output voltage and the R2 value,
ǒ
ǓR2
VOUT * VADJ
R1 +
VADJ
(1)
V
ADJ
is nominally 1.215 V.
SHUTDOWN (SD)
SD controls the turning on and off of the Si9181. VOUT is
guaranteed to be on when the SD pin voltage equals or is
greater than 1.5 V. VOUT is guaranteed to be off when theSD
pin voltage equals or is less than 0.4 V. During shutdown
mode, the Si9181 will draw less than 2-mA current from the
source. To automatically turn on VOUT whenever the input is
applied, tie the SD pin to VIN.
VIN
VIN is the input supply pin. The bypass capacitor for this pin
is not critical as long as the input supply has low enough source
impedance. For practical circuits, a 1.0-mF or larger ceramic
capacitor is recommended. When the source impedance is
not low enough and/or the source is several inches from the
Si9181, then a larger input bypass capacitor is needed. It is
required that the equivalent impedance (source impedance,
wire, and trace impedance in parallel with input bypass
capacitor impedance) must be smaller than the input
impedance of the Si9181 for stable operation. When the
source impedance, wire, and trace impedance are unknown,
it is recommended that an input bypass capacitor be used of
a value that is equal to or greater than the output capacitor.
ERROR
ERROR is an open drain output that goes low when VOUT is
less than 5% of its normal value. As with any open drain output,
an external pull up resistor is needed. When a capacitor is
connected from DELAY to GROUND, the error signal transition
from low to high is delayed (see Delay section). This delayed
error signal can be used as the power-on reset signal for the
application system. (Refer to Figure 4.)
VOUT
The ERROR pin is disconnected if not used.
VOUT is the output voltage of the regulator. Connect a bypass
capacitor from VOUT to ground. The output capacitor can be
any value from 1.0 mF to 10.0 mF. A ceramic capacitor with
X5R or X7R dielectric type is recommended for best output
noise, line transient, and load transient performance.
DELAY
A capacitor from DELAY to GROUND sets the time delay for
ERROR going from low to high state. The time delay can be
calculated using the following formula:
GND
ǒ
Ǔ
VADJ Cdelay
Ground is the common ground connection for VIN and VOUT
It is also the local ground connection for CNOISE, DELAY,
SENSE or ADJ, and SD.
.
(2)
Tdelay
+
Idelay
SENSE or ADJ
The DELAY pin should be an open circuit if not used.
SENSE is used to sense the output voltage. Connect SENSE
to VOUT for the fixed voltage version. For the adjustable output
version, use a resistor divider R1 and R2, connect R1 from
VOUT to ADJ and R2 from ADJ to ground. R2 should be in the
25-kW to 150-kW range for low power consumption, while
maintaining adequate noise immunity.
CNOISE
For low noise application, connect a high frequency ceramic
capacitor from CNOISE to ground. A 0.01-mF or a 0.1-mF X5R
or X7R is recommended.
Document Number: 71119
S-40694—Rev. D, 19-Apr-04
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