SI6410DQ [VISHAY]
N-Channel 30-V (D-S) MOSFET; N通道30 -V （D -S ）的MOSFET
| 型号： | SI6410DQ |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 30-V (D-S) MOSFET |
| 文件： | 总10页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si6410DQ
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free
VDS (V)
RDS(on) (Ω)
ID (A)
7.8
• TrenchFET® Power MOSFETs
0.014 at VGS = 10 V
0.021 at VGS = 4.5 V
30
RoHS
6.3
COMPLIANT
D
TSSOP-8
* Source Pins 2, 3, 6 and 7
must be tied common.
G
D
S
S
G
D
S
S
D
1
2
3
4
8
7
6
5
Si6410DQ
S*
Top View
Ordering Information: Si6410DQ-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
Limit
30
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
V
VGS
20
TA = 25 °C
TA = 70 °C
7.8
6.2
Continuous Drain Current (TJ = 150 °C)a
ID
A
IDM
IS
Pulsed Drain Current
30
Continuous Source Current (Diode Conduction)a
1.5
TA = 25 °C
TA = 70 °C
1.5
Maximum Power Dissipationa
PD
W
1.0
TJ, Tstg
Operating Junction and Storage Temperature Range
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Limit
Unit
Maximum Junction-to-Ambienta
RthJA
83
°C/W
Notes:
a. Surface Mounted on FR4 board, t ≤ 10 s.
For SPICE model information via the Worldwide Web: http://www.vishay.com/www/product/spice.htm.
Document Number: 70661
S-80682-Rev. D, 31-Mar-08
www.vishay.com
1
Si6410DQ
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VDS = VGS, ID = 250 µA
Gate Threshold Voltage
1
V
VDS = 0 V, VGS
=
20 V
Gate-Body Leakage
100
1
nA
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS = 5 V, VGS = 10 V
IDSS
ID(on)
Zero Gate Voltage Drain Current
µA
A
25
On-State Drain Currenta
20
VGS = 10 V, ID = 7.8 A
0.011
0.015
27
0.014
0.021
Drain-Source On-State Resistancea
RDS(on)
Ω
V
GS = 4.5 V, ID = 5 A
Forward Transconductancea
Diode Forward Voltagea
gfs
VDS = 15 V, ID = 7.8 A
IS = 1.5 A, VGS = 0 V
S
V
VSD
0.7
1.1
Dynamicb
Qg
Qgt
Qgs
Qgd
td(on)
tr
VDS = 15 V, VGS = 5 V, ID = 7.8 A
Gate Charge
22
43
9.0
7.0
15
10
70
20
50
33
60
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
nC
ns
V
DS = 15 V, VGS = 10 V, ID = 7.8 A
30
20
V
DD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
td(off)
tf
Turn-Off Delay Time
Fall Time
120
50
trr
IF = 1.5 A, di/dt = 100 A/µs
Source-Drain Reverse Recovery Time
80
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70661
S-80682-Rev. D, 31-Mar-08
Si6410DQ
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C unless noted
30
30
24
18
12
6
V
GS
= 10 V thru 4 V
24
18
12
6
T
C
= 125°C
3 V
25 °C
2
- 55 °C
0
0
0
2
4
6
8
10
0
1
3
4
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.030
4200
3500
2800
2100
1400
700
C
iss
0.024
0.018
0.012
0.006
0
V
GS
= 4.5 V
V
GS
= 10 V
C
oss
C
rss
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
2.0
1.6
1.2
0.8
0.4
0
10
8
V
I
= 10 V
= 7.8 A
V
I
= 15 V
= 7.8 A
GS
D
DS
D
6
4
2
0
- 50 - 25
0
25
50
75
100 125 150
0
9
18
27
36
45
T - Junction Temperature (°C)
J
Q
g
- Total Gate Charge (nC)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 70661
S-80682-Rev. D, 31-Mar-08
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3
Si6410DQ
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C unless noted
0.10
0.08
0.06
0.04
0.02
0
30
20
I
D
= 7.8 A
T
J
= 150 °C
10
T
= 25 °C
J
1
0
2
4
6
8
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.8
0.6
60
50
40
30
20
10
0
0.4
0.2
I
= 250 µA
D
0.0
- 0.2
- 0.4
- 0.6
- 0.8
- 1.0
- 1.2
- 50 - 25
0
25
50
75
100 125 150
0.01
0.10
1.00
Time (s)
10.00
T - Temperature (°C)
J
Threshold Voltage
Single Pulse Power
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
P
DM
0.1
t
1
0.05
t
2
t
t
1
1. Duty Cycle, D =
2
2. Per Unit Base = R
= 83 °C/W
0.02
thJA
(t)
3. T
T
= P
Z
JM
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
30
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?70661.
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Document Number: 70661
S-80682-Rev. D, 31-Mar-08
Package Information
Vishay Siliconix
TSSOP: 8ĆLEAD
JEDEC Part Number: MO-153
MILLIMETERS
Dim
A
A1
A2
B
C
D
E
E1
e
Min
–
Nom
–
Max
1.20
0.15
1.05
0.30
–
0.05
0.80
0.19
–
0.10
1.00
0.28
0.127
3.00
6.40
4.40
0.65
0.60
1.00
–
2.90
6.20
4.30
–
3.10
6.60
4.50
–
R 0.10
Corners)
D
e
0.45
0.90
–
0.75
1.10
0.10
6_
E
L
L1
Y
C
L
B
0_
3_
oK1
R 0.10
oK1
(4 Corners)
ECN: S-03946—Rev. G, 09-Jul-01
DWG: 5844
L1
Document Number: 71201
06-Jul-01
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1
AN1001
Vishay Siliconix
LITTLE FOOTR TSSOP-8
The Next Step in Surface-Mount Power MOSFETs
Wharton McDaniel and David Oldham
When Vishay Siliconix introduced its LITTLE FOOT
MOSFETs, it was the first time that power MOSFETs had been
offered in a true surface-mount package, the SOIC. LITTLE
FOOT immediately found a home in new small form factor disk
drives, computers, and cellular phones.
This is the low profile demanded by applications such as
PCMCIA cards.
It reduces the power package to the same height as many
resistors and capacitors in 0805 and 0605 sizes. It also allows
placement on the “passive” side of the PC board.
The new LITTLE FOOT TSSOP-8 power MOSFETs are the
natural evolutionary response to the continuing demands of
many markets for smaller and smaller packages. LITTLE
FOOT TSSOP-8 MOSFETs have a smaller footprint and a
lower profile than LITTLE FOOT SOICs, while maintaining low
rDS(on) and high thermal performance. Vishay Siliconix has
accomplished this by putting one or two high-density MOSFET
die in a standard 8-pin TSSOP package mounted on a custom
leadframe.
The standard pinouts of the LITTLE FOOT TSSOP-8
packages have been changed from the standard established
by LITTLE FOOT. This change minimizes the contribution of
interconnection resistance to rDS(on) and maximizes the
transfer of heat out of the package.
Figure 2 shows the pinouts for a single-die TSSOP. Notice that
both sides of the package have Source and Drain
connections, whereas LITTLE FOOT has the Source and Gate
connections on one side of the package, and the Drain
connections are on the opposite side.
THE TSSOP-8 PACKAGE
LITTLE FOOT TSSOP-8 power MOSFETs require
approximately half the PC board area of an equivalent LITTLE
FOOT device (Figure 1). In addition to the reduction in board
area, the package height has been reduced to 1.1 mm.
Drain
Source
Source
Gate
Drain
Source
Source
Drain
Figure 2. Pinouts for Single Die TSSOP
Figure 3 shows the standard pinouts for a dual-die TSSOP-8.
In this case, the connections for each individual MOSFET
occupy one side.
Top View
Drain 1
Source 1
Source 1
Gate 1
Drain 2
Source 2
Source 2
Gate 2
Side View
Figure 1. An TSSOP-8 Package Next to a SOIC-8 Package
with Views from Both Top and Side
Figure 3. Pinouts for Dual-Die TSSOP
Document Number: 70571
12-Dec-03
www.vishay.com
1
AN1001
Vishay Siliconix
Because the TSSOP has a fine pitch foot print, the pad layout
is somewhat more demanding than the layout of the SOIC.
Careful attention must be paid to silkscreen-to-pad and
soldermask-to-pad clearances. Also, fiduciary marks may be
required. The design and spacing of the pads must be dealt
with carefully. The pads must be sized to hold enough solder
paste to form a good joint, but should not be so large or so
placed as to extend under the body, increasing the potential for
solder bridging. The pad pattern should allow for typical pick
and place errors of 0.25 mm. See Application Note 826,
Recommended Minimum Pad Patterns With Outline
Figure 5.
The actual test is based on dissipating a known amount of
power in the device for a known period of time so the junction
temperature is raised to 150_C. The starting and ending
junction temperatures are determined by measuring the
forward drop of the body diode. The thermal resistance for that
pulse width is defined by the temperature rise of the junction
above ambient and the power of the pulse, DTja/P.
Drawing Access
for
Vishay
Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286), for the recommended
pad pattern for PC board layout.
THERMAL ISSUES
Figure 6 shows the single pulse power curve of the Si6436DQ
laid over the curve of the Si9936DY to give a comparison of the
thermal performance. The die in the two devices have
equivalent die areas, making this a comparison of the
packaging. This comparison shows that the TSSOP package
performs as well as the SOIC out to 150 ms, with long-term
performance being 0.5 W less. Although the thermal
performance is less, LITTLE FOOT TSSOP will operate in a
large percentage of applications that are currently being
served by LITTLE FOOT.
LITTLE FOOT TSSOP MOSFETs have been given thermal
ratings using the same methods used for LITTLE FOOT. The
maximum thermal resistance junction-to-ambient is 83_C/W
for the single die and 125_C/W for dual-die parts. TSSOP relies
on a leadframe similar to LITTLE FOOT to remove heat from
the package. The single- and dual-die leadframes are shown
in Figure 4.
14.0
12.0
10.0
8.0
a) 8-Pin Single-Pad TSSOP
6.0
Si9936
4.0
2.0
0.0
Si6436
1
0.1
10
100
Time (Sec.)
b) 8-Pin Dual-Pad TSSOP
Figure 6. Comparison of Thermal Performance
Figure 4. Leadframe
CONCLUSION
The MOSFETs are characterized using a single pulse power
test. For this test the device mounted on a one-square-inch
piece of copper clad FR-4 PC board, such as those shown in
Figure 5. The single pulse power test determines the
maximum amount of power the part can handle for a given
pulse width and defines the thermal resistance
junction-to-ambient. The test is run for pulse widths ranging
from approximately 10 ms to 100 seconds. The thermal
resistance at 30 seconds is the rated thermal resistance for the
part. This rating was chosen to allow comparison of packages
and leadframes. At longer pulse widths, the PC board thermal
charateristics become dominant, making all parts look the
same.
TSSOP power MOSFETs provide a significant reduction in PC
board footprint and package height, allowing reduction in
board size and application where SOICs will not fit. This is
accomplished using a standard IC package and a custom
leadframe, combining small size with good power handling
capability.
For the TSSOP-8 package outline visit:
http://www.vishay.com/doc?71201
For the SOIC-8 package outline visit:
http://www.vishay.com/doc?71192
Document Number: 70571
12-Dec-03
www.vishay.com
2
AN806
Vishay Siliconix
Mounting LITTLE FOOTR TSSOP-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
The pad patterns with copper spreading for the single-MOSFET
TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2)
show the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of copper
overlies the drain pins. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. These patterns
use all the available area underneath the body for this purpose.
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFET, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET
package footprint. In converting the footprint to the pad set for a
power device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
0.284
7.6
0.032
0.8
0.122
0.026
0.66
3.1
0.018
0.45
0.073
1.78
0.091
1.65
In the case of the TSSOP-8 package, the thermal connections
are very simple. Pins 1, 5, and 8 are the drain of the MOSFET
for a single MOSFET package and are connected together. In
the dual package, pins 1 and 8 are the two drains. For a
small-signal device or integrated circuit, typical connections
would be made with traces that are 0.020 inches wide. Since
the drain pins also provide the thermal connection to the
package, this level of connection is inadequate. The total
cross section of the copper may be adequate to carry the
current required for the application, but it presents a large
thermal impedance. Also, heat spreads in a circular fashion
from the heat source. In this case the drain pins are the heat
sources when looking at heat spread on the PC board.
FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with
Copper Spreading
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
0.284
7.6
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
0.032
0.8
0.026
0.66
0.122
3.1
0.018
0.45
0.073
1.78
0.118
3.54
FIGURE 1. Single MOSFET TSSOP-8 Pad
Pattern with Copper Spreading
Document Number: 70738
17-Dec-03
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1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TSSOP-8
0.092
(2.337)
0.026
(0.660)
0.014
0.012
(0.305)
(0.356)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72611
Revision: 21-Jan-08
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27
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
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Document Number: 91000
Revision: 11-Mar-11
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