DG429DN [VISHAY]
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers; 单8通道/差分4通道可锁存模拟多路复用器
| 型号： | DG429DN |
| 厂家： | 
VISHAY |
| 描述： | Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers |
| 文件： | 总12页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG428/429
Vishay Siliconix
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
FEATURES
BENEFITS
APPLICATIONS
D Low rDS(on): 55 W
D Low Charge Injection: 1 pC
D Improved System Accuracy
D Microprocessor Bus Compatible
D Easily Interfaced
D Data Acquisition Systems
D Automatic Test Equipment
D Avionics and Military Systems
D Communication Systems
D On-Board TTL Compatible
Address Latches
D Reduced Crosstalk
D High Throughput
D High Speed—tTRANS: 160 ns
D Break-Before-Make
D Microprocessor-Controlled
Analog Systems
D Improved Reliability
D Low Power Consumption: 0.3 mW
D Medical Instrumentation
DESCRIPTION
The DG428/DG429 analog multiplexers have on-chip address
and control latches to simplify design in microprocessor based
applications. Break-before-make switching action protects
against momentary crosstalk of adjacent input signals.
several devices. All control inputs, address (Ax) and enable
(EN) are TTL compatible over the full specified operating
temperature range.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximumvoltage
rating is extended to 44 V. Additionally, single supply operation
is also allowed and an epitaxial layer prevents latchup.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
An on channel conducts current equally well in both directions.
In the off state each channel blocks voltages up to the power
supply rails. An enable (EN) function allows the user to reset
the multiplexer/demultiplexer to all switches off for stacking
On-board TTL-compatible address latches simplify the digital
interface design and reduce board space in bus-controlled
systems such as data acquisition systems, process controls,
avionics, and ATE.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG428
DG428
Dual-In-Line
PLCC
WR
RS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
3
2
1
20 19
A
0
A
1
Latches
EN
V–
A
2
EN
V–
4
5
6
7
8
18
A
2
Latches
17 GND
Decoders/Drivers
Decoders/Drivers
GND
V+
V+
S
1
S
2
S
3
16
15
14
S
1
S
5
S
2
S
5
S
6
S
3
S
6
9
10 11 12 13
Top View
S
4
S
7
D
S
8
Top View
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-1
DG428/429
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG429
DG429
Dual-In-Line and SOIC
PLCC
WR
RS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
3
2
1
20 19
A
0
A
1
Latches
EN
V–
GND
V+
EN
V–
4
5
6
7
8
18 GND
Latches
17
16
15
14
V
S
Decoders/Drivers
DD
Decoders/Drivers
1b
S
1a
2a
3a
S
S
S
S
S
1a
2a
3a
1b
2b
3b
S
S
S
S
2b
S
S
S
3b
9
10 11 12 13
Top View
4a
4b
D
a
D
b
Top View
TRUTH TABLE
Ċ
DG429
TRUTH TABLE
Ċ
DG428
Differential 4-Channel Multiplexer
8-Channel Single-Ended Multiplexer
A1 A0 EN WR RS On Switch
A1
A0
EN
X
WR
RS
1
On Switch
A2
Latching
Latching
Maintains previous
switch condition
X
X
Maintains previous
switch condition
X
X
X
X
X
X
X
1
0
Reset
Reset
X
X
X
X
0
None (latches cleared)
X
X
None (latches cleared)
Transparent Operation
Transparent Operation
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
None
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
None
1
2
3
4
1
2
3
4
5
6
7
8
Logic “0” = V v 0.8 V
AL
Logic “1” = V w 2.4 V
AH
X = Don’t Care
ORDERING INFORMATION
Ċ
DG428
ORDERING INFORMATION
Ċ
DG429
Temp Range
Package
Part Number
Temp Range
Package
Part Number
18-Pin Plastic DIP
20-Pin PLCC
DG428DJ
DG428DN
18-Pin Plastic DIP
20-Pin PLCC
DG429DJ
DG429DN
DG429DW
–40 to 85_C
–40 to 85_C
18-Pin Widebody SOIC
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-2
DG428/429
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
b
Voltage Referenced to V–
Power Dissipation (Package)
c
18-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
18-Pin CerDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
d
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
a
f
Digital Inputs , V , V . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or
S
D
f
28-Pin Widebody SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
30 mA, whichever occurs first
Notes:
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
a. Signals on S , D or IN exceeding V+ or V– will be clamped by internal
X
X
X
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/_C above 75_C.
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Storage Temperature
(AK Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C
(DJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C
d. Derate 12 mW/_C above 75_C.
e. Derate 10 mW/_C above 75_C.
f.
Derate 6 mW/_C above 75_C.
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 15 V, V– = –15 V, WR = 0,
f
Parameter
Symbol
Tempb Typc Mind Maxd Mind Maxd Unit
RS = 2.4 V, V = 2.4 V, 0.8 V
IN
Analog Switch
e
Analog Signal Range
V
Full
–15
15
–15
15
V
ANALOG
Drain-Source
On-Resistance
V
= "10 V, V = 0.8 V
I = –1 mA, V = 2.4 V
S AH
Room
Full
55
100
125
100
125
D
AL
r
W
DS(on)
Greatest Change in r
Between Channels
–10 V < V < 10 V
S
DS(on)
Dr
Room
5
%
DS(on)
S(off)
g
I = –1 mA
S
Source Off
Leakage Current
V
S
= "10 V, V = #10 V
Room
Full
"0.03
–0.5
–50
0.5
50
–0.5
–50
0.5
50
D
= 0 V
I
V
EN
Room
Full
"0.07
"0.05
"0.07
"0.05
–1
–100
1
100
–1
–100
1
100
DG428
DG429
DG428
DG429
V
V
V
= "10 V
= #10 V
D
S
EN
Drain Off
Leakage Current
I
D(off)
Room
Full
–1
–50
1
50
–1
–50
1
50
= 0 V
nA
Room
Full
–1
–100
1
100
–1
–100
1
100
V
= V = "10 V
S
D
Drain On
Leakage Current
V
= 2.4 V
= 0.8 V
= 2.4 V
EN
AL
AH
I
D(on)
V
V
Room
Full
–1
–50
1
50
–1
–50
1
50
Digital Control
V
= 2.4 V
= 15 V
Full
Full
0.01
0.01
1
1
1
1
A
Logic Input Current
Input Voltage High
I
AH
V
A
mA
Logic Input Current
Input Voltage Low
V
= 0 V, 2.4 V, V = 0 V
EN A
I
Full
–0.01
8
–1
10
–1
10
AL
RS = 0 V, WR = 0 V
f = 1 MHz
Logic Input Capacitance
C
Room
pF
in
Dynamic Characteristics
Room
Full
150
250
300
250
300
Transition Time
t
See Figure 5
See Figure 4
TRANS
Break-Before-Make Interval
Enable and Write
t
Full
30
90
OPEN
ns
Room
Full
150
225
150
225
t
See Figures 6 and 7
ON(EN,WR)
Turn-On Time
Enable and Reset
Turn-Off Time
Room
Full
55
150
300
150
300
t
See Figures 6 and 8
OFF(EN,RS)
V
C
= 0 V, R
= 1 nF, See Figure 9
= 0 W
GEN
GEN
Charge Injection
Q
Room
Room
1
pC
dB
L
V
EN
= 0 V, R = 300 W, C = 15 pF
L
L
Off Isolation
OIRR
–75
V
S
= 7 V
f = 100 kHz
RMS,
Source Off Capacitance
C
V
= 0 V, V = 0 V, f = 1 MHz
Room
Room
Room
Room
Room
11
40
20
54
34
S(off)
D(off)
S
EN
DG428
Drain Off Capacitance
Drain On Capacitance
C
DG429
DG428
DG429
pF
V
D
= 0 V, V = 0 V
EN
f = 1 MHz
C
D(on)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-3
DG428/429
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 15 V, V– = –15 V, WR = 0, RS = 2.4
f
Parameter
Symbol
Tempb Typc Mind Maxd Mind Maxd Unit
V, V = 2.4 V, 0.8 V
IN
Minimum Input Timing Requirements
Write Pulse Width
t
Full
Full
Full
Full
100
100
10
100
100
10
W
A , EN Data Set Up time
X
t
See Figure 2
S
H
ns
A , EN Data Hold Time
X
t
Reset Pulse Width
t
V
S
= 5 V, See Figure 3
100
100
RS
Power Supplies
Positive Supply Current
Negative Supply Current
I+
I–
Room
Room
20
100
100
mA
V
EN
= 0 V, V = 0, RS = 5 V
A
–0.001
–5
–5
a
SPECIFICATIONS FOR SINGLE SUPPLY
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 12 V, V– = 0 V, WR = 0
f
Parameter
Symbol
Tempb Typc Mind Maxd Mind Maxd Unit
RS = 2.4 V, V = 2.4 V, 0.8 V
IN
Analog Switch
e
Analog Signal Range
V
Full
0
12
0
12
V
ANALOG
Drain-Source
On-Resistance
V = +10 V, V = 0.8 V
D AL
= –500 mA, V = 2.4 V
S AH
r
Room
80
150
150
W
DS(on)
I
0 V < V < 10 V
S
g
r
Match
Dr
Room
5
%
DS(on)
DS(on)
S(off)
I
S
= –1 mA
Source Off
V
S
= 0 V, 10 V, V = 10 V, 0 V
Room
Full
"0.03
–0.5
–50
0.5
50
–0.5
–50
0.5
50
D
= 0 V
I
Leakage Current
V
EN
Room
Full
"0.07
"0.05
"0.07
"0.05
–1
–100
1
100
–1
–100
1
100
DG428
DG429
DG428
DG429
V
= 0 V, 10 V
= 10 V, 0 V
D
Drain Off
Leakage Current
I
V
S
D(off)
D(on)
Room
Full
–1
–50
1
50
–1
–50
1
50
V
EN
= 0 V
nA
Room
Full
–1
–100
1
100
–1
–100
1
100
V
= V = 0 V, 10 V
D
S
Drain On
Leakage Current
V
V
V
= 2.4 V
= 0.8 V
= 2.4 V
EN
AL
AH
I
Room
Full
–1
–50
1
50
–1
–50
1
50
Digital Control
V
= 2.4 V
= 12 V
Full
Full
1
1
1
1
A
Logic Input Current
Input Voltage High
I
AH
V
A
mA
Logic Input Current
Input Voltage Low
V
= 0 V, 2.4 V, V = 0 V
RS = 0 V, WR = 0 V
EN A
I
AL
Full
–1
–1
Dynamic Characteristics
S
1
= 10 V/2 V, S = 2 V/ 10 V
8
Room
Full
160
280
350
280
350
Transition Time
t
TRANS
See Figure 5
Break-Before-Make
Interval
Room
Full
40
110
70
25
10
25
10
t
See Figure 4
OPEN
ns
Enable and Write
Turn-On Time
S
1
=5 V
Room
Full
300
400
300
400
t
ON(EN, WR)
See Figures 6 and 7
Enable and Reset
Turn-Off Time
S
1
=5 V
Room
Full
300
400
300
400
t
OFF(EN, RS)
See Figures 6 and 8
V
C
= 6 V, R = 0 W
= 1 nF, See Figure 9
GEN
GEN
Charge Injection
Off Isolation
Q
Room
Room
4
pC
dB
L
V
EN
= 0 V, R = 300 W, C = 15 pF
L
L
OIRR
–75
V
S
= 7 V
f = 100 kHz
RMS,
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-4
DG428/429
Vishay Siliconix
a
SPECIFICATIONS FOR SINGLE SUPPLY
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 12 V, V– = 0 V, WR = 0
f
Parameter
Symbol
Tempb Typc Mind Maxd Mind Maxd Unit
RS = 2.4 V, V = 2.4 V, 0.8 V
IN
Minimum Input Timing Requirements
Write Pulse Width
t
Full
Full
100
100
100
100
W
A , EN
X
Data Set Up Time
t
S
See Figure 2
ns
A , EN
X
Data Hold Time
t
Full
Full
10
10
H
Reset Pulse Width
t
V
S
= 5 V, See Figure 3
100
100
RS
Power Supplies
Positive Supply Current
I+
V
EN
= 0 V, V = 0, RS = 5 V
Room
20
100
100
mA
A
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f.
V
IN
= input voltage to perform proper function.
r
MAX – r
MIN
DS(on)
DS(on)
g.
Dr
+
x 100%
ǒ
Ǔ
DS(on)
r
AVE
DS(on)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-5
DG428/429
Vishay Siliconix
TYPICAL CHARACTERISTICS (_2C5 UNLESS NOTED)
r
vs. V and Temperature
r
vs. V and Supply Voltage
DS
D
DS(on)
D
100
90
80
70
60
50
40
30
20
10
0
140
120
100
"5 V
125_C
85_C
"10 V
80
60
"12 V
"15 V
"8 V
25_C
–55_C
40
"20 V
–40_C
20
0
V+ = 15 V
V– = –15 V
–20 –16 –12 –8 –4
0
4
8
12 16 20
–15
–10
–5
0
5
10
15
V
D
– Drain Voltage (V)
V
D
– Drain Voltage (V)
Single Supply r
vs. V and Supply
I
I Leakage Currents vs. Analog Voltage
S
DS(on)
D
D,
200
160
120
80
40
30
V+ = 15 V
V– = –15 V
V– = 0 V
V
V
= –V for I
S
D
D D(off)
V+ = 7.5 V
= V for I
S
D(on)
20
10 V
10
I
S(off)
12 V
0
15 V
20 V
I
I
D(on), D(off)
–10
–20
–30
40
0
0
4
8
12
16
20
–15
–10
–5
0
5
10
15
V
D
– Drain Voltage (V)
V V – Source, Drain Voltage (V)
S, D
I
I
Leakages vs. Temperature
Switching Times vs. Power Supply Voltage
D,
S
10 nA
1 nA
250
200
150
100
50
V+ = 15 V
V– = –15 V
S,
V
V
= "14 V
D
t
TRANS
I
S (off)
I
I
100 pA
10 pA
1 pA
D(on), D(off)
t
ON(EN)
t
OFF(EN)
0
”5
”10
”15
”20
–55 –35 –15
5
25
45
65
85 105 125
Temperature (C_)
Supply Voltage (V)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-6
DG428/429
Vishay Siliconix
TYPICAL CHARACTERISTICS (_2C5 UNLESS NOTED)
Charge Injection vs. Analog Voltage
Switching Times vs. Single Supply
350
V– = 0 V
60
40
300
250
200
150
100
50
V+ = 12 V
V– = 0 V
20
t
TRANS
0
t
–20
–40
–60
ON
t
OFF
V+ = 15 V
V– = –15 V
0
–15
–10
–5
0
5
10
15
5
10
15
20
V+ – Positive Supply (V)
V
S
– Source Voltage (V)
Off-Isolation vs. Frequency
Supply Current vs. Switching Frequency
8
6
–140
–120
–100
–80
I+
E
N
A
X
= 5 V
= 0 or 5 V
4
2
I
GND
0
–2
–4
–6
–8
–60
–40
I–
–20
1 k
10 k
100 k
1 M
10 M
1 k
10 k
100 k
1 M
10 M
f – Frequency (Hz)
f – Frequency (Hz)
Input Switching Threshold
vs. PositiveSupply Voltage
Switching Times vs. Temperature
200
150
100
50
3
2.5
2
V+ = 15 V
V– = –15 V
t
TRANS
t
ON
1.5
1
t
OFF
0.5
0
0
–55 –35 –15
25
45
85
125
5
65
105
0
5
10
15
20
Temperature (C_)
V+ Positive – Supply Voltage (V)
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-7
DG428/429
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
V
REF
GND
EN
D
D
D
Q
Q
O
O
V+
V–
Level
Shift
Decode/
Drive
A
X
n
n
S
1
Latches
WR
CLK
V+
V–
RESET
S
n
RS
V–
FIGURE 1.
TIMING DIAGRAMS
3 V
RS
50%
3 V
50%
WR
0 V
t
0 V
RS
t
W
t
OFF(RS)
t
H
t
S
V
O
80%
3 V
0 V
Switch
Output
A , A , (A )
20%
0
1
2
80%
EN
0 V
FIGURE 2.
FIGURE 3.
TEST CIRCUITS
+15 V
t <20 ns
r
t <20 ns
f
V+
+2.4 V
RS
3 V
0 V
Logic
Input
50%
EN
All S and D
+5 V
a
DG428
DG429
A , A , (A )
D , D
b
0
1
2
V
O
V
S
WR
GND
V–
80%
Switch
Output
50 W
300 W
35 pF
–15 V
V
O
t
OPEN
0 V
FIGURE 4. Break-Before-Make
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-8
DG428/429
Vishay Siliconix
TEST CIRCUITS
+15 V
V+
RS
"10 V
#10 V
S
+2.4 V
1
EN
S
– S
7
2
A
A
A
0
t <20 ns
r
DG428
t <20 ns
f
1
3 V
0 V
S
8
Logic
Input
2
50%
V
O
D
WR
GND
V–
35 pF
50 W
300 W
–15 V
V
S1
90%
Switch
Output
+15 V
V
O
0 V
V+
RS
EN
10%
+2.4 V
S
#10 V
#10 V
1b
V
S8
S
1a
– S , D
4a
and S
a
3b
S
t
t
TRANS
2b
TRANS
A
0
S ON
1
S
8
ON
S
4b
DG429
A
1
D
V
O
b
WR
GND
V–
35 pF
50 W
300 W
–15 V
FIGURE 5. Transition Time
+15 V
V+
+2.4 V
RS
EN
S
1
– 5 V
DG428
S
– S
8
2
A
A
A
0
1
2
V
D
O
t <20 ns
t <20 ns
f
r
WR
GND
V–
3 V
Logic
Input
50 W
50%
35 pF
300 W
0 V
t
–15 V
t
ON(EN)
OFF(EN)
0 V
+15 V
Switch
Output
V+
+2.4 V
RS
EN
S
– 5 V
1b
V
O
DG429
90%
V
O
S
1a
– S , D
4a
a
4b
A
0
S
2b
– S
V–
A
1
D
V
O
b
WR
GND
50 W
35 pF
300 W
–15 V
FIGURE 6. Enable t /t
Time
ON OFF
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-9
DG428/429
Vishay Siliconix
TEST CIRCUITS
+15 V
V+
S
or S
1b
EN
0
+5 V
3 V
0 V
1
+2.4 V
A , A , (A )
1
2
WR
50%
t
Remaining
Switches
RS
V
O
ON(WR)
DG428
Switch
Output
DG429 D , D
WR
b
V
O
GND
V–
20%
35 pF
300 W
–15 V
0 V
FIGURE 7. Write Turn-On Time t
ON(WR)
+15 V
V+
3 V
0 V
S
1
or S
1b
EN
0
+5 V
+2.4 V
RS
A , A , (A )
50%
1
2
Remaining
Switches
t
OFF(RS)
DG42
DG429
V
O
D , D
b
RS
80%
V
O
Switch
Output
WR
GND
V–
35 pF
300 W
–15 V
0 V
FIGURE 8. Reset Turn-Off Time t
OFF(RS)
+15 V
V+
A , A , (A )
OFF
ON
OFF
DV
RS
D
0
1
2
2.4 V
EN
R
g
O
S
V
O
V
O
IN
C
L
1 nF
V
g
3 V
WR
V–
GND
DV is the measured voltage error due to
O
charge injection. The charge in coulombs is Q =
x DV
C
L
O
–15 V
FIGURE 9. Charge Injection
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-10
DG428/429
Vishay Siliconix
DETAILED DESCRIPTION
APPLICATIONS
The internal structure of the DG428/DG429 includes a 5-V
logicinterfacewithinputprotectioncircuitryfollowedbyalatch,
level shifter, decoder and finally the switch constructed with
parallel n- and p-channel MOSFETs (see Figure 1).
Bus Interfacing
The DG428/DG429 minimize the amount of interface
hardware between a microprocessor system bus and the
analogsystem being controlled or measured. The internal TTL
compatiblelatches give these multiplexers write-only memory,
that is, they can be programmed to stay in a particular switch
state (e.g., switch 1 on) until the microprocessor determines it
isnecessarytoturndifferentswitchesonorturnallswitchesoff
(see Figure 10).
The input protection on the logic lines A0, A1, A2, EN and
control lines WR, RS shown in Figure 1 minimizes
susceptibility to ESD that may be encountered during handling
and operational transients.
The input latches become transparent when WR is held low;
therefore,thesemultiplexersoperatebydirectcommandofthe
coded switch state on A2, A1, A0. In this mode the DG428 is
identical to the popular DG408. The same is true of the DG429
versus the popular DG409.
ThelogicinterfaceisaCMOSlogicinputwithitssupplyvoltage
from an internal +5 V reference voltage. The output of the input
inverter feeds the data input of a D type latch. The level
sensitiveDlatchcontinuouslyplacestheDX inputsignalonthe
QX output when the WR input is low, resulting in transparent
latch operation. As soon as WRreturnshighthelatchholdsthe
datalastpresentontheDn input, subjecttothe“MinimumInput
Timing Requirements” table.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG428 maintains all switches in the off state.
Following the latches the Qn signals are level shifted and
decodedtoprovideproperdrivelevelsfortheCMOSswitches.
This level shifting ensures full on/off switch operation for any
analog signal level between the V+ and V– supply rails.
When the system program performs a write operation to the
address assigned to the DG428, the address decoder
provides a CS active low signal which is gated with the WRITE
(WR)controlsignal.AtthistimethedataontheDATABUS(that
will determine which switch to close) is stabilizing. When the
WR signal returns to the high state, (positive edge) the input
latches of the DG428 save the data from the DATA BUS. The
coded information in the A0, A1, A2 and EN latches is decoded
and the appropriate switch is turned on.
The EN pin is used to enable the address latches during the
WRpulse. ItcanbehardwiredtothelogicsupplyortoV+ifone
of the channels will always be used (except during a reset) or
itcanbetiedtoaddressdecodingcircuitryformemorymapped
operation. The RS pin is used as a master reset. All latches are
clearedregardlessofthestateofanyotherlatchorcontrolline.
The WR pin is used to transfer the state of the address control
lines to their latches, except during a reset or when EN is low
(see Truth Tables).
TheENlatchallowsallswitchestobeturnedoffunderprogram
control. This becomes useful when two or more DG428s are
cascaded to build 16-line and larger multiplexers.
+15 V
"15 V
Analog
Inputs
S
1
V+
Data Bus
A , A , A , EN
0
1
2
DG428
RS
RESET
Processor
System
+5 V
Bus
S
8
WRITE
WR
D
Address
Bus
Analog
Output
V–
Address
Decoder
– 15 V
FIGURE 10.Bus Interface
Document Number: 70063
S-52433—Rev. J, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-11
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
www.vishay.com
1
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