AN101 [VISHAY]

MOSFETs; MOSFET的


型号：	AN101
厂家：	VISHAY
描述：	MOSFETs MOSFET的
文件：	总5页 (文件大小：46K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN101

An Introduction to FETs

The family tree of FET devices (Figure 1) may be divided

into two main branches, Junction FETs (JFETs) and Insu-

lated Gate FETs (or MOSFETs, metal-oxide- semicon-

ductor field-effect transistors). Junction FETs are in-

herently depletion-mode devices, and are available in

both n- and p-channel configurations. MOSFETs are

available in both enhancement and depletion modes, and

also exist as both n- and p-channel devices. The two main

FET groups depend on different phenomena for their op-

eration, and will be discussed separately.

Introduction

The basic principle of the field-effect transistor (FET) has

been known since J. E. Lilienfeld’s patent of 1925. The

theoretical description of a FET made by Shockley in

1952 paved the way for development of a classic electron-

ic device which provides the designer the means to ac-

complish nearly every circuit function. At one time, the

field-effect transistor was known as a “unipolar” transis-

tor. The term refers to the fact that current is transported

by carriers of one polarity (majority), whereas in the con-

ventional bipolar transistor carriers of both polarities

(majority and minority) are involved.

Junction FETs

In its most elementary form, this transistor consists of a

piece of high-resistivity semiconductor material (usually

silicon) which constitutes a channel for the majority carri-

er flow. The magnitude of this current is controlled by a

voltage applied to a gate, which is a reverse-biased pn

junction formed along the channel. Implicit in this de-

scription is the fundamental difference between JFET and

bipolar devices: when the JFET junction is reverse-biased

the gate current is practically zero, whereas the base cur-

rent of the bipolar transistor is always some value greater

than zero. The JFET is a high-input resistance device,

while the input resistance of the bipolar transistor is com-

paratively low. If the channel is doped with a donor impu-

rity, n-type material is formed and the channel current

will consist of electrons. If the channel is doped with an

acceptor impurity, p-type material will be formed and the

channel current will consist of holes. N-channel devices

have greater conductivity than p-channel types, since

electrons have higher mobility than do holes; thus n-chan-

nel JFETs are approximately twice as efficient conductors

compared to their p-channel counterparts.

This Application Note provides an insight into the nature of

the FET, and touches briefly on its basic characteristics, ter-

minology, parameters, and typical applications.

The following list of FET applications indicates the ver-

satility of the FET family:

Amplifiers

S Small Signal

S Low Distortion

S High Gain

S Low Noise

S Selectivity

S DC

Switches

S Chopper-Type

S Analog Gate

S Communicator

Protection Diodes

S Low-leakage

S High-Frequency

Current Limiters

Voltage-Controlled Resistors

Mixers

Oscillators

FETs

Junction

MOS

Enhancement

Not Possible

Depletion

Enhancement

Figure 1. FET Family Tree

Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70594.

Siliconix

10-Mar-97

AN101

In addition to the channel material, a JFET contains two layer as V increases. The curve approaches the level of

ohmic (non-rectifying) contacts: the source and the drain. the limiting current I

when I begins to be pinched off.

DSS

These are shown in Figure 2. Since a symmetrical geome- The physical meaning of this term leads to one definition

try is shown in the idealized JFET chip, it is immaterial of pinch-off voltage, V , which is the value of V at

which contact is called the source and which is called the which the maximum I

drain; the JFET will conduct current equally well in either

direction and the source and drain leads are usually inter-

changeable.

flows.

DSS

V_DS< V_P

N-Source

Channel

N-Drain

Depletion

Layer

N-Channel

P-Gate

Final form taken by FET with n-type channel embedded in p-type

substrate.

3a) N-Channel FET Working in the Ohmic Region (V_GS

Figure 2. Idealized Structure of An N-Channel

0 V) (Depletion Shown Only in Channel Region)

Junction FET

(For certain JFET applications, such as high-frequency

amplifiers, an asymmetrical geometry is preferred for

lower capacitance and improved frequency response. In

these cases, the source and drain leads should not be inter-

changed.)

V_DS> V_P

Depletion

Layer

Figure 3 shows how the JFET functions. If the gate is con-

nected to the source, then the applied voltage (V ) will

appear between the gate and the drain. Since the pn junc-

tion is reverse-biased, little current will flow in the gate

connection. The potential gradient established will form

a depletion layer, where almost all the electrons present

in the n-type channel will be swept away. The most de-

pleted portion is in the high field between the gate and the

drain, and the least-depleted area is between the gate and

the source. Because the flow of current along the channel

from the (positive) drain to the (negative) source is really

a flow of free electrons from source to drain in the n-type

silicon, the magnitude of this current will fall as more sili-

con becomes depleted of free electrons. There is a limit

3b) N-Channel FET Working in the Current Saturation

Region (V_GS= 0)

I_DSS

Saturation Region

Current

V_GS= 0 V

Ohmic

Region

to the drain current (I ) which increased V can drive

through the channel. This limiting current is known as

(Drain-to-Source current with the gate shorted to the

DSS

source). Figure b shows the almost complete depletion of

the channel under these conditions.

3c) Idealized Output Characteristic for V_GS= 0

Figure 3.

Figure 3c shows the output characteristics of an n-channel

JFET with the gate short-circuited to the source. The

initial rise in I is related to the buildup of the depletion

Siliconix

10-Mar-97

AN101

In Figure 4, consider the case where V = 0 and where saturation region. JFETs operating in the current satura-

a negative voltage V is applied to the gate. Again, a tion region make excellent amplifiers. Note that in the

depletion layer has built up. If a small value of V were ohmic region both V and V control the channel cur-

now applied, this depletion layer would limit the resultant rent, while in the current saturation region V has little

channel current to a value lower than would be the case effect and V essentially controls I .

for V = 0. In fact, at a value of V > V the channel

current would be almost entirely cut off. This cutoff volt-

age is referred to as the gate cutoff voltage, and may be

Figure 5b relates the curves in Figure 5a to the actual cir-

cuit arrangement, and shows the number of meters which

may be connected to display the conditions relevant to

expressed by the symbol V or by V

. V has been

GS(off)

widely used in the past, but V

is now more com-

GS(off)

any combination of V and V . Note that the direction

monly accepted since it eliminates the ambiguity be-

tween gate cut-off and drain pinch-off.

of the arrow at the gate gives the direction of current flow

for the forward-bias condition of the junction. In practice,

however, it is always reverse-biased.

Depletion

Layer

The p-channel JFET works in precisely the same way as

the n-channel JFET. In manufacture, the planar process is

essentially reversed, with the acceptor impurity diffused

first onto n-type silicon, and the donor impurity diffused

later to form a second n-type region and leave a p-type

channel. In the p-channel JFET, the channel current is due

to hole movement, rather than to electron mobility. Con-

sequently, all the applied polarities are reversed, along

with their directions and the direction of current flow.

V_GS

Figure 4. N-Channel FET Showing Depletion Due to

In summary, a junction FET consists essentially of a chan-

nel of semiconductor material along which a current may

Gate-Source Voltage and V_DS= 0

flow whose magnitude is a function of two voltages, V

The mechanisms of Figures 3 and 4 react together to pro- and V . When V is greater than V , the channel cur-

vide the family of output characteristics shown in Figure rent is controlled largely by V alone, because V is ap-

5a. The area below the pinch-off voltage locus is known plied to a reverse-biased junction. The resulting gate cur-

as the ohmic region: the area above pinch-off is current rent is extremely small.

– V

= 0

DSS

–

= –V

–

GS(off)

5a) Family of Output Characteristics

5b) Circuit Arrangement for N-Channel FET

for N-Channel FET

Figure 5.

Siliconix

10-Mar-97

AN101

There are, however, some fundamental performance dif-

ferences between MOSFETs and JFETS. JFETs, by na-

ture, operate only in the depletion mode. That is, a reverse

gate bias depletes, or pinches off the flow of channel cur-

rent. A MOSFET, by virtue of its electrically-insulated

gate, can be fabricated to perform as either a depletion-

mode or enhancement-mode FET. Quite unlike the JFET,

a depletion-mode MOSFET will also perform as an en-

hancement-mode FET.

MOSFETs

The metal-oxide-semiconductor FET (MOSFET) depends

on the fact that it is not actually necessary to form a semi-

conductor junction on the channel of a FET to achieve gate

control of the channel current. On a MOSFET, the metallic

or polysilicon gate is isolated from the channel by a thin lay-

er of silicon dioxide (Figure 6a). Although the bottom of the

insulating layer is in contact with the p-type silicon sub-

strate, the physical processes which occur at this interface

dictate that free electrons will accumulate in the interface, While the great majority of JFETs operate as described in

inverting the p-type material and spontaneously forming an Figures 3 and 4, MOSFETs can assume several forms and

n-type channel. Thus, a conduction path exists between the operate in either the depletion/enhancement-mode or en-

diffused n-type channel source and drain regions.

hancement-mode only.

Metal

Insulating

Layer

–

Substrate

6a) Idealized Cross-Section Through an

6b) Circuit Arrangement for

N-Channel Depletion MOSFET

N-Channel Depletion-Type MOSFET

= V – V

GS GS(th)

Ohmic Region Characteristics

6 V

200

1.0

= 10 V

V_GS= 0.2 V

0 V

5 V

T = 25_C

160

0.8

0.6

0.4

0.2

–0.2 V

4 V

120

–0.4 V

–0.6 V

3 V

2 V

–0.8 V

–1 V

0.4

0.8

1.2

1.6

2.0

1.0

2.0

3.0

4.0

5.0

– Drain-Source Voltage (V)

6c) Family of Output Characteristics

for N-Channel Depletion MOSFET

6d) Family of Output Characteristics for

N-Channel Enhancement MOSFET

Figure 6.

Siliconix

10-Mar-97

AN101

There are three types of small-signal MOSFETs. First, we precisely-defined short channel that results and the “drift

have the planar, lateral MOSFET, similar to that shown in region” resulting from the remaining p-doped silicon

Figure 6a. By virtue of the n-doped channel spanning body and light n-doped ion implant.

from source to drain, it performs as an n-channel deple-

Gate

tion-mode MOSFET in a fashion not unlike that of the

Source

Drain

Metal

depletion-mode JFET when a voltage of the correct polar-

ity is applied to the gate, as in Figure 6b. However, if we

forward-bias the gate (that is, place a gate voltage whose

polarity equals the drain voltage polarity) additional elec-

trons will be attracted to the region beneath the gate, fur-

ther enhancing – and inverting (from p to n) the region.

As the channel region thickens, the channel resistance

will further decrease, allowing greater channel current to

Oxide

N+

N–

P-Silicon

Substrate

Figure 8. Planar Enhancement-Mode DMOS

flow beyond that identified as I , as we see in the family

DSS

of output characteristics in Figure 6c.

Although Figures 7 and 8 illustrate n-channel enhance-

ment-mode DMOS FETs, by reversing the doping se-

quences, p-channel DMOS FETs can easily be fabricated.

Furthermore, by lightly doping across the short channel

and drift region, depletion-mode DMOS FETs can be

constructed.

MOSFETs can also be constructed for enhancement-

mode-only performance, as shown in Figure 7. Unlike the

depletion-mode device, the enhancement-mode MOSFET

offers no channel between the source and drain. Not until a

forward bias on the gate enhances a channel by attracting

electrons beneath the gate oxide will current begin to flow

(Figure 6d).

As a result of the short channel, the MOSFET is allowed

to operate in “velocity saturation” and as a result of the

drift region, the MOSFET offers higher operating volt-

ages. Together, the short channel and the drift region offer

low on-resistance and low interelectrode capacitances,

Gate

Source

Drain

especially gate-to-drain, V

Oxide

Velocity saturation coupled with low interelectrode ca-

pacitance offers us high-speed and high-frequency per-

formance.

P-Silicon

Body

N–

Gate

Source

Figure 7. Planar Enhancement-Mode MOS Cross-Section

Metal

P+

N–

A newer MOSFET offering superior performance is the

lateral double-diffused or DMOS FET. Because of the li-

mitations of photo-lithographic masking, the earlier, old-

er-style MOSFET was severely limited in performance.

Some of these former limitations involved switching

N+

Drain

Figure 9. Vertical N-Channel Enhancement-Mode

DMOS FET

speeds, channel conductivity (too high an r ), and cur-

rent handling in general. The lateral DMOS FET removed

these limitations, offering a viable alternative between

the JFET and the GaAs FET for video and high-speed

switching applications.

The novelty of the short-channel DMOS FET led to the

evolution of a yet more advanced, higher-voltage, higher-

current MOSFET: the Vertical Double-Diffused MOSFET

(Figure 9). Where this vertical MOSFET offers improved

power-handling capabilities, its fundamental shortcoming is

The lateral DMOS FET differs radically in its channel that because of its construction and to a lesser extent because

construction when compared with the older planar MOS- of its size, it fails to challenge the high-speed performance

FET. Note the double-diffused source implant into the im- of the lateral DMOS FET. Consequently, the vertical and lat-

planted p-doped channel region, shown in Figure 8. The eral DMOS FETs complement each other in a wide selection

improved performance of DMOS is a result of both the of applications.

Siliconix

10-Mar-97

AN101 [VISHAY]

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