GA1086 [TRIQUINT]
11-Output Clock Buffer; 11路输出时钟缓冲器
| 型号： | GA1086 |
| 厂家： | 
TRIQUINT SEMICONDUCTOR |
| 描述： | 11-Output Clock Buffer |
| 文件： | 总12页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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S E M I C O N D U C T O R , I N C .
GA1086
Figure 1. Block Diagram
FBIN
11
S1
10
CLK S0
NC NC GND
8
7
6
5
9
11-Output
Clock Buffer
12
4
3
2
S2
VDD
Q9
Phase
Detector
Control
Logic
13
14
15
16
17
18
VDD
Q/2
VCO
Q8
Divide
Logic
1
GND
FBOUT
Q1
GND
Q7
Features
28
27
26
MUX
Q6
• Operates from 30 MHz to 67MHz
Precision
Output
Buffers
VDD
VDD
•
•
•
Pin-to-pin output skew of
250 ps (max)
19
GND
20
21
22
23
24
25
Q2
Q3
VDD
Q4
Q5 GND
Period-to-period jitter:
75 ps (typ)
TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock
buffer chip supports the tight timing requirements of high-performance
microprocessors, with near zero input-to-output delay and very low pin-to-
pin skew. The device offers 10 usable outputs synchronized in phase and
frequency to a periodic clock input signal. One of the ten outputs is a one-
half clock output (CLK ÷ 2). With split termination, the GA1086 can be
used to drive up to nineteen 15 pF loads, as shown in Figure 10.
Near-zero propagation delay:
–350 ps ± 500 ps or
–350 ps ± 1000 ps
•
•
10 symmetric, TTL-compatible
outputs with 30 mA drive and
rise and fall times of 1.4 ns(max)
28-pin J-lead surface-mount
package
The tight control over phase and frequency of the output clocks is achieved
with a 400 MHz internal Phase-Locked Loop (PLL). By feeding back one of
the output clocks to FBIN, the on-chip PLL continuously maintains
synchronization between the input clock (CLK) and all ten outputs. Any
drift or gradual variation in the system clock is matched and tracked at the
ten outputs. The GA1086 output buffers are symmetric, each sourcing and
sinking up to 30 mA of drive current. For diagnostic purposes, the device
has a test mode which is used to test the device and associated logic by
single-stepping through the control logic.
•
•
Special test mode
Meets or exceeds Pentium™
processor timing requirements
•
Typical applications include
low-skew clock distribution for:
•
•
•
RISC- or CISC-based systems
Multi-processor systems
High-speed backplanes
The GA1086 is fabricated using TriQuint’s One-Up™ gallium arsenide
technology to achieve precise timing control and to guarantee 100% TTL
compatibility. The output frequency makes this device ideal for clock
generation and distribution in a wide range of high-performance
microprocessor-based systems. Many other CISC- and RISC-based
systems will also benefit from its tight control of skew and delay.
1
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GA1086
Functional Description
control bit settings, divide mode and VCO range.
FBOUT is fed back to FBIN and has the same frequency
as the Qn outputs.
The GA1086 generates 10 outputs (Q1 – Q9 and
FBOUT) which have the same frequency and zero phase
delay relative to the reference clock input. In addition,
there is one output (Q/2) that has 1/2 the frequency of
the reference clock. The GA1086 maintains frequency
and zero phase delay using a Phase Detector to
compare the output clock with the reference clock
input. Phase deviations between the output clock and
reference clock are continuously corrected by the PLL.
Figure 1 shows a block diagram of the PLL, which
consists of a Phase Detector, Voltage Controlled
Oscillator (VCO), Divide Logic, Mux and Control Logic.
The GA1086 has a test mode that allows for single
stepping of the clock input for testing purposes. With
S2 HIGH, S1 LOW and S0 HIGH, the signal at the CLK
input goes directly to the outputs, bypassing the PLL
circuitry.
The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the GA1086 are TTL-compatible with 30
mA symmetric drive and a minimum VOH of 2.4 V.
The GA1086-MC500 and GA1086-MC1000 are identical
except for the propagation delay specification (see AC
Characteristics table).
The Phase Detector monitors the phase difference
between FBIN which is connected to FBOUT, and the
reference clock (CLK). The Phase Detector adjusts the
VCO such that FBIN aligns with CLK. The VCO has an
operating range of 360 MHz to 402 MHz. The output
clocks (Qn, FBOUT, and Q/2) are generated by dividing
the VCO output.
Breaking the Feedback Loop
There is no requirement that the external feedback
connection be a direct hardwire from an output pin to
the FBIN pin. As long as the signal at FBIN is derived
directly from the FBOUT pin and maintains its
frequency, additional delays can be accommodated.
The internal phase-locked loop will adjust the output
clocks on the GA1086 to ensure zero phase delay
between the FBIN and CLK signals.
The desired operating frequency determines the proper
divide mode. There are 4 divide modes; ÷12, ÷10, ÷8
and ÷6. In each mode, the GA1086 operates across the
frequency range listed in the Divide Mode Selection
Table. The operating frequency is equivalent to the VCO
frequency divided by the mode number.
Note: the signal at FBIN must be continuous, i.e. not a gated or
conditional signal.
Table 1 shows the input clock frequency (CLK), output
clock frequency (Qn), 1/2 output clock frequency (Q/2),
Table 1. Divide Mode Selection Table
Control
S1
Divide
Mode
CLK
Qn
Q/2
S2
S0
30 – 33 MHz
36 – 40 MHz
45 – 50 MHz
60 – 67 MHz
TSTCLK
30 – 33 MHz
36 – 40 MHz
45 – 50 MHz
60 – 67 MHz
TSTCLK
15 – 16.5 MHz
18 – 20 MHz
22.5 – 25 MHz
30 – 33.5 MHz
TSTCLK/2
1
1
1
0
1
1
1
0
1
0
1
0
0
1
1
÷12
÷10
÷8
÷6
—
2
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GA1086
obtained by summing the various skews. The skew
between the outputs of the GA1086 (1) which drive
the GA1086 (2) and the GA1086 (n) is summed
with the propagation delay of the GA1086 (2 or n),
the skew between the outputs of the GA1086 (2),
and the skew between the outputs of the GA1086
(n). This results in a total skew of 1.75 ns (250 ps +
1000 ps + 250 ps + 250 ps).
Power-Up/Reset Synchronization
The GA1086 utilizes on-chip phase-locked loop (PLL)
technology to maintain synchronization between inputs
and outputs. Whenever the device is powered up, or
the system clock (CLK) is reset, the phase-locked loop
requires a synchronization time (tSYNC) before lock is
achieved. The maximum time required for
synchronization is 500 ms.
2) Board-to-Board Synchronization
Typical Applications
Many computing systems today consist of multiple
boards designed to run synchronously. The skew
associated with routing clocks across a backplane
presents a major hurdle to maximizing system
performance.
The GA1086 is designed to satisfy a wide range of
system clocking requirements. Following are two of the
most common clocking bottlenecks which can be
solved using the GA1086.
• The edge placement feature of TriQuint's
configurable custom clock generator (GA1110E)
operating at 33 MHz, coupled with the tightly
controlled input/output delay of the GA1086,
ensures all boards in the system are running
synchronously.
1) Low-Skew Clock Distribution / Clock Trees
The most basic bottleneck to clocking high-performance
systems is generating multiple copies of a system clock,
while maintaining low skew throughout the system.
• The GA1086 guarantees low skew among all clocks
in the system by controlling both the input-to-
output delay and the skew among all outputs. In
Figure 2, the worst-case skew from Output 1 to
Output n, with reference to the system clock, is
Figure 3. Board-to-Board Synchronization
HOST
TARGETS
Figure 2. Low-Skew Clock Distribution
t
–t
–2t
GA1110E
SYS
CLK
GA1086
Q1
GA1086
(1)
OUTPUT 1
SYSTEM
CLOCK
Q1
GA1086
(2)
•
•
•
•
•
•
Q/2
Q9
•
•
•
GA1086
(n)
OUTPUT n
3
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GA1086
Multi-Processor Systems
The GA1086 can be effectively used to distribute clocks
in RISC- or CISC-processor-based systems. Its 10
outputs support both single- and multi-processor
systems. Following are three representative
configurations which show how the 10 outputs can be
used to synchronize the operation of CPU cache and
memory banks operating at different speeds.
Figure 4 depicts a 2-CPU system in which the
processors and associated peripherals are operating at
66 MHz. Each of the nine outputs operating at 66 MHz
are fully utilized to drive the appropriate CPU, cache,
and memory control logic. The 33 MHz output is used
to synchronize the operation of the slower memory
bank to the rest of the system.
Figure 4. Clocking a Dual-CPU System
R
CPU 1
CACHE
FBOUT
FBIN
R
R
SYSTEM
CLOCK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q/2
CLK
MEMORY
CONTROL
LOGIC
R
R
(66 MHZ)
R
R
R
GA1086
CPU 2
CACHE
R
R
LOW
S2
S1
S0
HIGH
HIGH
R
SLOW
MEMORY
CONTROL
LOGIC
(33 MHZ)
4
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GA1086
Multi-Processor Systems (cont.)
Figure 5 shows a 4-processor system with various
33 MHz memory banks synchronized to the 66 MHz
CPUs. The GA1110E, a custom device whose six
outputs can be individually configured, (see
the GA1086 devices. This configuration gives the user
18 copies of the 66 MHz clock and 7 copies of the 33
MHz clock. By using the configurability of the
GA1110E, the user can also specify and control the
placement of the edges of the outputs of the GA1110E.
GA1110E data sheet), is used as the clock source for
Figure 5. Generating Multiple Outputs
R
FBIN FBOUT
Q1
1
33 MHz
FBIN
CLK
FBOUT
GA1086
MC500
CLK
9 @ 66 MHz
33MHz
6 pF
Q1
Q2
Q3
Q4
Q5
Q9
2
3
– t
– 2t
– 3t
4 @ 33 MHz
Q/2
33 MHz
33 MHz
R
Note: The GA1000 is a custom device whose outputs
can be customized to the user's requirement.
The figure above is one possible configuration.
FBIN FBOUT
Q1
4
GA1086
MC500
CLK
9 @ 66 MHz
Max Pin-to-Pin Skew from:
6 pF
1
1
1
2
2
3
3
4
to
to
to
to
to
to
to
to
= 1.2 ns*
= 1.75 ns
= 1.5 ns
2
3
4
3
5
4
5
5
5
Q9
Q/2
33 MHz
= 2.7 ns*
= 3.2 ns*
= 1.75 ns
= 2.7 ns*
= 1.2 ns*
Assumes maximum skew between Q9 and Q/2 is 1.2 ns. See AC specifications.
*
5
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GA1086
Single-Processor Systems
The table in Figure 5 also specifies the maximum pin-
to-pin skew of various sets of outputs from the three
clocking devices.
Figure 6 is an example of a single-CPU system. The
nine 66MHz outputs of the GA1086 are used to drive
the CPU and its related cache, the state machine,
memory banks, and other general-purpose logic.
Please note that the GA1086s are series-terminated and
that the feedback trace lengths for the two devices
should be equal.
Figure 6. Clocking a Single-CPU System
R
CPU
CACHE
FBOUT
FBIN
R
SYSTEM
CLOCK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q/2
CLK
R
R
R
STATE
MACHINE
R
R
R
GA1086
R
R
MEMORY
CONTROL
LOW
HIGH
HIGH
S2
S1
S0
R
LOGIC
BLOCK 1
LOGIC
BLOCK 2
6
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GA1086
Parallel Termination of Outputs
the Thevenin equivalent using two resistors and +5 V
supply can replace the 65 ohms to 1.5 V.
The GA1086 can be terminated either in parallel or in
series. If power dissipation is not of primary concern,
then parallel termination can be the most effective
mode of termination for the GA1086. An example of
this termination is shown in Figure 7, along with the
waveforms at an output pin and at the load. Note that
Unused outputs must be terminated.
Figure 7. Parallel Termination
A
B
R
OUT
Z
R
IN
O
V
OUT
t
AB
R
T
Series Termination of Outputs
to use balanced termination as shown in Figure 8. This
could, however, slow the rise time of the pulses
arriving at the destination.
The alternative to parallel termination is series
termination. For applications where overshoots and
undershoots of the clock signal are a concern, it is best
Figure 8. Balanced Termination
52 Ω
65 Ω
FBIN
13 Ω
Q
Q
t
t
FBOUT
0
1
1.4 ns (max)
1.8 ns (typ)
52 Ω
13 Ω
Q
65 Ω
Q
t
1
CLK
Q
t
0
30 pF
GA1086
7
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GA1086
If rise times are critical and if overshoots and
undershoots can be tolerated, then unbalanced
termination may be used. Reflections due to
unbalanced termination can cause ringing at the load.
The transmission line lengths, therefore, must be long
enough to cause the ringing to occur only after the
waveform has completely switched to either the LOW
or the HIGH state, (the round trip). The propagation
time of the output signals should be greater than the
switching time for LOW to HIGH or HIGH to LOW.
To double the number of loads (devices) driven by the
GA1086, split termination may be used. Examples of
three types of series termination and the resulting
waveforms, measured between 0.8 V and 2.0 V, are
shown in Figures 9 and 10 for one of the outputs.
Unused outputs must be terminated.
Figure 9. Unbalanced Termination
37 Ω
65 Ω
FBIN
Q
Q
t
t
0
1
13 Ω
FBOUT
1.4 ns (max)
1.5 ns (typ)
37 Ω
13 Ω
Q
65 Ω
Q
t
1
CLK
Q
t
0
30 pF
GA1086
Figure 10. Split Unbalanced Termination
65 Ω
65 Ω
12 Ω
15 pF
Q
Q
Q
t
0
FBIN
13 Ω
FBOUT
1.4 ns (max)
Q
65 Ω
t
1
12 Ω
13 Ω
15 pF
Q
t
t
1
2
CLK
Q
t
0
GA1086
1.5 ns (typ)
1.5 ns (typ)
Q
t
65 Ω
2
15 pF
Note: Rise time at Qt1 is measured between 0.8 V and 2.0 V.
8
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GA1086
Absolute Maximum Ratings
Storage temperature
–65 °C to +150 °C
–55 °C to +100 °C
–0.5 V to +7.0 V
Ambient temperature with power applied
Supply voltage to ground potential
DC input voltage
–0.5 V to +(VDD + 0.5)
–30 mA to +5 mA
DC input current
Caution: Damage to the device may occur if an output is shorted to ground or VDD
.
DC Characteristics
(Supply voltage: +5 V + 5% Ambient temp: 0 °C to +70 °C) 1
Limits 2
Typ
Symbol
Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH voltage
VDD = Min
IOH= –30 mA
2.4
3.6
V
VIN= VIH or VIL
VOL
Output LOW voltage
Input HIGH level
Input LOW level
VDD = Min
VIN= VIH or VIL
IOL = 30 mA
0.2
0.5
V
V
V
3
VIH
Guaranteed input logical HIGH
voltage for all inputs
2.0
3
VIL
Guaranteed input logical LOW
voltage for all inputs
0.8
IIL
IIH
II
Input LOW current
Input HIGH current
Input HIGH current
Power supply current
Input clamp voltage
VDD = Max
VDD = Max
VDD = Max
VDD = Max
VDD = Min
VIN = 0.40 V
VIN = 2.7 V
VIN = 5.5 V
–166
–400
25
µA
0
2
µA
1000
115
–1.2
µA
4
IDD
160 mA
V
VI
IIN = –18 mA
–0.62
Capacitance 1,5
Symbol
Description
Test Conditions
Min
Typ
Max
Unit
CIN
Input capacitance
VIN = 2.0 V at f = 1 MHz
6
pF
Notes: 1. These values apply to both the GA1086-MC500 and GA1086-MC1000.
2. Typical limits are at VDD = 5.0 V and TA = 25 °C.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4. IDD is measured with outputs LOW and unloaded.
5. These parameters are not 100% tested, but are periodically sampled.
9
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GA1086
AC Specifications
Figure 11. Switching Waveforms
(Supply voltage: +5 V + 5%, Ambient temp: 0 °C to +70 °C) Buffer Configuration (FBIN = FBOUT)
Input Clocks
Min
Typ
Max Unit
t
t
CPW
CPW
REFCLK
FBIN
FIN
tCP
CLK frequency
30
14.9
3.0
—
—
—
—
—
67
33
—
MHz
ns
CLK period
t
t
JR
tCPW
tIR
CLK pulse width
Input rise time (0.8 V – 2.0 V)
ns
PD1,2
2.0
ns
t
PERIOD
Q0 – Q10
(INDIVIDUALLY)
t
JP
Output Clocks
Min
Typ
Max Unit
tOR
tOF
Output rise time (0.8 V – 2.0 V) 0.15
Output fall time (0.8 V – 2.0 V) 0.15
—
—
1.4
1.4
ns
ns
ps
ps
ps
ps
ps
ns
ps
ns
µs
ps
1
tPD1
CLK Î to FBIN Î (MC500)
CLK Î to FBIN Î (MC1000)
–850
–1350
–125
–125
–125
—
–350
–350
—
+150
+650
+125
+125
+125
1.2
1,2
tPD2
Figure 12. AC Test Circuit
2,3
tSKEW1 Q1–Q9 and FBOUT (0.8V)
2,3
tSKEW1 Q1–Q9 and FBOUT (1.5V)
—
2,3
tSKEW1 Q1–Q9 and FBOUT (2.0V)
—
Y
2,3
+5 V
R1
+5 V
tSKEW2 Q/2 Output skew
0.6
100
1.0
200
75
50 Ω
X
4
tW
Output window
—
250
—
R1
R2
Z
+5 V
5
Q0
Q1
Q2
•
•
•
tCYC
Duty-cycle variation
Synchronization time
Period-to-period jitter
—
FBIN
CLK
R1
R2
R2
6
tSYNC
—
500
—
7
•
tJIT
—
+5 V
R1
•
•
•
+5 V
R1
Z
•
Q10
R2
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y + Z = X
Notes: 1. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
2. tPD and tSKEW are tested with an input clock having a rise time of 0.5 ns (0.8 V to 2.0 V).
3. The output skew is measured from the middle of the output window, tW. The maximum skew is guaranteed across all voltages and
temperatures.
4. tW specifies the width of the window in which outputs Q1–Q9 switch.
5. This specification represents the deviation from 50/50 on the outputs; it is sampled periodically but is not guaranteed.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
7. Jitter is specified as a peak-to-peak value.
10
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GA1086
28-Pin MQuad J-Leaded Package Mechanical Specification
(All dimensions are in inches)
.172 ±.005
.040 MIN
.490 ±.005
.132 ±.005
.445 ±.005
.045
X 45°
PIN 1
.490
.410
±.015
±.005
8
22
.018
.050 TYP.
.028
.445
±.005
.445
±.005
0.125
VENT PLUG
15
.060
.104
±.005
.015
X 45°
.050 TYP.
NON-ACCUM.
28-Pin MQuad Pin Description
Pin #
Pin Name
Description
I/O
Pin #
Pin Name
Description
I/O
1
2
GND
Q8
Ground
–
O
O
–
–
–
–
I
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
FBOUT
Q1
Ground
–
O
O
–
Output Clock 8
Output Clock 9
+5 V
Feedback Clock
Output Clock 1
+5 V
3
Q9
4
VDD
GND
N/C
N/C
S0
VDD
GND
Q2
5
Ground
Ground
–
6
No Connect
No Connect
Select 0
Output Clock 2
Output Clock 3
+5 V
O
O
–
7
Q3
8
VDD
Q4
9
CLK
S1
Reference Clock
Select 1
I
Output Clock 4
Output Clock 5
Ground
O
O
–
10
11
12
13
14
I
Q5
FBIN
S2
Feedback In
Select 2
I
GND
VDD
Q6
I
+5 V
–
VDD
Q/2
+5 V
–
O
Output Clock 6
Output Clock 7
O
O
Half-Clock Out
Q7
11
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GA1086
Layout Guidelines
through-holes connect this small surface plane to an
inner-layer ground plane. The capacitors (C1–C5) are
0.1 mF. TriQuint’s test board uses X7R temperature-
stable capacitors in 1206 SMD cases.
Multiple ground and power pins on the GA1086 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the VDD supply
pins to the nearest ground pin, as close to the chip as
possible.
Figure 13. Top Layer Layout of Power Pins
(Approx. 3.3x)
V
V
DD
DD
C4
C3
Pin 1
Figure 13 shows the recommended power layout for
the GA1086. The bypass capacitors should be located
on the same side of the board as the GA1086. The VDD
traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple
Ground
Plane
V
DD
C2
Ordering Information
Pin 15
To order, please specify as shown below:
C1
C5
V
V
DD
DD
GA1086-MC n...n
11-Output Clock Buffer
Propagation delay skew:
500 –350 ps ± 500 ps
1000 –350 ps ± 1000 ps
Additional Information
For latest specifications, additional product
information, worldwide sales and distribution locations,
and information about TriQuint:
Temperature range:
Web: www.triquint.com
Email: sales@tqs.com
Tel: (503) 615-9000
Fax: (503) 615-8900
0 °C to 70 °C (Commercial)
Package: MQuad
For technical questions and additional information on
specific applications:
Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
12
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