GA1087 [TRIQUINT]
11-Output Configurable Clock Buffer; 11路输出可配置的时钟缓冲器
| 型号： | GA1087 |
| 厂家： | 
TRIQUINT SEMICONDUCTOR |
| 描述： | 11-Output Configurable Clock Buffer |
| 文件： | 总10页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T
R
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S E M I C O N D U C T O R , I N C .
GA1087
FBIN GND REFCLK GND F1
F0 GND
11
10
8
7
6
5
9
11-Output
Configurable
Clock Buffer
12
13
14
15
16
17
18
4
3
2
TEST
VDD
Q0
VDD
Q10
Q9
Phase
Detector
VCO
MUX
1
GND
Q1
GND
Q8
Features
Divide Logic
÷4, ÷5, or ÷6
28
27
26
• Wide frequency range:
24 MHz to 105 MHz
Q2
Q7
Output Buffers
Group A
• Output configurations:
five outputs at fREF
Group B
VDD
VDD
five outputs at fREF /2 or
six outputs at 2x fREF
four outputs at fREF
19
20
21
22
23
24
25
GND Q3
Q4
VDD Q5
Q6 GND
• Low output-to-output skew:
150 ps (max) within a group
TriQuint’s GA1087 is a configurable clock buffer which generates 11 outputs,
operating over a wide range of frequencies — from 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and 1/2 x the
reference clock frequency, fREF . When one of the Group A outputs
(Q5–Q10) is used as feedback to the PLL, all Group A outputs will be at
fREF , and all Group B outputs (Q0–Q4) will be at 1/2 x fREF . When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
• Near-zero propagation delay:
–350 ps +500 ps (max) or
–350 ps +700 ps (max)
• TTL-compatible with 30 mA
output drive
will be at 2x fREF and all Group B outputs will be at fREF
.
• 28-pin J-lead
surface-mount package
A very stable internal Phase-Locked Loop (PLL) provides low-jitter
operation. Completely self-contained, this PLL requires no external
capacitors or resistors. The PLL’s voltage-controlled oscillator (VCO)
has a frequency range from 280 MHz to 420 MHz. By feeding back one
of the output clocks to FBIN, the PLL continuously maintains frequency
and phase synchronization between the reference clock (REFCLK) and
each of the outputs.
TriQuint’s patented output buffer design delivers a very low output-to-
output skew of 150 ps (max). The GA1087’s symmetrical TTL outputs
are capable of sourcing and sinking 30 mA.
1
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GA1087
Functional Description
and the output used as feedback to FBIN set the divide
mode as shown in Table 1.
The core of the GA1087 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock (REFCLK)
In the test mode, the PLL is bypassed and REFCLK is
to the feedback clock (FBIN), maintaining a zero frequency connected directly to the Divide Logic block via the
difference between the two. Since one of the outputs
(Q0–Q8) is always connected to FBIN, the PLL keeps
the propagation delay between the outputs and the
reference clock within –350 ps +500 ps for the
GA1087-MC500, and within –350 ps +700 ps for the
GA1087-MC700.
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The various test modes are
outlined in Table 2. In the test mode, the frequency of
the reference clock is divided by 4, 5, or 6.
The maximum rise and fall time at the output pins is
1.4 ns. All outputs of the GA1087 are TTL-compatible
with 30 mA symmetric drive and a minimum VOH of 2.4 V.
The internal voltage-controlled oscillator (VCO) has an
operating range of 280 MHz to 420 MHz. The combi-
nation of the VCO and the Divide Logic enables the
GA1087 to operate between 24 MHz and 105 MHz.
Power Up/Reset Synchronization
After-power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
The device features six divide modes: ÷4, ÷5, ÷6, ÷8,
÷10, and ÷12. The Frequency Select pins, F0 and F1,
Table 1. Frequency Mode Selection
Feedback: Any Group A Output (Q5 – Q10)
Select Pins
F0
Reference Clock
Frequency Range
Output Frequency Range
Test
F1
Mode
Group A: Q5–Q10
Group B: Q0–Q4
0
0
0
0
1
0
0
1
0
0
1
1
÷ 4
÷ 5
70 MHz – 105 MHz
56 MHz – 84 MHz
48 MHz – 70 MHz
N.A.
70 MHz – 105 MHz
56 MHz – 84 MHz 1
48 MHz – 70 MHz
N.A.
35 MHz – 52 MHz
28 MHz – 42 MHz
24 MHz – 35 MHz
N.A.
÷ 6
Not Used
Feedback: Any Group B Output (Q0 – Q4)
Select Pins
Reference Clock
Frequency Range
Output Frequency Range
Test
F0
F1
Mode
Group A: Q5–Q10
Group B: Q0–Q4
0
0
0
0
1
0
0
1
0
0
1
1
÷ 8
÷ 10
35 MHz – 52 MHz
28 MHz – 42 MHz
24 MHz – 35 MHz
N.A.
70 MHz – 105 MHz
56 MHz – 84 MHz 1
48 MHz – 70 MHz
N.A.
35 MHz – 52 MHz
28 MHz – 42 MHz
24 MHz – 35 MHz
N.A.
÷ 12
Not Used
Notes: 1. This mode produces outputs with 40/60 duty cycle for Q5 – Q10 only.
2
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GA1087
Table 2. Test Mode Selection
Group B:
Outputs Q0–Q4
Group A:
Outputs Q5–Q10
Test
F0
F1
Mode
Ref. Clock
1
1
1
1
1
0
0
1
0
0
1
1
÷ 4
÷ 5
÷ 6
—
f REF
f REF
f REF
—
f
REF ÷ 8
f REF ÷ 4
f
f
REF ÷ 10
REF ÷ 12
—
f
REF ÷ 5
REF ÷ 6
—
f
Layout Guidelines
Multiple ground and power pins on the GA1087 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the VDD supply
pins to the nearest ground pin, as close to the chip as
possible.
Figure 2. Top Layer Layout of Power Pins
(approx. 3.3x)
V
V
DD
DD
C4
C3
Pin 1
Figure 2 shows the recommended power layout for the
GA1087. The bypass capacitors should be located on
the same side of the board as the GA1087. The VDD
traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple through
holes connect this small surface plane to an inner-layer
ground plane. The capacitors (C1–C5) are 0.1 mF.
TriQuint’s test board uses X7R temperature-stable
capacitors in 1206 SMD cases.
Ground
Plane
V
DD
C2
Pin 15
C1
C5
V
V
DD
DD
3
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GA1087
Absolute Maximum Ratings 1
Storage temperature
–65 °C to +150 °C
–55 °C to +100 °C
–0.5 V to +7.0 V
–0.5 V to (VDD + 0.5) V
–30 mA to +5 mA
θJA = 45 °C/W
Ambient temperature with power applied 2
Supply voltage to ground potential
DC input voltage
DC input current
Package thermal resistance (MQuad)
Die junction temperature
TJ = 150 °C
(VDD = +5 V + 5%, TA = 0 °C to +70 °C) 3
DC Characteristics
Limits 4
Typ
Symbol
Description
Test Conditions
Min
Max
Units
VOHT
Output HIGH voltage
VDD= Min
VIN= VIH or VIL
IOH = –30 mA
IOH = –1 mA
IOL = 30 mA
2.4
3.4
V
VOHC
VOL
Output HIGH voltage
VIN
VDD = Min
= VIH or VIL
3.2
2.0
4.1
V
V
V
V
Output LOW voltage
VIN
VDD = Min
= VIH or VIL
0.27
0.5
0.8
5
VIH
Input HIGH level
Voltage for all Inputs
Guaranteed input logical HIGH
Guaranteed input logical LOW
5
VIL
Input LOW level
Voltage for all inputs
IIL
IIH
II
Input LOW current
Input HIGH current
Input HIGH current
Power supply current
Input clamp voltage
VDD = Max
VDD = Max
VDD = Max
VDD = Max
VDD = Min
VIN = 0.40 V
VIN = 2.7 V
VIN = 5.5 V
–156
0
–400
25
µA
µA
µA
mA
V
2
1000
160
–1.2
6
IDDS
119
–0.70
VI
IIN = –18 mA
Capacitance
Symbol
Description
Test Conditions
Min
Typ
Max
Units
3,7
CIN
Input capacitance
VIN = 2.0 V at f = 1 MHz
6
pF
Notes: 1. Exceeding these parameters may damage the device.
2. Maximum ambient temperature with device not switching and unloaded.
3. These values apply to both GA1087-MC500 and GA1087-MC700.
4. Typical limits are at VDD = 5.0 V and TA = 25 °C.
5. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
6. This parameter is measured with device not switching and unloaded.
7. These parameters are not 100% tested, but are periodically sampled.
4
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GA1087
AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t CPWH
t CPWL
t IR
CLK pulse width HIGH
Figure 4
Figure 4
3
3
---
---
—
—
—
ns
ns
ns
CLK pulse width LOW
Input rise time (0.8 V - 2.0 V)
—
2.0
Symbol Input Clock (Q0–Q10)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t OR,t OF
Rise/fall time (0.8 V – 2.0 V)
Figure 4
350
–850
–1050
—
—
–350
–350
60
1400
+150
+350
150
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
µs
2
t PD1
CLK ↑ to FBIN ↑ (GA1087-MC500)
CLK ↑ to FBIN ↑ (GA1087-MC700)
Rise–rise, fall–fall (within group)
Rise–rise, fall–fall (group-to-group, aligned)
Figure 4
2
t PD2
Figure 4
3
t SKEW1
t SKEW2
t SKEW3
t SKEW4
Figure 5
3
3
3
Figure 6 (skew2 takes into account skew1)
—
75
350
Rise–rise, fall–fall (group-to-group, non-aligned) Figure 7 (skew3 takes into account skews1, 2)
—
—
—
650
Rise–fall, fall–rise
Duty-cycle Variation
Period-to-Period Jitter
Random Jitter
Figure 8 (skew4 takes into account skew3)
—
1200
+1000
200
4
t CYC
Figure 4
Figure 4
Figure 4
–1000
—
0
5
t JP
80
5
t JR
—
190
10
400
6
t SYNC
Synchronization Time
—
500
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because
the input duty cycle can vary.
while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock.
t
JP is the jitter on the output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
Y
+5 V
R1
+5 V
R1
50 Ω
X
Z
+5 V
R1
Q0
Q1
Q2
•
•
•
FBIN
CLK
R2
R2
•
•
•
•
R2
+5 V
R1
+5 V
R1
Z
•
Q10
R2
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y + Z = X
5
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GA1087
Switching Waveforms
Figure 4. General Timing
t
t
CPW
CPW
REFCLK
FBIN
t
t
JR
PD1,2
t
PERIOD
Q0 – Q10
(INDIVIDUALLY)
t
JP
Figure 5. tSKEW1
Figure 7. tSKEW3 (For Group B Feedback)
1
Group B
Group B
Period =
f
REFCLK
f = 2x f
REF
Group A
t
1
t
t
t
SKEW1
SKEW1
SKEW1
Period
2
t
SKEW3 =
– t
1
Group A
Group A
t
SKEW1
Figure 6. tSKEW2
Figure 8. tSKEW4
1
Period =
f
f = f
Group B
REFCLK
REF
Group B
t
2
f = 2x f
REF
Group A
Group A
t
t
4
3
t
SKEW2
Period
2
Period
4
Period
4
t
SKEW4 =
– t
– t
3
=
– t
4
=
2
6
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GA1087
28-Pin MQuad J-Leaded Package Mechanical Specification
(All dimensions in inches)
.172 ±.005
.040 MIN
.490 ±.005
.132 ±.005
.445 ±.005
.045
X 45°
PIN 1
.490
.410
±.015
±.005
8
22
.018
.028
.445
±.005
.445
±.005
.050 TYP.
0.125
VENT PLUG
15
.060
.104
±.005
.015
X 45°
.050 TYP.
NON-ACCUM.
28-Pin MQuad Pin Description
Pin #
Pin Name
Description
I/O
Pin #
Pin Name
Description
I/O
1
2
GND
Q9
Ground
—
O
O
—
—
I
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
Q1
Ground
Output Clock 9 (A5)
Output Clock 10 (A6)
+5 V
Output Clock 1 (B2)
Output Clock 2 (B3)
+5 V
3
Q10
VDD
GND
F0
Q2
4
VDD
GND
Q3
5
Ground
Ground
6
Frequency Select 0
Frequency Select 1
Ground
Output Clock 3 (B4)
Output Clock 4 (B5)
+5 V
7
F1
I
Q4
8
GND
REFCLK
GND
FBIN
TEST
VDD
Q0
—
I
VDD
Q5
9
Reference Clock
Ground
Output Clock 5 (A1)
Output Clock 6 (A2)
Ground
10
11
12
13
14
—
I
Q6
Feedback In
Test
GND
VDD
Q7
I
+5 V
+5 V
—
O
Output Clock 7 (A3)
Output Clock 8 (A4)
Output Clock 0 (B1)
Q8
7
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GA1087
Output Characteristics
These output characteristics are provided for modeling
purposes only. TriQuint does not guarantee the
information in these tables and figures.
The IV characteristics, transition times, package
characteristics, device and bond wire-characteristics
for the QA1087 are described in Tables 4 through 9 and
Figures 9 through 11.
Figure 9. IOH vs.VOH
Figure 10. IOL vs.VOL
HIGH
LOW
0.0
1.0
2.0
3.0
4.0
5.0
160
0
-20
VOL min
VOL max
140
120
100
80
VOH min
VOHmax
-40
-60
-80
60
-100
-120
-140
-160
40
20
0
0.0
1.0
2.0
Volts
3.0
4.0
5.0
Volts
Table 4. IOH vs.VOH
VOL
Table 5. IOL vs.VOL
VOL
IOL min (mA)
IOL max (mA)
IOL min (mA)
IOL max (mA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
8.0
9.0
10.0
–70
–70
–68
–65
–59
–48
–29
0
–160
–157
–152
–142
–130
–106
–79
–42
0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
–145
–135
–115
–90
–40
0
–435
–410
–350
–265
–120
0
0.5
37
97
1.0
49
140
155
157
159
160
160
160
160
160
160
0
1.5
53
0
0
2.0
54
0
0
2.5
54
0
0
3.0
54
0
0
3.5
54
0
0
4.0
54
0
1
4.5
54
0
5
5.0
54
10.0
54
Notes: 1. These are worst–case corners for process, voltage,
and temperature.
2. Includes diode to ground current.
8
For additional information and latest specifications, see our website: www.triquint.com
GA1087
Table 6. Above-VDD and Below-Ground
Characteristics
Table 9. Rise and Fall Times
(Into 0 pF, 50 Ohms to 1.5 V)
Time (ns) TR min (V) TR max (V) TF min (V) TF max (V)
Diode to GND
Diode Stack to VDD
V
0.0
I (mA)
0
V
I (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
0.15
0.15
0.16
0.18
0.23
0.26
0.34
0.46
0.67
0.89
1.12
1.32
1.50
1.73
1.93
2.15
2.75
2.58
2.75
2.90
3.02
3.12
3.17
3.19
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
0.32
0.32
0.32
0.32
0.32
0.32
0.32
0.34
0.39
0.49
0.63
0.86
1.09
1.27
1.45
1.64
2.23
2.00
2.23
2.41
2.50
2.64
2.77
2.86
2.95
2.99
3.02
3.02
3.04
3.04
3.04
3.04
3.04
3.04
3.04
3.20
3.20
3.06
2.86
2.62
2.38
2.17
2.00
1.85
1.69
1.52
1.38
1.26
1.12
0.96
0.83
0.52
0.61
0.52
0.45
0.39
0.33
0.29
0.24
0.21
0.19
0.17
0.16
0.16
0.15
0.15
0.15
0.15
0.15
0.15
3.04
3.04
2.95
2.90
2.68
2.50
2.36
2.22
2.09
1.95
1.86
1.68
1.59
1.49
1.36
1.23
0.95
1.00
0.95
0.91
0.86
0.77
0.73
0.68
0.64
0.59
0.55
0.53
0.50
0.45
0.41
0.40
0.37
0.36
0.32
5.0
0
0
0
0
0
1
5
9
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–2.0
–2.5
–3.0
0
6.0
0
7.0
–5
8.0
–15
–35
–55
–75
–300
–350
–360
9.0
10.0
11.0
12.0
Note:
TriQuint does not guarantee diode operation for purposes
other than ESD protection.
Figure 11. Output Model
L1
L2
DIE
C1
OUTPUT
C2
Table 7. Device and Bond-Wire Characteristics
(Estimates)
L1
C1
2 nH
10 pF
Table 8. 28-Pin MQuad Package Characteristics
L1
C1
1.85 nH
0.40 pF
9
For additional information and latest specifications, see our website: www.triquint.com
GA1087
Ordering Information
To order, please specify as shown below:
GA1087-MC nnn
11-Output Configurable Clock Buffer
Propagation delay skew:
Note: All parts are marked
as MC500. MC700 parts have
a “2” added to the marking.
500
700
–350 ps ± 500 ps
–350 ps ± 700 ps
Temperature range: 0 °C to 70 °C (Commercial)
Package: MQuad
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: sales@tqs.com
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
10
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